tegra20-seaboard.dts 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include <dt-bindings/input/input.h>
  4. #include "tegra20.dtsi"
  5. / {
  6. model = "NVIDIA Seaboard";
  7. compatible = "nvidia,seaboard", "nvidia,tegra20";
  8. aliases {
  9. rtc0 = "/i2c@7000d000/tps6586x@34";
  10. rtc1 = "/rtc@7000e000";
  11. serial0 = &uartd;
  12. };
  13. chosen {
  14. stdout-path = "serial0:115200n8";
  15. };
  16. memory@0 {
  17. reg = <0x00000000 0x40000000>;
  18. };
  19. host1x@50000000 {
  20. dc@54200000 {
  21. rgb {
  22. status = "okay";
  23. nvidia,panel = <&panel>;
  24. };
  25. };
  26. hdmi@54280000 {
  27. status = "okay";
  28. vdd-supply = <&hdmi_vdd_reg>;
  29. pll-supply = <&hdmi_pll_reg>;
  30. hdmi-supply = <&vdd_hdmi>;
  31. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  32. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  33. GPIO_ACTIVE_HIGH>;
  34. };
  35. };
  36. pinmux@70000014 {
  37. pinctrl-names = "default";
  38. pinctrl-0 = <&state_default>;
  39. state_default: pinmux {
  40. ata {
  41. nvidia,pins = "ata";
  42. nvidia,function = "ide";
  43. };
  44. atb {
  45. nvidia,pins = "atb", "gma", "gme";
  46. nvidia,function = "sdio4";
  47. };
  48. atc {
  49. nvidia,pins = "atc";
  50. nvidia,function = "nand";
  51. };
  52. atd {
  53. nvidia,pins = "atd", "ate", "gmb", "spia",
  54. "spib", "spic";
  55. nvidia,function = "gmi";
  56. };
  57. cdev1 {
  58. nvidia,pins = "cdev1";
  59. nvidia,function = "plla_out";
  60. };
  61. cdev2 {
  62. nvidia,pins = "cdev2";
  63. nvidia,function = "pllp_out4";
  64. };
  65. crtp {
  66. nvidia,pins = "crtp", "lm1";
  67. nvidia,function = "crt";
  68. };
  69. csus {
  70. nvidia,pins = "csus";
  71. nvidia,function = "vi_sensor_clk";
  72. };
  73. dap1 {
  74. nvidia,pins = "dap1";
  75. nvidia,function = "dap1";
  76. };
  77. dap2 {
  78. nvidia,pins = "dap2";
  79. nvidia,function = "dap2";
  80. };
  81. dap3 {
  82. nvidia,pins = "dap3";
  83. nvidia,function = "dap3";
  84. };
  85. dap4 {
  86. nvidia,pins = "dap4";
  87. nvidia,function = "dap4";
  88. };
  89. dta {
  90. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  91. nvidia,function = "vi";
  92. };
  93. dtf {
  94. nvidia,pins = "dtf";
  95. nvidia,function = "i2c3";
  96. };
  97. gmc {
  98. nvidia,pins = "gmc";
  99. nvidia,function = "uartd";
  100. };
  101. gmd {
  102. nvidia,pins = "gmd";
  103. nvidia,function = "sflash";
  104. };
  105. gpu {
  106. nvidia,pins = "gpu";
  107. nvidia,function = "pwm";
  108. };
  109. gpu7 {
  110. nvidia,pins = "gpu7";
  111. nvidia,function = "rtck";
  112. };
  113. gpv {
  114. nvidia,pins = "gpv", "slxa", "slxk";
  115. nvidia,function = "pcie";
  116. };
  117. hdint {
  118. nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
  119. "lsck", "lsda";
  120. nvidia,function = "hdmi";
  121. };
  122. i2cp {
  123. nvidia,pins = "i2cp";
  124. nvidia,function = "i2cp";
  125. };
  126. irrx {
  127. nvidia,pins = "irrx", "irtx";
  128. nvidia,function = "uartb";
  129. };
  130. kbca {
  131. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  132. "kbce", "kbcf";
  133. nvidia,function = "kbc";
  134. };
  135. lcsn {
  136. nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
  137. "lsdi", "lvp0";
  138. nvidia,function = "rsvd4";
  139. };
  140. ld0 {
  141. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  142. "ld5", "ld6", "ld7", "ld8", "ld9",
  143. "ld10", "ld11", "ld12", "ld13", "ld14",
  144. "ld15", "ld16", "ld17", "ldi", "lhp0",
  145. "lhp1", "lhp2", "lhs", "lpp", "lsc0",
  146. "lspi", "lvp1", "lvs";
  147. nvidia,function = "displaya";
  148. };
  149. owc {
  150. nvidia,pins = "owc", "spdi", "spdo", "uac";
  151. nvidia,function = "rsvd2";
  152. };
  153. pmc {
  154. nvidia,pins = "pmc";
  155. nvidia,function = "pwr_on";
  156. };
  157. rm {
  158. nvidia,pins = "rm";
  159. nvidia,function = "i2c1";
  160. };
  161. sdb {
  162. nvidia,pins = "sdb", "sdc", "sdd";
  163. nvidia,function = "sdio3";
  164. };
  165. sdio1 {
  166. nvidia,pins = "sdio1";
  167. nvidia,function = "sdio1";
  168. };
  169. slxc {
  170. nvidia,pins = "slxc", "slxd";
  171. nvidia,function = "spdif";
  172. };
  173. spid {
  174. nvidia,pins = "spid", "spie", "spif";
  175. nvidia,function = "spi1";
  176. };
  177. spig {
  178. nvidia,pins = "spig", "spih";
  179. nvidia,function = "spi2_alt";
  180. };
  181. uaa {
  182. nvidia,pins = "uaa", "uab", "uda";
  183. nvidia,function = "ulpi";
  184. };
  185. uad {
  186. nvidia,pins = "uad";
  187. nvidia,function = "irda";
  188. };
  189. uca {
  190. nvidia,pins = "uca", "ucb";
  191. nvidia,function = "uartc";
  192. };
  193. conf_ata {
  194. nvidia,pins = "ata", "atb", "atc", "atd",
  195. "cdev1", "cdev2", "dap1", "dap2",
  196. "dap4", "ddc", "dtf", "gma", "gmc", "gmd",
  197. "gme", "gpu", "gpu7", "i2cp", "irrx",
  198. "irtx", "pta", "rm", "sdc", "sdd",
  199. "slxd", "slxk", "spdi", "spdo", "uac",
  200. "uad", "uca", "ucb", "uda";
  201. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  202. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  203. };
  204. conf_ate {
  205. nvidia,pins = "ate", "csus", "dap3",
  206. "gpv", "owc", "slxc", "spib", "spid",
  207. "spie";
  208. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  209. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  210. };
  211. conf_ck32 {
  212. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  213. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  214. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  215. };
  216. conf_crtp {
  217. nvidia,pins = "crtp", "gmb", "slxa", "spia",
  218. "spig", "spih";
  219. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  220. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  221. };
  222. conf_dta {
  223. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  224. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  225. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  226. };
  227. conf_dte {
  228. nvidia,pins = "dte", "spif";
  229. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  230. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  231. };
  232. conf_hdint {
  233. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  234. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  235. "lvp0";
  236. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  237. };
  238. conf_kbca {
  239. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  240. "kbce", "kbcf", "sdio1", "spic", "uaa",
  241. "uab";
  242. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  243. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  244. };
  245. conf_lc {
  246. nvidia,pins = "lc", "ls";
  247. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  248. };
  249. conf_ld0 {
  250. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  251. "ld5", "ld6", "ld7", "ld8", "ld9",
  252. "ld10", "ld11", "ld12", "ld13", "ld14",
  253. "ld15", "ld16", "ld17", "ldi", "lhp0",
  254. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  255. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  256. "lvs", "pmc", "sdb";
  257. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  258. };
  259. conf_ld17_0 {
  260. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  261. "ld23_22";
  262. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  263. };
  264. drive_sdio1 {
  265. nvidia,pins = "drive_sdio1";
  266. nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
  267. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  268. nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
  269. nvidia,pull-down-strength = <31>;
  270. nvidia,pull-up-strength = <31>;
  271. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  272. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  273. };
  274. };
  275. state_i2cmux_ddc: pinmux_i2cmux_ddc {
  276. ddc {
  277. nvidia,pins = "ddc";
  278. nvidia,function = "i2c2";
  279. };
  280. pta {
  281. nvidia,pins = "pta";
  282. nvidia,function = "rsvd4";
  283. };
  284. };
  285. state_i2cmux_pta: pinmux_i2cmux_pta {
  286. ddc {
  287. nvidia,pins = "ddc";
  288. nvidia,function = "rsvd4";
  289. };
  290. pta {
  291. nvidia,pins = "pta";
  292. nvidia,function = "i2c2";
  293. };
  294. };
  295. state_i2cmux_idle: pinmux_i2cmux_idle {
  296. ddc {
  297. nvidia,pins = "ddc";
  298. nvidia,function = "rsvd4";
  299. };
  300. pta {
  301. nvidia,pins = "pta";
  302. nvidia,function = "rsvd4";
  303. };
  304. };
  305. };
  306. i2s@70002800 {
  307. status = "okay";
  308. };
  309. serial@70006300 {
  310. status = "okay";
  311. };
  312. pwm: pwm@7000a000 {
  313. status = "okay";
  314. };
  315. i2c@7000c000 {
  316. status = "okay";
  317. clock-frequency = <400000>;
  318. wm8903: wm8903@1a {
  319. compatible = "wlf,wm8903";
  320. reg = <0x1a>;
  321. interrupt-parent = <&gpio>;
  322. interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
  323. gpio-controller;
  324. #gpio-cells = <2>;
  325. micdet-cfg = <0>;
  326. micdet-delay = <100>;
  327. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  328. };
  329. /* ALS and proximity sensor */
  330. isl29018@44 {
  331. compatible = "isil,isl29018";
  332. reg = <0x44>;
  333. interrupt-parent = <&gpio>;
  334. interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
  335. };
  336. gyrometer@68 {
  337. compatible = "invensense,mpu3050";
  338. reg = <0x68>;
  339. interrupt-parent = <&gpio>;
  340. interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
  341. };
  342. };
  343. i2c@7000c400 {
  344. status = "okay";
  345. clock-frequency = <100000>;
  346. };
  347. i2cmux {
  348. compatible = "i2c-mux-pinctrl";
  349. #address-cells = <1>;
  350. #size-cells = <0>;
  351. i2c-parent = <&{/i2c@7000c400}>;
  352. pinctrl-names = "ddc", "pta", "idle";
  353. pinctrl-0 = <&state_i2cmux_ddc>;
  354. pinctrl-1 = <&state_i2cmux_pta>;
  355. pinctrl-2 = <&state_i2cmux_idle>;
  356. hdmi_ddc: i2c@0 {
  357. reg = <0>;
  358. #address-cells = <1>;
  359. #size-cells = <0>;
  360. };
  361. lvds_ddc: i2c@1 {
  362. reg = <1>;
  363. #address-cells = <1>;
  364. #size-cells = <0>;
  365. smart-battery@b {
  366. compatible = "ti,bq20z75", "sbs,sbs-battery";
  367. reg = <0xb>;
  368. sbs,i2c-retry-count = <2>;
  369. sbs,poll-retry-count = <10>;
  370. };
  371. };
  372. };
  373. i2c@7000c500 {
  374. status = "okay";
  375. clock-frequency = <400000>;
  376. };
  377. i2c@7000d000 {
  378. status = "okay";
  379. clock-frequency = <400000>;
  380. magnetometer@c {
  381. compatible = "asahi-kasei,ak8975";
  382. reg = <0xc>;
  383. interrupt-parent = <&gpio>;
  384. interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
  385. };
  386. pmic: tps6586x@34 {
  387. compatible = "ti,tps6586x";
  388. reg = <0x34>;
  389. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  390. ti,system-power-controller;
  391. #gpio-cells = <2>;
  392. gpio-controller;
  393. sys-supply = <&vdd_5v0_reg>;
  394. vin-sm0-supply = <&sys_reg>;
  395. vin-sm1-supply = <&sys_reg>;
  396. vin-sm2-supply = <&sys_reg>;
  397. vinldo01-supply = <&sm2_reg>;
  398. vinldo23-supply = <&sm2_reg>;
  399. vinldo4-supply = <&sm2_reg>;
  400. vinldo678-supply = <&sm2_reg>;
  401. vinldo9-supply = <&sm2_reg>;
  402. regulators {
  403. sys_reg: sys {
  404. regulator-name = "vdd_sys";
  405. regulator-always-on;
  406. };
  407. vdd_core: sm0 {
  408. regulator-name = "vdd_sm0,vdd_core";
  409. regulator-min-microvolt = <1300000>;
  410. regulator-max-microvolt = <1300000>;
  411. regulator-always-on;
  412. };
  413. sm1 {
  414. regulator-name = "vdd_sm1,vdd_cpu";
  415. regulator-min-microvolt = <1125000>;
  416. regulator-max-microvolt = <1125000>;
  417. regulator-always-on;
  418. };
  419. sm2_reg: sm2 {
  420. regulator-name = "vdd_sm2,vin_ldo*";
  421. regulator-min-microvolt = <3700000>;
  422. regulator-max-microvolt = <3700000>;
  423. regulator-always-on;
  424. };
  425. /* LDO0 is not connected to anything */
  426. ldo1 {
  427. regulator-name = "vdd_ldo1,avdd_pll*";
  428. regulator-min-microvolt = <1100000>;
  429. regulator-max-microvolt = <1100000>;
  430. regulator-always-on;
  431. };
  432. ldo2 {
  433. regulator-name = "vdd_ldo2,vdd_rtc";
  434. regulator-min-microvolt = <1200000>;
  435. regulator-max-microvolt = <1200000>;
  436. };
  437. ldo3 {
  438. regulator-name = "vdd_ldo3,avdd_usb*";
  439. regulator-min-microvolt = <3300000>;
  440. regulator-max-microvolt = <3300000>;
  441. regulator-always-on;
  442. };
  443. ldo4 {
  444. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  445. regulator-min-microvolt = <1800000>;
  446. regulator-max-microvolt = <1800000>;
  447. regulator-always-on;
  448. };
  449. ldo5 {
  450. regulator-name = "vdd_ldo5,vcore_mmc";
  451. regulator-min-microvolt = <2850000>;
  452. regulator-max-microvolt = <2850000>;
  453. regulator-always-on;
  454. };
  455. ldo6 {
  456. regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
  457. regulator-min-microvolt = <1800000>;
  458. regulator-max-microvolt = <1800000>;
  459. };
  460. hdmi_vdd_reg: ldo7 {
  461. regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
  462. regulator-min-microvolt = <3300000>;
  463. regulator-max-microvolt = <3300000>;
  464. };
  465. hdmi_pll_reg: ldo8 {
  466. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  467. regulator-min-microvolt = <1800000>;
  468. regulator-max-microvolt = <1800000>;
  469. };
  470. ldo9 {
  471. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  472. regulator-min-microvolt = <2850000>;
  473. regulator-max-microvolt = <2850000>;
  474. regulator-always-on;
  475. };
  476. ldo_rtc {
  477. regulator-name = "vdd_rtc_out,vdd_cell";
  478. regulator-min-microvolt = <3300000>;
  479. regulator-max-microvolt = <3300000>;
  480. regulator-always-on;
  481. };
  482. };
  483. };
  484. temperature-sensor@4c {
  485. compatible = "onnn,nct1008";
  486. reg = <0x4c>;
  487. };
  488. };
  489. kbc@7000e200 {
  490. status = "okay";
  491. nvidia,debounce-delay-ms = <32>;
  492. nvidia,repeat-delay-ms = <160>;
  493. nvidia,ghost-filter;
  494. nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  495. nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
  496. linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
  497. MATRIX_KEY(0x00, 0x03, KEY_S)
  498. MATRIX_KEY(0x00, 0x04, KEY_A)
  499. MATRIX_KEY(0x00, 0x05, KEY_Z)
  500. MATRIX_KEY(0x00, 0x07, KEY_FN)
  501. MATRIX_KEY(0x01, 0x07, KEY_LEFTMETA)
  502. MATRIX_KEY(0x02, 0x06, KEY_RIGHTALT)
  503. MATRIX_KEY(0x02, 0x07, KEY_LEFTALT)
  504. MATRIX_KEY(0x03, 0x00, KEY_5)
  505. MATRIX_KEY(0x03, 0x01, KEY_4)
  506. MATRIX_KEY(0x03, 0x02, KEY_R)
  507. MATRIX_KEY(0x03, 0x03, KEY_E)
  508. MATRIX_KEY(0x03, 0x04, KEY_F)
  509. MATRIX_KEY(0x03, 0x05, KEY_D)
  510. MATRIX_KEY(0x03, 0x06, KEY_X)
  511. MATRIX_KEY(0x04, 0x00, KEY_7)
  512. MATRIX_KEY(0x04, 0x01, KEY_6)
  513. MATRIX_KEY(0x04, 0x02, KEY_T)
  514. MATRIX_KEY(0x04, 0x03, KEY_H)
  515. MATRIX_KEY(0x04, 0x04, KEY_G)
  516. MATRIX_KEY(0x04, 0x05, KEY_V)
  517. MATRIX_KEY(0x04, 0x06, KEY_C)
  518. MATRIX_KEY(0x04, 0x07, KEY_SPACE)
  519. MATRIX_KEY(0x05, 0x00, KEY_9)
  520. MATRIX_KEY(0x05, 0x01, KEY_8)
  521. MATRIX_KEY(0x05, 0x02, KEY_U)
  522. MATRIX_KEY(0x05, 0x03, KEY_Y)
  523. MATRIX_KEY(0x05, 0x04, KEY_J)
  524. MATRIX_KEY(0x05, 0x05, KEY_N)
  525. MATRIX_KEY(0x05, 0x06, KEY_B)
  526. MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
  527. MATRIX_KEY(0x06, 0x00, KEY_MINUS)
  528. MATRIX_KEY(0x06, 0x01, KEY_0)
  529. MATRIX_KEY(0x06, 0x02, KEY_O)
  530. MATRIX_KEY(0x06, 0x03, KEY_I)
  531. MATRIX_KEY(0x06, 0x04, KEY_L)
  532. MATRIX_KEY(0x06, 0x05, KEY_K)
  533. MATRIX_KEY(0x06, 0x06, KEY_COMMA)
  534. MATRIX_KEY(0x06, 0x07, KEY_M)
  535. MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
  536. MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
  537. MATRIX_KEY(0x07, 0x03, KEY_ENTER)
  538. MATRIX_KEY(0x07, 0x07, KEY_MENU)
  539. MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT)
  540. MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT)
  541. MATRIX_KEY(0x09, 0x05, KEY_RIGHTCTRL)
  542. MATRIX_KEY(0x09, 0x07, KEY_LEFTCTRL)
  543. MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
  544. MATRIX_KEY(0x0B, 0x01, KEY_P)
  545. MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
  546. MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
  547. MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
  548. MATRIX_KEY(0x0B, 0x05, KEY_DOT)
  549. MATRIX_KEY(0x0C, 0x00, KEY_F10)
  550. MATRIX_KEY(0x0C, 0x01, KEY_F9)
  551. MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
  552. MATRIX_KEY(0x0C, 0x03, KEY_3)
  553. MATRIX_KEY(0x0C, 0x04, KEY_2)
  554. MATRIX_KEY(0x0C, 0x05, KEY_UP)
  555. MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
  556. MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
  557. MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
  558. MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
  559. MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
  560. MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
  561. MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
  562. MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
  563. MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
  564. MATRIX_KEY(0x0E, 0x00, KEY_F11)
  565. MATRIX_KEY(0x0E, 0x01, KEY_F12)
  566. MATRIX_KEY(0x0E, 0x02, KEY_F8)
  567. MATRIX_KEY(0x0E, 0x03, KEY_Q)
  568. MATRIX_KEY(0x0E, 0x04, KEY_F4)
  569. MATRIX_KEY(0x0E, 0x05, KEY_F3)
  570. MATRIX_KEY(0x0E, 0x06, KEY_1)
  571. MATRIX_KEY(0x0E, 0x07, KEY_F7)
  572. MATRIX_KEY(0x0F, 0x00, KEY_ESC)
  573. MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
  574. MATRIX_KEY(0x0F, 0x02, KEY_F5)
  575. MATRIX_KEY(0x0F, 0x03, KEY_TAB)
  576. MATRIX_KEY(0x0F, 0x04, KEY_F1)
  577. MATRIX_KEY(0x0F, 0x05, KEY_F2)
  578. MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
  579. MATRIX_KEY(0x0F, 0x07, KEY_F6)
  580. /* Software Handled Function Keys */
  581. MATRIX_KEY(0x14, 0x00, KEY_KP7)
  582. MATRIX_KEY(0x15, 0x00, KEY_KP9)
  583. MATRIX_KEY(0x15, 0x01, KEY_KP8)
  584. MATRIX_KEY(0x15, 0x02, KEY_KP4)
  585. MATRIX_KEY(0x15, 0x04, KEY_KP1)
  586. MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
  587. MATRIX_KEY(0x16, 0x02, KEY_KP6)
  588. MATRIX_KEY(0x16, 0x03, KEY_KP5)
  589. MATRIX_KEY(0x16, 0x04, KEY_KP3)
  590. MATRIX_KEY(0x16, 0x05, KEY_KP2)
  591. MATRIX_KEY(0x16, 0x07, KEY_KP0)
  592. MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
  593. MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
  594. MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
  595. MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
  596. MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
  597. MATRIX_KEY(0x1D, 0x03, KEY_HOME)
  598. MATRIX_KEY(0x1D, 0x04, KEY_END)
  599. MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN)
  600. MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
  601. MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP)
  602. MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
  603. MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
  604. MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
  605. MATRIX_KEY(0x1F, 0x04, KEY_HELP)>;
  606. };
  607. pmc@7000e400 {
  608. nvidia,invert-interrupt;
  609. nvidia,suspend-mode = <1>;
  610. nvidia,cpu-pwr-good-time = <5000>;
  611. nvidia,cpu-pwr-off-time = <5000>;
  612. nvidia,core-pwr-good-time = <3845 3845>;
  613. nvidia,core-pwr-off-time = <3875>;
  614. nvidia,sys-clock-req-active-high;
  615. core-supply = <&vdd_core>;
  616. };
  617. memory-controller@7000f400 {
  618. emc-table@190000 {
  619. reg = <190000>;
  620. compatible = "nvidia,tegra20-emc-table";
  621. clock-frequency = <190000>;
  622. nvidia,emc-registers = <0x0000000c 0x00000026
  623. 0x00000009 0x00000003 0x00000004 0x00000004
  624. 0x00000002 0x0000000c 0x00000003 0x00000003
  625. 0x00000002 0x00000001 0x00000004 0x00000005
  626. 0x00000004 0x00000009 0x0000000d 0x0000059f
  627. 0x00000000 0x00000003 0x00000003 0x00000003
  628. 0x00000003 0x00000001 0x0000000b 0x000000c8
  629. 0x00000003 0x00000007 0x00000004 0x0000000f
  630. 0x00000002 0x00000000 0x00000000 0x00000002
  631. 0x00000000 0x00000000 0x00000083 0xa06204ae
  632. 0x007dc010 0x00000000 0x00000000 0x00000000
  633. 0x00000000 0x00000000 0x00000000 0x00000000>;
  634. };
  635. emc-table@380000 {
  636. reg = <380000>;
  637. compatible = "nvidia,tegra20-emc-table";
  638. clock-frequency = <380000>;
  639. nvidia,emc-registers = <0x00000017 0x0000004b
  640. 0x00000012 0x00000006 0x00000004 0x00000005
  641. 0x00000003 0x0000000c 0x00000006 0x00000006
  642. 0x00000003 0x00000001 0x00000004 0x00000005
  643. 0x00000004 0x00000009 0x0000000d 0x00000b5f
  644. 0x00000000 0x00000003 0x00000003 0x00000006
  645. 0x00000006 0x00000001 0x00000011 0x000000c8
  646. 0x00000003 0x0000000e 0x00000007 0x0000000f
  647. 0x00000002 0x00000000 0x00000000 0x00000002
  648. 0x00000000 0x00000000 0x00000083 0xe044048b
  649. 0x007d8010 0x00000000 0x00000000 0x00000000
  650. 0x00000000 0x00000000 0x00000000 0x00000000>;
  651. };
  652. };
  653. usb@c5000000 {
  654. status = "okay";
  655. dr_mode = "otg";
  656. };
  657. usb-phy@c5000000 {
  658. status = "okay";
  659. vbus-supply = <&vbus_reg>;
  660. dr_mode = "otg";
  661. };
  662. usb@c5004000 {
  663. status = "okay";
  664. };
  665. usb-phy@c5004000 {
  666. status = "okay";
  667. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  668. GPIO_ACTIVE_LOW>;
  669. };
  670. usb@c5008000 {
  671. status = "okay";
  672. };
  673. usb-phy@c5008000 {
  674. status = "okay";
  675. };
  676. mmc@c8000000 {
  677. status = "okay";
  678. power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  679. bus-width = <4>;
  680. keep-power-in-suspend;
  681. };
  682. mmc@c8000400 {
  683. status = "okay";
  684. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  685. wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  686. power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
  687. bus-width = <4>;
  688. };
  689. mmc@c8000600 {
  690. status = "okay";
  691. bus-width = <8>;
  692. non-removable;
  693. };
  694. backlight: backlight {
  695. compatible = "pwm-backlight";
  696. enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
  697. power-supply = <&vdd_bl_reg>;
  698. pwms = <&pwm 2 5000000>;
  699. brightness-levels = <0 4 8 16 32 64 128 255>;
  700. default-brightness-level = <6>;
  701. };
  702. clk32k_in: clock-32k {
  703. compatible = "fixed-clock";
  704. clock-frequency = <32768>;
  705. #clock-cells = <0>;
  706. };
  707. gpio-keys {
  708. compatible = "gpio-keys";
  709. key-power {
  710. label = "Power";
  711. gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  712. linux,code = <KEY_POWER>;
  713. wakeup-source;
  714. };
  715. switch-lid {
  716. label = "Lid";
  717. gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
  718. linux,input-type = <5>; /* EV_SW */
  719. linux,code = <0>; /* SW_LID */
  720. debounce-interval = <1>;
  721. wakeup-source;
  722. };
  723. };
  724. panel: panel {
  725. compatible = "chunghwa,claa101wa01a";
  726. power-supply = <&vdd_pnl_reg>;
  727. enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
  728. backlight = <&backlight>;
  729. ddc-i2c-bus = <&lvds_ddc>;
  730. };
  731. vdd_5v0_reg: regulator-5v0 {
  732. compatible = "regulator-fixed";
  733. regulator-name = "vdd_5v0";
  734. regulator-min-microvolt = <5000000>;
  735. regulator-max-microvolt = <5000000>;
  736. regulator-always-on;
  737. };
  738. regulator-1v5 {
  739. compatible = "regulator-fixed";
  740. regulator-name = "vdd_1v5";
  741. regulator-min-microvolt = <1500000>;
  742. regulator-max-microvolt = <1500000>;
  743. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  744. };
  745. regulator-1v2 {
  746. compatible = "regulator-fixed";
  747. regulator-name = "vdd_1v2";
  748. regulator-min-microvolt = <1200000>;
  749. regulator-max-microvolt = <1200000>;
  750. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  751. enable-active-high;
  752. };
  753. vbus_reg: regulator-vbus {
  754. compatible = "regulator-fixed";
  755. regulator-name = "vdd_vbus_wup1";
  756. regulator-min-microvolt = <5000000>;
  757. regulator-max-microvolt = <5000000>;
  758. enable-active-high;
  759. gpio = <&gpio TEGRA_GPIO(D, 0) 0>;
  760. regulator-always-on;
  761. regulator-boot-on;
  762. };
  763. vdd_pnl_reg: regulator-pnl {
  764. compatible = "regulator-fixed";
  765. regulator-name = "vdd_pnl";
  766. regulator-min-microvolt = <2800000>;
  767. regulator-max-microvolt = <2800000>;
  768. gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
  769. enable-active-high;
  770. };
  771. vdd_bl_reg: regulator-bl {
  772. compatible = "regulator-fixed";
  773. regulator-name = "vdd_bl";
  774. regulator-min-microvolt = <2800000>;
  775. regulator-max-microvolt = <2800000>;
  776. gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
  777. enable-active-high;
  778. };
  779. vdd_hdmi: regulator-hdmi {
  780. compatible = "regulator-fixed";
  781. regulator-name = "VDDIO_HDMI";
  782. regulator-min-microvolt = <5000000>;
  783. regulator-max-microvolt = <5000000>;
  784. gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
  785. enable-active-high;
  786. vin-supply = <&vdd_5v0_reg>;
  787. };
  788. sound {
  789. compatible = "nvidia,tegra-audio-wm8903-seaboard",
  790. "nvidia,tegra-audio-wm8903";
  791. nvidia,model = "NVIDIA Tegra Seaboard";
  792. nvidia,audio-routing =
  793. "Headphone Jack", "HPOUTR",
  794. "Headphone Jack", "HPOUTL",
  795. "Int Spk", "ROP",
  796. "Int Spk", "RON",
  797. "Int Spk", "LOP",
  798. "Int Spk", "LON",
  799. "Mic Jack", "MICBIAS",
  800. "IN1R", "Mic Jack";
  801. nvidia,i2s-controller = <&tegra_i2s1>;
  802. nvidia,audio-codec = <&wm8903>;
  803. nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
  804. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_LOW>;
  805. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  806. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  807. <&tegra_car TEGRA20_CLK_CDEV1>;
  808. clock-names = "pll_a", "pll_a_out0", "mclk";
  809. };
  810. };