tegra20-paz00.dts 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/thermal/thermal.h>
  5. #include "tegra20.dtsi"
  6. #include "tegra20-cpu-opp.dtsi"
  7. #include "tegra20-cpu-opp-microvolt.dtsi"
  8. / {
  9. model = "Toshiba AC100 / Dynabook AZ";
  10. compatible = "compal,paz00", "nvidia,tegra20";
  11. aliases {
  12. mmc0 = &sdmmc4; /* eMMC */
  13. mmc1 = &sdmmc1; /* MicroSD */
  14. rtc0 = "/i2c@7000d000/tps6586x@34";
  15. rtc1 = "/rtc@7000e000";
  16. serial0 = &uarta;
  17. serial1 = &uartc;
  18. };
  19. chosen {
  20. stdout-path = "serial0:115200n8";
  21. };
  22. memory@0 {
  23. reg = <0x00000000 0x20000000>;
  24. };
  25. host1x@50000000 {
  26. dc@54200000 {
  27. rgb {
  28. status = "okay";
  29. nvidia,panel = <&panel>;
  30. };
  31. };
  32. hdmi@54280000 {
  33. status = "okay";
  34. vdd-supply = <&hdmi_vdd_reg>;
  35. pll-supply = <&hdmi_pll_reg>;
  36. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  37. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  38. GPIO_ACTIVE_HIGH>;
  39. };
  40. };
  41. pinmux@70000014 {
  42. pinctrl-names = "default";
  43. pinctrl-0 = <&state_default>;
  44. state_default: pinmux {
  45. ata {
  46. nvidia,pins = "ata", "atc", "atd", "ate",
  47. "dap2", "gmb", "gmc", "gmd", "spia",
  48. "spib", "spic", "spid", "spie";
  49. nvidia,function = "gmi";
  50. };
  51. atb {
  52. nvidia,pins = "atb", "gma", "gme";
  53. nvidia,function = "sdio4";
  54. };
  55. cdev1 {
  56. nvidia,pins = "cdev1";
  57. nvidia,function = "plla_out";
  58. };
  59. cdev2 {
  60. nvidia,pins = "cdev2";
  61. nvidia,function = "pllp_out4";
  62. };
  63. crtp {
  64. nvidia,pins = "crtp";
  65. nvidia,function = "crt";
  66. };
  67. csus {
  68. nvidia,pins = "csus";
  69. nvidia,function = "pllc_out1";
  70. };
  71. dap1 {
  72. nvidia,pins = "dap1";
  73. nvidia,function = "dap1";
  74. };
  75. dap3 {
  76. nvidia,pins = "dap3";
  77. nvidia,function = "dap3";
  78. };
  79. dap4 {
  80. nvidia,pins = "dap4";
  81. nvidia,function = "dap4";
  82. };
  83. ddc {
  84. nvidia,pins = "ddc";
  85. nvidia,function = "i2c2";
  86. };
  87. dta {
  88. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  89. nvidia,function = "rsvd1";
  90. };
  91. dtf {
  92. nvidia,pins = "dtf";
  93. nvidia,function = "i2c3";
  94. };
  95. gpu {
  96. nvidia,pins = "gpu", "sdb", "sdd";
  97. nvidia,function = "pwm";
  98. };
  99. gpu7 {
  100. nvidia,pins = "gpu7";
  101. nvidia,function = "rtck";
  102. };
  103. gpv {
  104. nvidia,pins = "gpv", "slxa", "slxk";
  105. nvidia,function = "pcie";
  106. };
  107. hdint {
  108. nvidia,pins = "hdint", "pta";
  109. nvidia,function = "hdmi";
  110. };
  111. i2cp {
  112. nvidia,pins = "i2cp";
  113. nvidia,function = "i2cp";
  114. };
  115. irrx {
  116. nvidia,pins = "irrx", "irtx";
  117. nvidia,function = "uarta";
  118. };
  119. kbca {
  120. nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
  121. nvidia,function = "kbc";
  122. };
  123. kbcb {
  124. nvidia,pins = "kbcb", "kbcd";
  125. nvidia,function = "sdio2";
  126. };
  127. lcsn {
  128. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  129. "ld3", "ld4", "ld5", "ld6", "ld7",
  130. "ld8", "ld9", "ld10", "ld11", "ld12",
  131. "ld13", "ld14", "ld15", "ld16", "ld17",
  132. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  133. "lhs", "lm0", "lm1", "lpp", "lpw0",
  134. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  135. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  136. "lvs";
  137. nvidia,function = "displaya";
  138. };
  139. owc {
  140. nvidia,pins = "owc";
  141. nvidia,function = "owr";
  142. };
  143. pmc {
  144. nvidia,pins = "pmc";
  145. nvidia,function = "pwr_on";
  146. };
  147. rm {
  148. nvidia,pins = "rm";
  149. nvidia,function = "i2c1";
  150. };
  151. sdc {
  152. nvidia,pins = "sdc";
  153. nvidia,function = "twc";
  154. };
  155. sdio1 {
  156. nvidia,pins = "sdio1";
  157. nvidia,function = "sdio1";
  158. };
  159. slxc {
  160. nvidia,pins = "slxc", "slxd";
  161. nvidia,function = "spi4";
  162. };
  163. spdi {
  164. nvidia,pins = "spdi", "spdo";
  165. nvidia,function = "rsvd2";
  166. };
  167. spif {
  168. nvidia,pins = "spif", "uac";
  169. nvidia,function = "rsvd4";
  170. };
  171. spig {
  172. nvidia,pins = "spig", "spih";
  173. nvidia,function = "spi2_alt";
  174. };
  175. uaa {
  176. nvidia,pins = "uaa", "uab", "uda";
  177. nvidia,function = "ulpi";
  178. };
  179. uad {
  180. nvidia,pins = "uad";
  181. nvidia,function = "spdif";
  182. };
  183. uca {
  184. nvidia,pins = "uca", "ucb";
  185. nvidia,function = "uartc";
  186. };
  187. conf_ata {
  188. nvidia,pins = "ata", "atb", "atc", "atd", "ate",
  189. "cdev1", "cdev2", "dap1", "dap2", "dtf",
  190. "gma", "gmb", "gmc", "gmd", "gme",
  191. "gpu", "gpu7", "gpv", "i2cp", "pta",
  192. "rm", "sdio1", "slxk", "spdo", "uac",
  193. "uda";
  194. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  195. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  196. };
  197. conf_ck32 {
  198. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  199. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  200. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  201. };
  202. conf_crtp {
  203. nvidia,pins = "crtp", "dap3", "dap4", "dtb",
  204. "dtc", "dte", "slxa", "slxc", "slxd",
  205. "spdi";
  206. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  207. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  208. };
  209. conf_csus {
  210. nvidia,pins = "csus", "spia", "spib", "spid",
  211. "spif";
  212. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  213. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  214. };
  215. conf_ddc {
  216. nvidia,pins = "ddc", "irrx", "irtx", "kbca",
  217. "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
  218. "spic", "spig", "uaa", "uab";
  219. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  220. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  221. };
  222. conf_dta {
  223. nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
  224. "spie", "spih", "uad", "uca", "ucb";
  225. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  226. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  227. };
  228. conf_hdint {
  229. nvidia,pins = "hdint", "ld0", "ld1", "ld2",
  230. "ld3", "ld4", "ld5", "ld6", "ld7",
  231. "ld8", "ld9", "ld10", "ld11", "ld12",
  232. "ld13", "ld14", "ld15", "ld16", "ld17",
  233. "ldc", "ldi", "lhs", "lsc0", "lspi",
  234. "lvs", "pmc";
  235. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  236. };
  237. conf_lc {
  238. nvidia,pins = "lc", "ls";
  239. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  240. };
  241. conf_lcsn {
  242. nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
  243. "lm0", "lm1", "lpp", "lpw0", "lpw1",
  244. "lpw2", "lsc1", "lsck", "lsda", "lsdi",
  245. "lvp0", "lvp1", "sdb";
  246. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  247. };
  248. conf_ld17_0 {
  249. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  250. "ld23_22";
  251. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  252. };
  253. };
  254. };
  255. spdif@70002400 {
  256. status = "okay";
  257. nvidia,fixed-parent-rate;
  258. };
  259. i2s@70002800 {
  260. status = "okay";
  261. nvidia,fixed-parent-rate;
  262. };
  263. serial@70006000 {
  264. status = "okay";
  265. };
  266. serial@70006200 {
  267. status = "okay";
  268. };
  269. pwm: pwm@7000a000 {
  270. status = "okay";
  271. };
  272. lvds_ddc: i2c@7000c000 {
  273. status = "okay";
  274. clock-frequency = <400000>;
  275. alc5632: alc5632@1e {
  276. compatible = "realtek,alc5632";
  277. reg = <0x1e>;
  278. gpio-controller;
  279. #gpio-cells = <2>;
  280. };
  281. };
  282. hdmi_ddc: i2c@7000c400 {
  283. status = "okay";
  284. clock-frequency = <100000>;
  285. };
  286. nvec@7000c500 {
  287. compatible = "nvidia,nvec";
  288. reg = <0x7000c500 0x100>;
  289. interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
  290. #address-cells = <1>;
  291. #size-cells = <0>;
  292. clock-frequency = <80000>;
  293. request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
  294. slave-addr = <138>;
  295. clocks = <&tegra_car TEGRA20_CLK_I2C3>,
  296. <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
  297. clock-names = "div-clk", "fast-clk";
  298. resets = <&tegra_car 67>;
  299. reset-names = "i2c";
  300. };
  301. memory-controller@7000f400 {
  302. nvidia,use-ram-code;
  303. emc-tables@0 {
  304. nvidia,ram-code = <0x0>;
  305. #address-cells = <1>;
  306. #size-cells = <0>;
  307. reg = <0>;
  308. emc-table@166500 {
  309. reg = <166500>;
  310. compatible = "nvidia,tegra20-emc-table";
  311. clock-frequency = <166500>;
  312. nvidia,emc-registers = <0x0000000a 0x00000016
  313. 0x00000008 0x00000003 0x00000004 0x00000004
  314. 0x00000002 0x0000000c 0x00000003 0x00000003
  315. 0x00000002 0x00000001 0x00000004 0x00000005
  316. 0x00000004 0x00000009 0x0000000d 0x000004df
  317. 0x00000000 0x00000003 0x00000003 0x00000003
  318. 0x00000003 0x00000001 0x0000000a 0x000000c8
  319. 0x00000003 0x00000006 0x00000004 0x00000008
  320. 0x00000002 0x00000000 0x00000000 0x00000002
  321. 0x00000000 0x00000000 0x00000083 0xe03b0323
  322. 0x007fe010 0x00001414 0x00000000 0x00000000
  323. 0x00000000 0x00000000 0x00000000 0x00000000>;
  324. };
  325. emc-table@333000 {
  326. reg = <333000>;
  327. compatible = "nvidia,tegra20-emc-table";
  328. clock-frequency = <333000>;
  329. nvidia,emc-registers = <0x00000018 0x00000033
  330. 0x00000012 0x00000004 0x00000004 0x00000005
  331. 0x00000003 0x0000000c 0x00000006 0x00000006
  332. 0x00000003 0x00000001 0x00000004 0x00000005
  333. 0x00000004 0x00000009 0x0000000d 0x00000bff
  334. 0x00000000 0x00000003 0x00000003 0x00000006
  335. 0x00000006 0x00000001 0x00000011 0x000000c8
  336. 0x00000003 0x0000000e 0x00000007 0x00000008
  337. 0x00000002 0x00000000 0x00000000 0x00000002
  338. 0x00000000 0x00000000 0x00000083 0xf0440303
  339. 0x007fe010 0x00001414 0x00000000 0x00000000
  340. 0x00000000 0x00000000 0x00000000 0x00000000>;
  341. };
  342. };
  343. };
  344. i2c@7000d000 {
  345. status = "okay";
  346. clock-frequency = <400000>;
  347. pmic: tps6586x@34 {
  348. compatible = "ti,tps6586x";
  349. reg = <0x34>;
  350. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  351. #gpio-cells = <2>;
  352. gpio-controller;
  353. sys-supply = <&p5valw_reg>;
  354. vin-sm0-supply = <&sys_reg>;
  355. vin-sm1-supply = <&sys_reg>;
  356. vin-sm2-supply = <&sys_reg>;
  357. vinldo01-supply = <&sm2_reg>;
  358. vinldo23-supply = <&sm2_reg>;
  359. vinldo4-supply = <&sm2_reg>;
  360. vinldo678-supply = <&sm2_reg>;
  361. vinldo9-supply = <&sm2_reg>;
  362. regulators {
  363. sys_reg: sys {
  364. regulator-name = "vdd_sys";
  365. regulator-always-on;
  366. };
  367. core_vdd_reg: sm0 {
  368. regulator-name = "+1.2vs_sm0,vdd_core";
  369. regulator-min-microvolt = <950000>;
  370. regulator-max-microvolt = <1300000>;
  371. regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>;
  372. regulator-coupled-max-spread = <170000 550000>;
  373. regulator-always-on;
  374. nvidia,tegra-core-regulator;
  375. };
  376. cpu_vdd_reg: sm1 {
  377. regulator-name = "+1.0vs_sm1,vdd_cpu";
  378. regulator-min-microvolt = <750000>;
  379. regulator-max-microvolt = <1100000>;
  380. regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>;
  381. regulator-coupled-max-spread = <550000 550000>;
  382. regulator-always-on;
  383. nvidia,tegra-cpu-regulator;
  384. };
  385. sm2_reg: sm2 {
  386. regulator-name = "+3.7vs_sm2,vin_ldo*";
  387. regulator-min-microvolt = <3700000>;
  388. regulator-max-microvolt = <3700000>;
  389. regulator-always-on;
  390. };
  391. /* LDO0 is not connected to anything */
  392. ldo1 {
  393. regulator-name = "+1.1vs_ldo1,avdd_pll*";
  394. regulator-min-microvolt = <1100000>;
  395. regulator-max-microvolt = <1100000>;
  396. regulator-always-on;
  397. };
  398. rtc_vdd_reg: ldo2 {
  399. regulator-name = "+1.2vs_ldo2,vdd_rtc";
  400. regulator-min-microvolt = <950000>;
  401. regulator-max-microvolt = <1300000>;
  402. regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>;
  403. regulator-coupled-max-spread = <170000 550000>;
  404. regulator-always-on;
  405. nvidia,tegra-rtc-regulator;
  406. };
  407. ldo3 {
  408. regulator-name = "+3.3vs_ldo3,avdd_usb*";
  409. regulator-min-microvolt = <3300000>;
  410. regulator-max-microvolt = <3300000>;
  411. regulator-always-on;
  412. };
  413. ldo4 {
  414. regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
  415. regulator-min-microvolt = <1800000>;
  416. regulator-max-microvolt = <1800000>;
  417. regulator-always-on;
  418. };
  419. ldo5 {
  420. regulator-name = "+2.85vs_ldo5,vcore_mmc";
  421. regulator-min-microvolt = <2850000>;
  422. regulator-max-microvolt = <2850000>;
  423. regulator-always-on;
  424. };
  425. ldo6 {
  426. /*
  427. * Research indicates this should be
  428. * 1.8v; other boards that use this
  429. * rail for the same purpose need it
  430. * set to 1.8v. The schematic signal
  431. * name is incorrect; perhaps copied
  432. * from an incorrect NVIDIA reference.
  433. */
  434. regulator-name = "+2.85vs_ldo6,avdd_vdac";
  435. regulator-min-microvolt = <1800000>;
  436. regulator-max-microvolt = <1800000>;
  437. };
  438. hdmi_vdd_reg: ldo7 {
  439. regulator-name = "+3.3vs_ldo7,avdd_hdmi";
  440. regulator-min-microvolt = <3300000>;
  441. regulator-max-microvolt = <3300000>;
  442. };
  443. hdmi_pll_reg: ldo8 {
  444. regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
  445. regulator-min-microvolt = <1800000>;
  446. regulator-max-microvolt = <1800000>;
  447. };
  448. ldo9 {
  449. regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
  450. regulator-min-microvolt = <2850000>;
  451. regulator-max-microvolt = <2850000>;
  452. regulator-always-on;
  453. };
  454. ldo_rtc {
  455. regulator-name = "+3.3vs_rtc";
  456. regulator-min-microvolt = <3300000>;
  457. regulator-max-microvolt = <3300000>;
  458. regulator-always-on;
  459. };
  460. };
  461. };
  462. adt7461: temperature-sensor@4c {
  463. compatible = "adi,adt7461";
  464. reg = <0x4c>;
  465. interrupt-parent = <&gpio>;
  466. interrupts = <TEGRA_GPIO(N, 6) IRQ_TYPE_EDGE_FALLING>;
  467. #thermal-sensor-cells = <1>;
  468. };
  469. };
  470. pmc@7000e400 {
  471. nvidia,invert-interrupt;
  472. nvidia,suspend-mode = <1>;
  473. nvidia,cpu-pwr-good-time = <2000>;
  474. nvidia,cpu-pwr-off-time = <0>;
  475. nvidia,core-pwr-good-time = <3845 3845>;
  476. nvidia,core-pwr-off-time = <0>;
  477. nvidia,sys-clock-req-active-high;
  478. core-supply = <&core_vdd_reg>;
  479. };
  480. usb@c5000000 {
  481. compatible = "nvidia,tegra20-udc";
  482. status = "okay";
  483. dr_mode = "peripheral";
  484. };
  485. usb-phy@c5000000 {
  486. status = "okay";
  487. };
  488. usb@c5004000 {
  489. status = "okay";
  490. };
  491. usb-phy@c5004000 {
  492. status = "okay";
  493. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
  494. GPIO_ACTIVE_LOW>;
  495. };
  496. usb@c5008000 {
  497. status = "okay";
  498. };
  499. usb-phy@c5008000 {
  500. status = "okay";
  501. };
  502. sdmmc1: mmc@c8000000 {
  503. status = "okay";
  504. cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
  505. wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  506. power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
  507. bus-width = <4>;
  508. };
  509. sdmmc4: mmc@c8000600 {
  510. status = "okay";
  511. bus-width = <8>;
  512. non-removable;
  513. };
  514. backlight: backlight {
  515. compatible = "pwm-backlight";
  516. enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
  517. pwms = <&pwm 0 5000000>;
  518. brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
  519. default-brightness-level = <10>;
  520. /* close enough */
  521. power-supply = <&vdd_pnl_reg>;
  522. };
  523. clk32k_in: clock-32k {
  524. compatible = "fixed-clock";
  525. clock-frequency = <32768>;
  526. #clock-cells = <0>;
  527. };
  528. gpio-keys {
  529. compatible = "gpio-keys";
  530. key-wakeup {
  531. label = "Wakeup";
  532. gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
  533. linux,code = <KEY_WAKEUP>;
  534. wakeup-source;
  535. };
  536. };
  537. gpio-leds {
  538. compatible = "gpio-leds";
  539. led-0 {
  540. label = "wifi-led";
  541. gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
  542. linux,default-trigger = "rfkill0";
  543. };
  544. };
  545. panel: panel {
  546. compatible = "samsung,ltn101nt05";
  547. ddc-i2c-bus = <&lvds_ddc>;
  548. power-supply = <&vdd_pnl_reg>;
  549. enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>;
  550. backlight = <&backlight>;
  551. };
  552. p5valw_reg: regulator-5v0alw {
  553. compatible = "regulator-fixed";
  554. regulator-name = "+5valw";
  555. regulator-min-microvolt = <5000000>;
  556. regulator-max-microvolt = <5000000>;
  557. regulator-always-on;
  558. };
  559. vdd_pnl_reg: regulator-3v0 {
  560. compatible = "regulator-fixed";
  561. regulator-name = "+3VS,vdd_pnl";
  562. regulator-min-microvolt = <3300000>;
  563. regulator-max-microvolt = <3300000>;
  564. regulator-boot-on;
  565. gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
  566. enable-active-high;
  567. };
  568. sound {
  569. compatible = "nvidia,tegra-audio-alc5632-paz00",
  570. "nvidia,tegra-audio-alc5632";
  571. nvidia,model = "Compal PAZ00";
  572. nvidia,audio-routing =
  573. "Int Spk", "SPKOUT",
  574. "Int Spk", "SPKOUTN",
  575. "Headset Mic", "MICBIAS1",
  576. "MIC1", "Headset Mic",
  577. "Headset Stereophone", "HPR",
  578. "Headset Stereophone", "HPL",
  579. "DMICDAT", "Digital Mic";
  580. nvidia,audio-codec = <&alc5632>;
  581. nvidia,i2s-controller = <&tegra_i2s1>;
  582. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
  583. GPIO_ACTIVE_HIGH>;
  584. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  585. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  586. <&tegra_car TEGRA20_CLK_CDEV1>;
  587. clock-names = "pll_a", "pll_a_out0", "mclk";
  588. };
  589. cpus {
  590. cpu0: cpu@0 {
  591. cpu-supply = <&cpu_vdd_reg>;
  592. operating-points-v2 = <&cpu0_opp_table>;
  593. #cooling-cells = <2>;
  594. };
  595. cpu1: cpu@1 {
  596. cpu-supply = <&cpu_vdd_reg>;
  597. operating-points-v2 = <&cpu0_opp_table>;
  598. #cooling-cells = <2>;
  599. };
  600. };
  601. thermal-zones {
  602. cpu-thermal {
  603. polling-delay-passive = <500>; /* milliseconds */
  604. polling-delay = <1500>; /* milliseconds */
  605. thermal-sensors = <&adt7461 1>;
  606. trips {
  607. trip0: cpu-alert0 {
  608. /* start throttling at 80C */
  609. temperature = <80000>;
  610. hysteresis = <200>;
  611. type = "passive";
  612. };
  613. trip1: cpu-crit {
  614. /* shut down at 85C */
  615. temperature = <85000>;
  616. hysteresis = <2000>;
  617. type = "critical";
  618. };
  619. };
  620. cooling-maps {
  621. map0 {
  622. trip = <&trip0>;
  623. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  624. <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  625. };
  626. };
  627. };
  628. };
  629. };
  630. &emc_icc_dvfs_opp_table {
  631. /delete-node/ opp-760000000;
  632. };