tegra20-harmony.dts 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include <dt-bindings/input/input.h>
  4. #include "tegra20.dtsi"
  5. / {
  6. model = "NVIDIA Tegra20 Harmony evaluation board";
  7. compatible = "nvidia,harmony", "nvidia,tegra20";
  8. aliases {
  9. rtc0 = "/i2c@7000d000/tps6586x@34";
  10. rtc1 = "/rtc@7000e000";
  11. serial0 = &uartd;
  12. };
  13. chosen {
  14. stdout-path = "serial0:115200n8";
  15. };
  16. memory@0 {
  17. reg = <0x00000000 0x40000000>;
  18. };
  19. host1x@50000000 {
  20. dc@54200000 {
  21. rgb {
  22. status = "okay";
  23. nvidia,panel = <&panel>;
  24. };
  25. };
  26. hdmi@54280000 {
  27. status = "okay";
  28. hdmi-supply = <&vdd_5v0_hdmi>;
  29. vdd-supply = <&hdmi_vdd_reg>;
  30. pll-supply = <&hdmi_pll_reg>;
  31. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  32. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  33. GPIO_ACTIVE_HIGH>;
  34. };
  35. };
  36. pinmux@70000014 {
  37. pinctrl-names = "default";
  38. pinctrl-0 = <&state_default>;
  39. state_default: pinmux {
  40. ata {
  41. nvidia,pins = "ata";
  42. nvidia,function = "ide";
  43. };
  44. atb {
  45. nvidia,pins = "atb", "gma", "gme";
  46. nvidia,function = "sdio4";
  47. };
  48. atc {
  49. nvidia,pins = "atc";
  50. nvidia,function = "nand";
  51. };
  52. atd {
  53. nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
  54. "spia", "spib", "spic";
  55. nvidia,function = "gmi";
  56. };
  57. cdev1 {
  58. nvidia,pins = "cdev1";
  59. nvidia,function = "plla_out";
  60. };
  61. cdev2 {
  62. nvidia,pins = "cdev2";
  63. nvidia,function = "pllp_out4";
  64. };
  65. crtp {
  66. nvidia,pins = "crtp";
  67. nvidia,function = "crt";
  68. };
  69. csus {
  70. nvidia,pins = "csus";
  71. nvidia,function = "vi_sensor_clk";
  72. };
  73. dap1 {
  74. nvidia,pins = "dap1";
  75. nvidia,function = "dap1";
  76. };
  77. dap2 {
  78. nvidia,pins = "dap2";
  79. nvidia,function = "dap2";
  80. };
  81. dap3 {
  82. nvidia,pins = "dap3";
  83. nvidia,function = "dap3";
  84. };
  85. dap4 {
  86. nvidia,pins = "dap4";
  87. nvidia,function = "dap4";
  88. };
  89. ddc {
  90. nvidia,pins = "ddc";
  91. nvidia,function = "i2c2";
  92. };
  93. dta {
  94. nvidia,pins = "dta", "dtd";
  95. nvidia,function = "sdio2";
  96. };
  97. dtb {
  98. nvidia,pins = "dtb", "dtc", "dte";
  99. nvidia,function = "rsvd1";
  100. };
  101. dtf {
  102. nvidia,pins = "dtf";
  103. nvidia,function = "i2c3";
  104. };
  105. gmc {
  106. nvidia,pins = "gmc";
  107. nvidia,function = "uartd";
  108. };
  109. gpu7 {
  110. nvidia,pins = "gpu7";
  111. nvidia,function = "rtck";
  112. };
  113. gpv {
  114. nvidia,pins = "gpv", "slxa", "slxk";
  115. nvidia,function = "pcie";
  116. };
  117. hdint {
  118. nvidia,pins = "hdint", "pta";
  119. nvidia,function = "hdmi";
  120. };
  121. i2cp {
  122. nvidia,pins = "i2cp";
  123. nvidia,function = "i2cp";
  124. };
  125. irrx {
  126. nvidia,pins = "irrx", "irtx";
  127. nvidia,function = "uarta";
  128. };
  129. kbca {
  130. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  131. "kbce", "kbcf";
  132. nvidia,function = "kbc";
  133. };
  134. lcsn {
  135. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  136. "ld3", "ld4", "ld5", "ld6", "ld7",
  137. "ld8", "ld9", "ld10", "ld11", "ld12",
  138. "ld13", "ld14", "ld15", "ld16", "ld17",
  139. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  140. "lhs", "lm0", "lm1", "lpp", "lpw0",
  141. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  142. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  143. "lvs";
  144. nvidia,function = "displaya";
  145. };
  146. owc {
  147. nvidia,pins = "owc", "spdi", "spdo", "uac";
  148. nvidia,function = "rsvd2";
  149. };
  150. pmc {
  151. nvidia,pins = "pmc";
  152. nvidia,function = "pwr_on";
  153. };
  154. rm {
  155. nvidia,pins = "rm";
  156. nvidia,function = "i2c1";
  157. };
  158. sdb {
  159. nvidia,pins = "sdb", "sdc", "sdd";
  160. nvidia,function = "pwm";
  161. };
  162. sdio1 {
  163. nvidia,pins = "sdio1";
  164. nvidia,function = "sdio1";
  165. };
  166. slxc {
  167. nvidia,pins = "slxc", "slxd";
  168. nvidia,function = "spdif";
  169. };
  170. spid {
  171. nvidia,pins = "spid", "spie", "spif";
  172. nvidia,function = "spi1";
  173. };
  174. spig {
  175. nvidia,pins = "spig", "spih";
  176. nvidia,function = "spi2_alt";
  177. };
  178. uaa {
  179. nvidia,pins = "uaa", "uab", "uda";
  180. nvidia,function = "ulpi";
  181. };
  182. uad {
  183. nvidia,pins = "uad";
  184. nvidia,function = "irda";
  185. };
  186. uca {
  187. nvidia,pins = "uca", "ucb";
  188. nvidia,function = "uartc";
  189. };
  190. conf_ata {
  191. nvidia,pins = "ata", "atb", "atc", "atd", "ate",
  192. "cdev1", "cdev2", "dap1", "dtb", "gma",
  193. "gmb", "gmc", "gmd", "gme", "gpu7",
  194. "gpv", "i2cp", "pta", "rm", "slxa",
  195. "slxk", "spia", "spib", "uac";
  196. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  197. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  198. };
  199. conf_ck32 {
  200. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  201. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  202. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  203. };
  204. conf_csus {
  205. nvidia,pins = "csus", "spid", "spif";
  206. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  207. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  208. };
  209. conf_crtp {
  210. nvidia,pins = "crtp", "dap2", "dap3", "dap4",
  211. "dtc", "dte", "dtf", "gpu", "sdio1",
  212. "slxc", "slxd", "spdi", "spdo", "spig",
  213. "uda";
  214. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  215. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  216. };
  217. conf_ddc {
  218. nvidia,pins = "ddc", "dta", "dtd", "kbca",
  219. "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
  220. "sdc";
  221. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  222. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  223. };
  224. conf_hdint {
  225. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  226. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  227. "lvp0", "owc", "sdb";
  228. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  229. };
  230. conf_irrx {
  231. nvidia,pins = "irrx", "irtx", "sdd", "spic",
  232. "spie", "spih", "uaa", "uab", "uad",
  233. "uca", "ucb";
  234. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  235. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  236. };
  237. conf_lc {
  238. nvidia,pins = "lc", "ls";
  239. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  240. };
  241. conf_ld0 {
  242. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  243. "ld5", "ld6", "ld7", "ld8", "ld9",
  244. "ld10", "ld11", "ld12", "ld13", "ld14",
  245. "ld15", "ld16", "ld17", "ldi", "lhp0",
  246. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  247. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  248. "lvs", "pmc";
  249. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  250. };
  251. conf_ld17_0 {
  252. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  253. "ld23_22";
  254. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  255. };
  256. };
  257. };
  258. i2s@70002800 {
  259. status = "okay";
  260. };
  261. serial@70006300 {
  262. status = "okay";
  263. };
  264. pwm: pwm@7000a000 {
  265. status = "okay";
  266. };
  267. i2c@7000c000 {
  268. status = "okay";
  269. clock-frequency = <400000>;
  270. wm8903: wm8903@1a {
  271. compatible = "wlf,wm8903";
  272. reg = <0x1a>;
  273. interrupt-parent = <&gpio>;
  274. interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
  275. gpio-controller;
  276. #gpio-cells = <2>;
  277. micdet-cfg = <0>;
  278. micdet-delay = <100>;
  279. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  280. };
  281. };
  282. hdmi_ddc: i2c@7000c400 {
  283. status = "okay";
  284. clock-frequency = <100000>;
  285. };
  286. i2c@7000c500 {
  287. status = "okay";
  288. clock-frequency = <400000>;
  289. };
  290. i2c@7000d000 {
  291. status = "okay";
  292. clock-frequency = <400000>;
  293. pmic: tps6586x@34 {
  294. compatible = "ti,tps6586x";
  295. reg = <0x34>;
  296. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  297. ti,system-power-controller;
  298. #gpio-cells = <2>;
  299. gpio-controller;
  300. sys-supply = <&vdd_5v0_reg>;
  301. vin-sm0-supply = <&sys_reg>;
  302. vin-sm1-supply = <&sys_reg>;
  303. vin-sm2-supply = <&sys_reg>;
  304. vinldo01-supply = <&sm2_reg>;
  305. vinldo23-supply = <&sm2_reg>;
  306. vinldo4-supply = <&sm2_reg>;
  307. vinldo678-supply = <&sm2_reg>;
  308. vinldo9-supply = <&sm2_reg>;
  309. regulators {
  310. sys_reg: sys {
  311. regulator-name = "vdd_sys";
  312. regulator-always-on;
  313. };
  314. vdd_core: sm0 {
  315. regulator-name = "vdd_sm0,vdd_core";
  316. regulator-min-microvolt = <1200000>;
  317. regulator-max-microvolt = <1200000>;
  318. regulator-always-on;
  319. };
  320. sm1 {
  321. regulator-name = "vdd_sm1,vdd_cpu";
  322. regulator-min-microvolt = <1000000>;
  323. regulator-max-microvolt = <1000000>;
  324. regulator-always-on;
  325. };
  326. sm2_reg: sm2 {
  327. regulator-name = "vdd_sm2,vin_ldo*";
  328. regulator-min-microvolt = <3700000>;
  329. regulator-max-microvolt = <3700000>;
  330. regulator-always-on;
  331. };
  332. pci_clk_reg: ldo0 {
  333. regulator-name = "vdd_ldo0,vddio_pex_clk";
  334. regulator-min-microvolt = <3300000>;
  335. regulator-max-microvolt = <3300000>;
  336. };
  337. ldo1 {
  338. regulator-name = "vdd_ldo1,avdd_pll*";
  339. regulator-min-microvolt = <1100000>;
  340. regulator-max-microvolt = <1100000>;
  341. regulator-always-on;
  342. };
  343. ldo2 {
  344. regulator-name = "vdd_ldo2,vdd_rtc";
  345. regulator-min-microvolt = <1200000>;
  346. regulator-max-microvolt = <1200000>;
  347. };
  348. ldo3 {
  349. regulator-name = "vdd_ldo3,avdd_usb*";
  350. regulator-min-microvolt = <3300000>;
  351. regulator-max-microvolt = <3300000>;
  352. regulator-always-on;
  353. };
  354. ldo4 {
  355. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  356. regulator-min-microvolt = <1800000>;
  357. regulator-max-microvolt = <1800000>;
  358. regulator-always-on;
  359. };
  360. ldo5 {
  361. regulator-name = "vdd_ldo5,vcore_mmc";
  362. regulator-min-microvolt = <2850000>;
  363. regulator-max-microvolt = <2850000>;
  364. regulator-always-on;
  365. };
  366. ldo6 {
  367. regulator-name = "vdd_ldo6,avdd_vdac";
  368. regulator-min-microvolt = <1800000>;
  369. regulator-max-microvolt = <1800000>;
  370. };
  371. hdmi_vdd_reg: ldo7 {
  372. regulator-name = "vdd_ldo7,avdd_hdmi";
  373. regulator-min-microvolt = <3300000>;
  374. regulator-max-microvolt = <3300000>;
  375. };
  376. hdmi_pll_reg: ldo8 {
  377. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  378. regulator-min-microvolt = <1800000>;
  379. regulator-max-microvolt = <1800000>;
  380. };
  381. ldo9 {
  382. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  383. regulator-min-microvolt = <2850000>;
  384. regulator-max-microvolt = <2850000>;
  385. regulator-always-on;
  386. };
  387. ldo_rtc {
  388. regulator-name = "vdd_rtc_out,vdd_cell";
  389. regulator-min-microvolt = <3300000>;
  390. regulator-max-microvolt = <3300000>;
  391. regulator-always-on;
  392. };
  393. };
  394. };
  395. temperature-sensor@4c {
  396. compatible = "adi,adt7461";
  397. reg = <0x4c>;
  398. };
  399. };
  400. kbc@7000e200 {
  401. status = "okay";
  402. nvidia,debounce-delay-ms = <2>;
  403. nvidia,repeat-delay-ms = <160>;
  404. nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  405. nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
  406. linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
  407. MATRIX_KEY(0x00, 0x03, KEY_S)
  408. MATRIX_KEY(0x00, 0x04, KEY_A)
  409. MATRIX_KEY(0x00, 0x05, KEY_Z)
  410. MATRIX_KEY(0x00, 0x07, KEY_FN)
  411. MATRIX_KEY(0x01, 0x07, KEY_MENU)
  412. MATRIX_KEY(0x02, 0x06, KEY_LEFTALT)
  413. MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT)
  414. MATRIX_KEY(0x03, 0x00, KEY_5)
  415. MATRIX_KEY(0x03, 0x01, KEY_4)
  416. MATRIX_KEY(0x03, 0x02, KEY_R)
  417. MATRIX_KEY(0x03, 0x03, KEY_E)
  418. MATRIX_KEY(0x03, 0x04, KEY_F)
  419. MATRIX_KEY(0x03, 0x05, KEY_D)
  420. MATRIX_KEY(0x03, 0x06, KEY_X)
  421. MATRIX_KEY(0x04, 0x00, KEY_7)
  422. MATRIX_KEY(0x04, 0x01, KEY_6)
  423. MATRIX_KEY(0x04, 0x02, KEY_T)
  424. MATRIX_KEY(0x04, 0x03, KEY_H)
  425. MATRIX_KEY(0x04, 0x04, KEY_G)
  426. MATRIX_KEY(0x04, 0x05, KEY_V)
  427. MATRIX_KEY(0x04, 0x06, KEY_C)
  428. MATRIX_KEY(0x04, 0x07, KEY_SPACE)
  429. MATRIX_KEY(0x05, 0x00, KEY_9)
  430. MATRIX_KEY(0x05, 0x01, KEY_8)
  431. MATRIX_KEY(0x05, 0x02, KEY_U)
  432. MATRIX_KEY(0x05, 0x03, KEY_Y)
  433. MATRIX_KEY(0x05, 0x04, KEY_J)
  434. MATRIX_KEY(0x05, 0x05, KEY_N)
  435. MATRIX_KEY(0x05, 0x06, KEY_B)
  436. MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
  437. MATRIX_KEY(0x06, 0x00, KEY_MINUS)
  438. MATRIX_KEY(0x06, 0x01, KEY_0)
  439. MATRIX_KEY(0x06, 0x02, KEY_O)
  440. MATRIX_KEY(0x06, 0x03, KEY_I)
  441. MATRIX_KEY(0x06, 0x04, KEY_L)
  442. MATRIX_KEY(0x06, 0x05, KEY_K)
  443. MATRIX_KEY(0x06, 0x06, KEY_COMMA)
  444. MATRIX_KEY(0x06, 0x07, KEY_M)
  445. MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
  446. MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
  447. MATRIX_KEY(0x07, 0x03, KEY_ENTER)
  448. MATRIX_KEY(0x07, 0x07, KEY_MENU)
  449. MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT)
  450. MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT)
  451. MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL)
  452. MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL)
  453. MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
  454. MATRIX_KEY(0x0B, 0x01, KEY_P)
  455. MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
  456. MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
  457. MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
  458. MATRIX_KEY(0x0B, 0x05, KEY_DOT)
  459. MATRIX_KEY(0x0C, 0x00, KEY_F10)
  460. MATRIX_KEY(0x0C, 0x01, KEY_F9)
  461. MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
  462. MATRIX_KEY(0x0C, 0x03, KEY_3)
  463. MATRIX_KEY(0x0C, 0x04, KEY_2)
  464. MATRIX_KEY(0x0C, 0x05, KEY_UP)
  465. MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
  466. MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
  467. MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
  468. MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
  469. MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
  470. MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
  471. MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
  472. MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
  473. MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
  474. MATRIX_KEY(0x0E, 0x00, KEY_F11)
  475. MATRIX_KEY(0x0E, 0x01, KEY_F12)
  476. MATRIX_KEY(0x0E, 0x02, KEY_F8)
  477. MATRIX_KEY(0x0E, 0x03, KEY_Q)
  478. MATRIX_KEY(0x0E, 0x04, KEY_F4)
  479. MATRIX_KEY(0x0E, 0x05, KEY_F3)
  480. MATRIX_KEY(0x0E, 0x06, KEY_1)
  481. MATRIX_KEY(0x0E, 0x07, KEY_F7)
  482. MATRIX_KEY(0x0F, 0x00, KEY_ESC)
  483. MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
  484. MATRIX_KEY(0x0F, 0x02, KEY_F5)
  485. MATRIX_KEY(0x0F, 0x03, KEY_TAB)
  486. MATRIX_KEY(0x0F, 0x04, KEY_F1)
  487. MATRIX_KEY(0x0F, 0x05, KEY_F2)
  488. MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
  489. MATRIX_KEY(0x0F, 0x07, KEY_F6)
  490. MATRIX_KEY(0x14, 0x00, KEY_KP7)
  491. MATRIX_KEY(0x15, 0x00, KEY_KP9)
  492. MATRIX_KEY(0x15, 0x01, KEY_KP8)
  493. MATRIX_KEY(0x15, 0x02, KEY_KP4)
  494. MATRIX_KEY(0x15, 0x04, KEY_KP1)
  495. MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
  496. MATRIX_KEY(0x16, 0x02, KEY_KP6)
  497. MATRIX_KEY(0x16, 0x03, KEY_KP5)
  498. MATRIX_KEY(0x16, 0x04, KEY_KP3)
  499. MATRIX_KEY(0x16, 0x05, KEY_KP2)
  500. MATRIX_KEY(0x16, 0x07, KEY_KP0)
  501. MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
  502. MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
  503. MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
  504. MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
  505. MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
  506. MATRIX_KEY(0x1D, 0x03, KEY_HOME)
  507. MATRIX_KEY(0x1D, 0x04, KEY_END)
  508. MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP)
  509. MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
  510. MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN)
  511. MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
  512. MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
  513. MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
  514. MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>;
  515. };
  516. pmc@7000e400 {
  517. nvidia,invert-interrupt;
  518. nvidia,suspend-mode = <1>;
  519. nvidia,cpu-pwr-good-time = <5000>;
  520. nvidia,cpu-pwr-off-time = <5000>;
  521. nvidia,core-pwr-good-time = <3845 3845>;
  522. nvidia,core-pwr-off-time = <3875>;
  523. nvidia,sys-clock-req-active-high;
  524. core-supply = <&vdd_core>;
  525. };
  526. pcie@80003000 {
  527. status = "okay";
  528. avdd-pex-supply = <&pci_vdd_reg>;
  529. vdd-pex-supply = <&pci_vdd_reg>;
  530. avdd-pex-pll-supply = <&pci_vdd_reg>;
  531. avdd-plle-supply = <&pci_vdd_reg>;
  532. vddio-pex-clk-supply = <&pci_clk_reg>;
  533. pci@1,0 {
  534. status = "okay";
  535. };
  536. pci@2,0 {
  537. status = "okay";
  538. };
  539. };
  540. usb@c5000000 {
  541. status = "okay";
  542. };
  543. usb-phy@c5000000 {
  544. status = "okay";
  545. };
  546. usb@c5004000 {
  547. status = "okay";
  548. };
  549. usb-phy@c5004000 {
  550. status = "okay";
  551. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  552. GPIO_ACTIVE_LOW>;
  553. };
  554. usb@c5008000 {
  555. status = "okay";
  556. };
  557. usb-phy@c5008000 {
  558. status = "okay";
  559. };
  560. mmc@c8000200 {
  561. status = "okay";
  562. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  563. wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  564. power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
  565. bus-width = <4>;
  566. };
  567. mmc@c8000600 {
  568. status = "okay";
  569. cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
  570. wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
  571. power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
  572. bus-width = <8>;
  573. };
  574. backlight: backlight {
  575. compatible = "pwm-backlight";
  576. enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
  577. power-supply = <&vdd_bl_reg>;
  578. pwms = <&pwm 0 5000000>;
  579. brightness-levels = <0 4 8 16 32 64 128 255>;
  580. default-brightness-level = <6>;
  581. };
  582. clk32k_in: clock-32k {
  583. compatible = "fixed-clock";
  584. clock-frequency = <32768>;
  585. #clock-cells = <0>;
  586. };
  587. gpio-keys {
  588. compatible = "gpio-keys";
  589. key-power {
  590. label = "Power";
  591. gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  592. linux,code = <KEY_POWER>;
  593. wakeup-source;
  594. };
  595. };
  596. panel: panel {
  597. compatible = "auo,b101aw03";
  598. power-supply = <&vdd_pnl_reg>;
  599. enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
  600. backlight = <&backlight>;
  601. };
  602. vdd_5v0_reg: regulator-5v0 {
  603. compatible = "regulator-fixed";
  604. regulator-name = "vdd_5v0";
  605. regulator-min-microvolt = <5000000>;
  606. regulator-max-microvolt = <5000000>;
  607. regulator-always-on;
  608. };
  609. regulator-1v5 {
  610. compatible = "regulator-fixed";
  611. regulator-name = "vdd_1v5";
  612. regulator-min-microvolt = <1500000>;
  613. regulator-max-microvolt = <1500000>;
  614. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  615. };
  616. regulator-1v2 {
  617. compatible = "regulator-fixed";
  618. regulator-name = "vdd_1v2";
  619. regulator-min-microvolt = <1200000>;
  620. regulator-max-microvolt = <1200000>;
  621. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  622. enable-active-high;
  623. };
  624. pci_vdd_reg: regulator-1v05 {
  625. compatible = "regulator-fixed";
  626. regulator-name = "vdd_1v05";
  627. regulator-min-microvolt = <1050000>;
  628. regulator-max-microvolt = <1050000>;
  629. gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
  630. enable-active-high;
  631. };
  632. vdd_pnl_reg: regulator-pn1 {
  633. compatible = "regulator-fixed";
  634. regulator-name = "vdd_pnl";
  635. regulator-min-microvolt = <2800000>;
  636. regulator-max-microvolt = <2800000>;
  637. gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
  638. enable-active-high;
  639. };
  640. vdd_bl_reg: regulator-bl {
  641. compatible = "regulator-fixed";
  642. regulator-name = "vdd_bl";
  643. regulator-min-microvolt = <2800000>;
  644. regulator-max-microvolt = <2800000>;
  645. gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
  646. enable-active-high;
  647. };
  648. vdd_5v0_hdmi: regulator-hdmi {
  649. compatible = "regulator-fixed";
  650. regulator-name = "VDDIO_HDMI";
  651. regulator-min-microvolt = <5000000>;
  652. regulator-max-microvolt = <5000000>;
  653. gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>;
  654. enable-active-high;
  655. vin-supply = <&vdd_5v0_reg>;
  656. };
  657. sound {
  658. compatible = "nvidia,tegra-audio-wm8903-harmony",
  659. "nvidia,tegra-audio-wm8903";
  660. nvidia,model = "NVIDIA Tegra Harmony";
  661. nvidia,audio-routing =
  662. "Headphone Jack", "HPOUTR",
  663. "Headphone Jack", "HPOUTL",
  664. "Int Spk", "ROP",
  665. "Int Spk", "RON",
  666. "Int Spk", "LOP",
  667. "Int Spk", "LON",
  668. "Mic Jack", "MICBIAS",
  669. "IN1L", "Mic Jack";
  670. nvidia,i2s-controller = <&tegra_i2s1>;
  671. nvidia,audio-codec = <&wm8903>;
  672. nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
  673. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
  674. GPIO_ACTIVE_LOW>;
  675. nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
  676. GPIO_ACTIVE_HIGH>;
  677. nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
  678. GPIO_ACTIVE_HIGH>;
  679. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  680. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  681. <&tegra_car TEGRA20_CLK_CDEV1>;
  682. clock-names = "pll_a", "pll_a_out0", "mclk";
  683. };
  684. };