tegra20-asus-tf101.dts 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include <dt-bindings/input/atmel-maxtouch.h>
  4. #include <dt-bindings/input/gpio-keys.h>
  5. #include <dt-bindings/input/input.h>
  6. #include <dt-bindings/thermal/thermal.h>
  7. #include "tegra20.dtsi"
  8. #include "tegra20-cpu-opp.dtsi"
  9. #include "tegra20-cpu-opp-microvolt.dtsi"
  10. / {
  11. model = "ASUS EeePad Transformer TF101";
  12. compatible = "asus,tf101", "nvidia,tegra20";
  13. chassis-type = "convertible";
  14. aliases {
  15. mmc0 = &sdmmc4; /* eMMC */
  16. mmc1 = &sdmmc3; /* MicroSD */
  17. mmc2 = &sdmmc1; /* WiFi */
  18. rtc0 = &pmic;
  19. rtc1 = "/rtc@7000e000";
  20. serial0 = &uartd;
  21. serial1 = &uartc; /* Bluetooth */
  22. serial2 = &uartb; /* GPS */
  23. };
  24. /*
  25. * The decompressor and also some bootloaders rely on a
  26. * pre-existing /chosen node to be available to insert the
  27. * command line and merge other ATAGS info.
  28. */
  29. chosen {};
  30. memory@0 {
  31. reg = <0x00000000 0x40000000>;
  32. };
  33. reserved-memory {
  34. #address-cells = <1>;
  35. #size-cells = <1>;
  36. ranges;
  37. ramoops@2ffe0000 {
  38. compatible = "ramoops";
  39. reg = <0x2ffe0000 0x10000>; /* 64kB */
  40. console-size = <0x8000>; /* 32kB */
  41. record-size = <0x400>; /* 1kB */
  42. ecc-size = <16>;
  43. };
  44. linux,cma@30000000 {
  45. compatible = "shared-dma-pool";
  46. alloc-ranges = <0x30000000 0x10000000>;
  47. size = <0x10000000>; /* 256MiB */
  48. linux,cma-default;
  49. reusable;
  50. };
  51. };
  52. host1x@50000000 {
  53. dc@54200000 {
  54. rgb {
  55. status = "okay";
  56. port@0 {
  57. lcd_output: endpoint {
  58. remote-endpoint = <&lvds_encoder_input>;
  59. bus-width = <18>;
  60. };
  61. };
  62. };
  63. };
  64. hdmi@54280000 {
  65. status = "okay";
  66. vdd-supply = <&hdmi_vdd_reg>;
  67. pll-supply = <&hdmi_pll_reg>;
  68. hdmi-supply = <&vdd_hdmi_en>;
  69. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  70. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  71. GPIO_ACTIVE_HIGH>;
  72. };
  73. };
  74. gpio@6000d000 {
  75. charging-enable-hog {
  76. gpio-hog;
  77. gpios = <TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
  78. output-low;
  79. };
  80. };
  81. pinmux@70000014 {
  82. pinctrl-names = "default";
  83. pinctrl-0 = <&state_default>;
  84. state_default: pinmux {
  85. ata {
  86. nvidia,pins = "ata";
  87. nvidia,function = "ide";
  88. };
  89. atb {
  90. nvidia,pins = "atb", "gma", "gme";
  91. nvidia,function = "sdio4";
  92. };
  93. atc {
  94. nvidia,pins = "atc";
  95. nvidia,function = "nand";
  96. };
  97. atd {
  98. nvidia,pins = "atd", "ate", "gmb", "spia",
  99. "spib", "spic";
  100. nvidia,function = "gmi";
  101. };
  102. cdev1 {
  103. nvidia,pins = "cdev1";
  104. nvidia,function = "plla_out";
  105. };
  106. cdev2 {
  107. nvidia,pins = "cdev2";
  108. nvidia,function = "pllp_out4";
  109. };
  110. crtp {
  111. nvidia,pins = "crtp";
  112. nvidia,function = "crt";
  113. };
  114. lm1 {
  115. nvidia,pins = "lm1";
  116. nvidia,function = "rsvd3";
  117. };
  118. csus {
  119. nvidia,pins = "csus";
  120. nvidia,function = "vi_sensor_clk";
  121. };
  122. dap1 {
  123. nvidia,pins = "dap1";
  124. nvidia,function = "dap1";
  125. };
  126. dap2 {
  127. nvidia,pins = "dap2";
  128. nvidia,function = "dap2";
  129. };
  130. dap3 {
  131. nvidia,pins = "dap3";
  132. nvidia,function = "dap3";
  133. };
  134. dap4 {
  135. nvidia,pins = "dap4";
  136. nvidia,function = "dap4";
  137. };
  138. dta {
  139. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  140. nvidia,function = "vi";
  141. };
  142. dtf {
  143. nvidia,pins = "dtf";
  144. nvidia,function = "i2c3";
  145. };
  146. gmc {
  147. nvidia,pins = "gmc";
  148. nvidia,function = "uartd";
  149. };
  150. gmd {
  151. nvidia,pins = "gmd";
  152. nvidia,function = "sflash";
  153. };
  154. gpu {
  155. nvidia,pins = "gpu";
  156. nvidia,function = "pwm";
  157. };
  158. gpu7 {
  159. nvidia,pins = "gpu7";
  160. nvidia,function = "rtck";
  161. };
  162. gpv {
  163. nvidia,pins = "gpv", "slxa";
  164. nvidia,function = "pcie";
  165. };
  166. hdint {
  167. nvidia,pins = "hdint";
  168. nvidia,function = "hdmi";
  169. };
  170. i2cp {
  171. nvidia,pins = "i2cp";
  172. nvidia,function = "i2cp";
  173. };
  174. irrx {
  175. nvidia,pins = "irrx", "irtx";
  176. nvidia,function = "uartb";
  177. };
  178. kbca {
  179. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  180. "kbce", "kbcf";
  181. nvidia,function = "kbc";
  182. };
  183. lcsn {
  184. nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
  185. "lsdi", "lvp0";
  186. nvidia,function = "rsvd4";
  187. };
  188. ld0 {
  189. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  190. "ld5", "ld6", "ld7", "ld8", "ld9",
  191. "ld10", "ld11", "ld12", "ld13", "ld14",
  192. "ld15", "ld16", "ld17", "ldi", "lhp0",
  193. "lhp1", "lhp2", "lhs", "lpp", "lpw0",
  194. "lpw2", "lsc0", "lsc1", "lsck", "lsda",
  195. "lspi", "lvp1", "lvs";
  196. nvidia,function = "displaya";
  197. };
  198. owc {
  199. nvidia,pins = "owc", "spdi", "spdo", "uac";
  200. nvidia,function = "rsvd2";
  201. };
  202. pmc {
  203. nvidia,pins = "pmc";
  204. nvidia,function = "pwr_on";
  205. };
  206. rm {
  207. nvidia,pins = "rm";
  208. nvidia,function = "i2c1";
  209. };
  210. sdb {
  211. nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk";
  212. nvidia,function = "sdio3";
  213. };
  214. sdio1 {
  215. nvidia,pins = "sdio1";
  216. nvidia,function = "sdio1";
  217. };
  218. slxd {
  219. nvidia,pins = "slxd";
  220. nvidia,function = "spdif";
  221. };
  222. spid {
  223. nvidia,pins = "spid", "spie", "spif";
  224. nvidia,function = "spi1";
  225. };
  226. spig {
  227. nvidia,pins = "spig", "spih";
  228. nvidia,function = "spi2_alt";
  229. };
  230. uaa {
  231. nvidia,pins = "uaa", "uab", "uda";
  232. nvidia,function = "ulpi";
  233. };
  234. uad {
  235. nvidia,pins = "uad";
  236. nvidia,function = "irda";
  237. };
  238. uca {
  239. nvidia,pins = "uca", "ucb";
  240. nvidia,function = "uartc";
  241. };
  242. conf_ata {
  243. nvidia,pins = "ata", "atb", "atc", "atd",
  244. "cdev1", "cdev2", "dap1", "dap4",
  245. "dte", "ddc", "dtf", "gma", "gmc",
  246. "gme", "gpu", "gpu7", "gpv", "i2cp",
  247. "irrx", "irtx", "pta", "rm", "sdc",
  248. "sdd", "slxc", "slxd", "slxk", "spdi",
  249. "spdo", "uac", "uad",
  250. "uda", "csus";
  251. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  252. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  253. };
  254. conf_ate {
  255. nvidia,pins = "ate", "dap2", "dap3", "gmb", "gmd",
  256. "owc", "spia", "spib", "spic",
  257. "spid", "spie", "spig", "slxa";
  258. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  259. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  260. };
  261. conf_ck32 {
  262. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  263. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  264. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  265. };
  266. conf_crtp {
  267. nvidia,pins = "crtp", "spih";
  268. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  269. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  270. };
  271. conf_dta {
  272. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  273. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  274. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  275. };
  276. conf_spif {
  277. nvidia,pins = "spif";
  278. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  279. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  280. };
  281. conf_hdint {
  282. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  283. "lpw1", "lsck", "lsda", "lsdi", "lvp0";
  284. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  285. };
  286. conf_kbca {
  287. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  288. "kbce", "kbcf", "sdio1", "uaa", "uab",
  289. "uca", "ucb";
  290. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  291. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  292. };
  293. conf_lc {
  294. nvidia,pins = "lc", "ls";
  295. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  296. };
  297. conf_ld0 {
  298. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  299. "ld5", "ld6", "ld7", "ld8", "ld9",
  300. "ld10", "ld11", "ld12", "ld13", "ld14",
  301. "ld15", "ld16", "ld17", "ldi", "lhp0",
  302. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  303. "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
  304. "lvp1", "lvs", "pmc", "sdb";
  305. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  306. };
  307. conf_ld17_0 {
  308. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  309. "ld23_22";
  310. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  311. };
  312. drive_sdio1 {
  313. nvidia,pins = "drive_sdio1", "drive_ddc", "drive_vi1";
  314. nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
  315. nvidia,schmitt = <TEGRA_PIN_ENABLE>;
  316. nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
  317. nvidia,pull-down-strength = <31>;
  318. nvidia,pull-up-strength = <31>;
  319. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  320. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  321. };
  322. drive_csus {
  323. nvidia,pins = "drive_csus";
  324. nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
  325. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  326. nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
  327. nvidia,pull-down-strength = <31>;
  328. nvidia,pull-up-strength = <31>;
  329. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  330. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  331. };
  332. };
  333. state_i2cmux_ddc: pinmux_i2cmux_ddc {
  334. ddc {
  335. nvidia,pins = "ddc";
  336. nvidia,function = "i2c2";
  337. };
  338. pta {
  339. nvidia,pins = "pta";
  340. nvidia,function = "rsvd4";
  341. };
  342. };
  343. state_i2cmux_pta: pinmux_i2cmux_pta {
  344. ddc {
  345. nvidia,pins = "ddc";
  346. nvidia,function = "rsvd4";
  347. };
  348. pta {
  349. nvidia,pins = "pta";
  350. nvidia,function = "i2c2";
  351. };
  352. };
  353. state_i2cmux_idle: pinmux_i2cmux_idle {
  354. ddc {
  355. nvidia,pins = "ddc";
  356. nvidia,function = "rsvd4";
  357. };
  358. pta {
  359. nvidia,pins = "pta";
  360. nvidia,function = "rsvd4";
  361. };
  362. };
  363. };
  364. spdif@70002400 {
  365. status = "okay";
  366. nvidia,fixed-parent-rate;
  367. };
  368. i2s@70002800 {
  369. status = "okay";
  370. nvidia,fixed-parent-rate;
  371. };
  372. serial@70006040 {
  373. compatible = "nvidia,tegra20-hsuart";
  374. /delete-property/ reg-shift;
  375. /* GPS BCM4751 */
  376. };
  377. serial@70006200 {
  378. compatible = "nvidia,tegra20-hsuart";
  379. /delete-property/ reg-shift;
  380. status = "okay";
  381. /* Azurewave AW-NH615 BCM4329B1 */
  382. bluetooth {
  383. compatible = "brcm,bcm4329-bt";
  384. interrupt-parent = <&gpio>;
  385. interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
  386. interrupt-names = "host-wakeup";
  387. /* PLLP 216MHz / 16 / 4 */
  388. max-speed = <3375000>;
  389. clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
  390. clock-names = "txco";
  391. vbat-supply = <&vdd_3v3_sys>;
  392. vddio-supply = <&vdd_1v8_sys>;
  393. device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
  394. shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
  395. };
  396. };
  397. serial@70006300 {
  398. status = "okay";
  399. };
  400. pwm@7000a000 {
  401. status = "okay";
  402. };
  403. i2c@7000c000 {
  404. status = "okay";
  405. clock-frequency = <400000>;
  406. /* Aichi AMI306 digital compass */
  407. magnetometer@e {
  408. compatible = "asahi-kasei,ak8974";
  409. reg = <0xe>;
  410. avdd-supply = <&vdd_3v3_sys>;
  411. dvdd-supply = <&vdd_1v8_sys>;
  412. mount-matrix = "-1", "0", "0",
  413. "0", "1", "0",
  414. "0", "0", "-1";
  415. };
  416. wm8903: audio-codec@1a {
  417. compatible = "wlf,wm8903";
  418. reg = <0x1a>;
  419. interrupt-parent = <&gpio>;
  420. interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_BOTH>;
  421. gpio-controller;
  422. #gpio-cells = <2>;
  423. micdet-cfg = <0x83>;
  424. micdet-delay = <100>;
  425. gpio-cfg = <
  426. 0xffffffff /* don't touch */
  427. 0xffffffff /* don't touch */
  428. 0x00000000 /* Speaker-enable GPIO, output, low */
  429. 0x00000400 /* Mic bias current detect */
  430. 0xffffffff /* don't touch */
  431. >;
  432. AVDD-supply = <&vdd_1v8_sys>;
  433. CPVDD-supply = <&vdd_1v8_sys>;
  434. DBVDD-supply = <&vdd_1v8_sys>;
  435. DCVDD-supply = <&vdd_1v8_sys>;
  436. };
  437. /* Atmel MXT1386 Touchscreen */
  438. touchscreen@5b {
  439. compatible = "atmel,maxtouch";
  440. reg = <0x5b>;
  441. interrupt-parent = <&gpio>;
  442. interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_LEVEL_LOW>;
  443. reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>;
  444. vdda-supply = <&vdd_3v3_sys>;
  445. vdd-supply = <&vdd_3v3_sys>;
  446. atmel,wakeup-method = <ATMEL_MXT_WAKEUP_I2C_SCL>;
  447. };
  448. gyroscope@68 {
  449. compatible = "invensense,mpu3050";
  450. reg = <0x68>;
  451. interrupt-parent = <&gpio>;
  452. interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_EDGE_RISING>;
  453. vdd-supply = <&vdd_3v3_sys>;
  454. vlogic-supply = <&vdd_1v8_sys>;
  455. mount-matrix = "0", "1", "0",
  456. "-1", "0", "0",
  457. "0", "0", "1";
  458. i2c-gate {
  459. #address-cells = <1>;
  460. #size-cells = <0>;
  461. accelerometer@f {
  462. compatible = "kionix,kxtf9";
  463. reg = <0xf>;
  464. interrupt-parent = <&gpio>;
  465. interrupts = <TEGRA_GPIO(N, 4) IRQ_TYPE_EDGE_RISING>;
  466. vdd-supply = <&vdd_1v8_sys>;
  467. vddio-supply = <&vdd_1v8_sys>;
  468. mount-matrix = "1", "0", "0",
  469. "0", "1", "0",
  470. "0", "0", "1";
  471. };
  472. };
  473. };
  474. };
  475. i2c2: i2c@7000c400 {
  476. status = "okay";
  477. clock-frequency = <100000>;
  478. };
  479. i2c@7000c500 {
  480. status = "okay";
  481. clock-frequency = <400000>;
  482. };
  483. i2c@7000d000 {
  484. status = "okay";
  485. clock-frequency = <400000>;
  486. pmic: pmic@34 {
  487. compatible = "ti,tps6586x";
  488. reg = <0x34>;
  489. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  490. ti,system-power-controller;
  491. #gpio-cells = <2>;
  492. gpio-controller;
  493. sys-supply = <&vdd_5v0_sys>;
  494. vin-sm0-supply = <&sys_reg>;
  495. vin-sm1-supply = <&sys_reg>;
  496. vin-sm2-supply = <&sys_reg>;
  497. vinldo01-supply = <&sm2_reg>;
  498. vinldo23-supply = <&sm2_reg>;
  499. vinldo4-supply = <&sm2_reg>;
  500. vinldo678-supply = <&sm2_reg>;
  501. vinldo9-supply = <&sm2_reg>;
  502. regulators {
  503. sys_reg: sys {
  504. regulator-name = "vdd_sys";
  505. regulator-always-on;
  506. };
  507. vdd_core: sm0 {
  508. regulator-name = "vdd_sm0,vdd_core";
  509. regulator-min-microvolt = <950000>;
  510. regulator-max-microvolt = <1300000>;
  511. regulator-coupled-with = <&rtc_vdd &vdd_cpu>;
  512. regulator-coupled-max-spread = <170000 550000>;
  513. regulator-always-on;
  514. regulator-boot-on;
  515. nvidia,tegra-core-regulator;
  516. };
  517. vdd_cpu: sm1 {
  518. regulator-name = "vdd_sm1,vdd_cpu";
  519. regulator-min-microvolt = <750000>;
  520. regulator-max-microvolt = <1125000>;
  521. regulator-coupled-with = <&vdd_core &rtc_vdd>;
  522. regulator-coupled-max-spread = <550000 550000>;
  523. regulator-always-on;
  524. regulator-boot-on;
  525. nvidia,tegra-cpu-regulator;
  526. };
  527. sm2_reg: sm2 {
  528. regulator-name = "vdd_sm2,vin_ldo*";
  529. regulator-min-microvolt = <3700000>;
  530. regulator-max-microvolt = <3700000>;
  531. regulator-always-on;
  532. };
  533. /* LDO0 is not connected to anything */
  534. ldo1 {
  535. regulator-name = "vdd_ldo1,avdd_pll*";
  536. regulator-min-microvolt = <1100000>;
  537. regulator-max-microvolt = <1100000>;
  538. regulator-always-on;
  539. };
  540. rtc_vdd: ldo2 {
  541. regulator-name = "vdd_ldo2,vdd_rtc";
  542. regulator-min-microvolt = <950000>;
  543. regulator-max-microvolt = <1300000>;
  544. regulator-coupled-with = <&vdd_core &vdd_cpu>;
  545. regulator-coupled-max-spread = <170000 550000>;
  546. regulator-always-on;
  547. regulator-boot-on;
  548. nvidia,tegra-rtc-regulator;
  549. };
  550. ldo3 {
  551. regulator-name = "vdd_ldo3,avdd_usb*";
  552. regulator-min-microvolt = <3300000>;
  553. regulator-max-microvolt = <3300000>;
  554. regulator-always-on;
  555. };
  556. ldo4 {
  557. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  558. regulator-min-microvolt = <1800000>;
  559. regulator-max-microvolt = <1800000>;
  560. regulator-always-on;
  561. };
  562. vcore_emmc: ldo5 {
  563. regulator-name = "vdd_ldo5,vcore_mmc";
  564. regulator-min-microvolt = <2850000>;
  565. regulator-max-microvolt = <2850000>;
  566. regulator-always-on;
  567. };
  568. ldo6 {
  569. regulator-name = "vdd_ldo6,avdd_vdac";
  570. regulator-min-microvolt = <1800000>;
  571. regulator-max-microvolt = <1800000>;
  572. };
  573. hdmi_vdd_reg: ldo7 {
  574. regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
  575. regulator-min-microvolt = <3300000>;
  576. regulator-max-microvolt = <3300000>;
  577. };
  578. hdmi_pll_reg: ldo8 {
  579. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  580. regulator-min-microvolt = <1800000>;
  581. regulator-max-microvolt = <1800000>;
  582. };
  583. ldo9 {
  584. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  585. regulator-min-microvolt = <2850000>;
  586. regulator-max-microvolt = <2850000>;
  587. regulator-always-on;
  588. };
  589. ldo_rtc {
  590. regulator-name = "vdd_rtc_out,vdd_cell";
  591. regulator-min-microvolt = <3300000>;
  592. regulator-max-microvolt = <3300000>;
  593. regulator-always-on;
  594. };
  595. };
  596. };
  597. nct1008: temperature-sensor@4c {
  598. compatible = "onnn,nct1008";
  599. reg = <0x4c>;
  600. vcc-supply = <&vdd_3v3_sys>;
  601. interrupt-parent = <&gpio>;
  602. interrupts = <TEGRA_GPIO(N, 6) IRQ_TYPE_EDGE_FALLING>;
  603. #thermal-sensor-cells = <1>;
  604. };
  605. };
  606. pmc@7000e400 {
  607. nvidia,invert-interrupt;
  608. nvidia,suspend-mode = <1>;
  609. nvidia,cpu-pwr-good-time = <2000>;
  610. nvidia,cpu-pwr-off-time = <100>;
  611. nvidia,core-pwr-good-time = <3845 3845>;
  612. nvidia,core-pwr-off-time = <458>;
  613. nvidia,sys-clock-req-active-high;
  614. core-supply = <&vdd_core>;
  615. };
  616. memory-controller@7000f400 {
  617. nvidia,use-ram-code;
  618. emc-tables@3 {
  619. reg = <0x3>;
  620. #address-cells = <1>;
  621. #size-cells = <0>;
  622. lpddr2 {
  623. compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4";
  624. revision-id = <1 0>;
  625. density = <2048>;
  626. io-width = <16>;
  627. };
  628. emc-table@25000 {
  629. reg = <25000>;
  630. compatible = "nvidia,tegra20-emc-table";
  631. clock-frequency = <25000>;
  632. nvidia,emc-registers = <0x00000002 0x00000006
  633. 0x00000003 0x00000003 0x00000006 0x00000004
  634. 0x00000002 0x00000009 0x00000003 0x00000003
  635. 0x00000002 0x00000002 0x00000002 0x00000004
  636. 0x00000003 0x00000008 0x0000000b 0x0000004d
  637. 0x00000000 0x00000003 0x00000003 0x00000003
  638. 0x00000008 0x00000001 0x0000000a 0x00000004
  639. 0x00000003 0x00000008 0x00000004 0x00000006
  640. 0x00000002 0x00000068 0x00000000 0x00000003
  641. 0x00000000 0x00000000 0x00000282 0xa0ae04ae
  642. 0x00070000 0x00000000 0x00000000 0x00000003
  643. 0x00000000 0x00000000 0x00000000 0x00000000>;
  644. };
  645. emc-table@50000 {
  646. reg = <50000>;
  647. compatible = "nvidia,tegra20-emc-table";
  648. clock-frequency = <50000>;
  649. nvidia,emc-registers = <0x00000003 0x00000007
  650. 0x00000003 0x00000003 0x00000006 0x00000004
  651. 0x00000002 0x00000009 0x00000003 0x00000003
  652. 0x00000002 0x00000002 0x00000002 0x00000005
  653. 0x00000003 0x00000008 0x0000000b 0x0000009f
  654. 0x00000000 0x00000003 0x00000003 0x00000003
  655. 0x00000008 0x00000001 0x0000000a 0x00000007
  656. 0x00000003 0x00000008 0x00000004 0x00000006
  657. 0x00000002 0x000000d0 0x00000000 0x00000000
  658. 0x00000000 0x00000000 0x00000282 0xa0ae04ae
  659. 0x00070000 0x00000000 0x00000000 0x00000005
  660. 0x00000000 0x00000000 0x00000000 0x00000000>;
  661. };
  662. emc-table@75000 {
  663. reg = <75000>;
  664. compatible = "nvidia,tegra20-emc-table";
  665. clock-frequency = <75000>;
  666. nvidia,emc-registers = <0x00000005 0x0000000a
  667. 0x00000004 0x00000003 0x00000006 0x00000004
  668. 0x00000002 0x00000009 0x00000003 0x00000003
  669. 0x00000002 0x00000002 0x00000002 0x00000005
  670. 0x00000003 0x00000008 0x0000000b 0x000000ff
  671. 0x00000000 0x00000003 0x00000003 0x00000003
  672. 0x00000008 0x00000001 0x0000000a 0x0000000b
  673. 0x00000003 0x00000008 0x00000004 0x00000006
  674. 0x00000002 0x00000138 0x00000000 0x00000000
  675. 0x00000000 0x00000000 0x00000282 0xa0ae04ae
  676. 0x00070000 0x00000000 0x00000000 0x00000007
  677. 0x00000000 0x00000000 0x00000000 0x00000000>;
  678. };
  679. emc-table@150000 {
  680. reg = <150000>;
  681. compatible = "nvidia,tegra20-emc-table";
  682. clock-frequency = <150000>;
  683. nvidia,emc-registers = <0x00000009 0x00000014
  684. 0x00000007 0x00000003 0x00000006 0x00000004
  685. 0x00000002 0x00000009 0x00000003 0x00000003
  686. 0x00000002 0x00000002 0x00000002 0x00000005
  687. 0x00000003 0x00000008 0x0000000b 0x0000021f
  688. 0x00000000 0x00000003 0x00000003 0x00000003
  689. 0x00000008 0x00000001 0x0000000a 0x00000015
  690. 0x00000003 0x00000008 0x00000004 0x00000006
  691. 0x00000002 0x00000270 0x00000000 0x00000001
  692. 0x00000000 0x00000000 0x00000282 0xa07c04ae
  693. 0x007dc010 0x00000000 0x00000000 0x0000000e
  694. 0x00000000 0x00000000 0x00000000 0x00000000>;
  695. };
  696. emc-table@300000 {
  697. reg = <300000>;
  698. compatible = "nvidia,tegra20-emc-table";
  699. clock-frequency = <300000>;
  700. nvidia,emc-registers = <0x00000012 0x00000027
  701. 0x0000000d 0x00000006 0x00000007 0x00000005
  702. 0x00000003 0x00000009 0x00000006 0x00000006
  703. 0x00000003 0x00000003 0x00000002 0x00000006
  704. 0x00000003 0x00000009 0x0000000c 0x0000045f
  705. 0x00000000 0x00000004 0x00000004 0x00000006
  706. 0x00000008 0x00000001 0x0000000e 0x0000002a
  707. 0x00000003 0x0000000f 0x00000007 0x00000005
  708. 0x00000002 0x000004e0 0x00000005 0x00000002
  709. 0x00000000 0x00000000 0x00000282 0xe059048b
  710. 0x007e0010 0x00000000 0x00000000 0x0000001b
  711. 0x00000000 0x00000000 0x00000000 0x00000000>;
  712. };
  713. };
  714. };
  715. /* Peripheral USB via ASUS connector */
  716. usb@c5000000 {
  717. compatible = "nvidia,tegra20-udc";
  718. status = "okay";
  719. dr_mode = "peripheral";
  720. };
  721. usb-phy@c5000000 {
  722. status = "okay";
  723. dr_mode = "peripheral";
  724. nvidia,xcvr-setup-use-fuses;
  725. nvidia,xcvr-lsfslew = <2>;
  726. nvidia,xcvr-lsrslew = <2>;
  727. vbus-supply = <&vdd_5v0_sys>;
  728. };
  729. /* Dock's USB port */
  730. usb@c5008000 {
  731. status = "okay";
  732. };
  733. usb-phy@c5008000 {
  734. status = "okay";
  735. nvidia,xcvr-setup-use-fuses;
  736. vbus-supply = <&vdd_5v0_sys>;
  737. };
  738. sdmmc1: mmc@c8000000 {
  739. status = "okay";
  740. #address-cells = <1>;
  741. #size-cells = <0>;
  742. assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
  743. assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
  744. assigned-clock-rates = <40000000>;
  745. max-frequency = <40000000>;
  746. keep-power-in-suspend;
  747. bus-width = <4>;
  748. non-removable;
  749. mmc-pwrseq = <&brcm_wifi_pwrseq>;
  750. vmmc-supply = <&vdd_3v3_sys>;
  751. vqmmc-supply = <&vdd_3v3_sys>;
  752. /* Azurewave AW-NH615 BCM4329B1 */
  753. wifi@1 {
  754. compatible = "brcm,bcm4329-fmac";
  755. reg = <1>;
  756. interrupt-parent = <&gpio>;
  757. interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>;
  758. interrupt-names = "host-wake";
  759. };
  760. };
  761. sdmmc3: mmc@c8000400 {
  762. status = "okay";
  763. bus-width = <4>;
  764. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  765. wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  766. power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
  767. vmmc-supply = <&vdd_3v3_sys>;
  768. vqmmc-supply = <&vdd_3v3_sys>;
  769. };
  770. sdmmc4: mmc@c8000600 {
  771. status = "okay";
  772. bus-width = <8>;
  773. vmmc-supply = <&vcore_emmc>;
  774. vqmmc-supply = <&vdd_3v3_sys>;
  775. non-removable;
  776. };
  777. mains: ac-adapter-detect {
  778. compatible = "gpio-charger";
  779. charger-type = "mains";
  780. gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
  781. };
  782. backlight: backlight {
  783. compatible = "pwm-backlight";
  784. enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
  785. power-supply = <&vdd_3v3_sys>;
  786. pwms = <&pwm 2 4000000>;
  787. brightness-levels = <7 255>;
  788. num-interpolated-steps = <248>;
  789. default-brightness-level = <20>;
  790. };
  791. /* PMIC has a built-in 32KHz oscillator which is used by PMC */
  792. clk32k_in: clock-32k-in {
  793. compatible = "fixed-clock";
  794. clock-frequency = <32768>;
  795. #clock-cells = <0>;
  796. };
  797. cpus {
  798. cpu0: cpu@0 {
  799. cpu-supply = <&vdd_cpu>;
  800. operating-points-v2 = <&cpu0_opp_table>;
  801. #cooling-cells = <2>;
  802. };
  803. cpu1: cpu@1 {
  804. cpu-supply = <&vdd_cpu>;
  805. operating-points-v2 = <&cpu0_opp_table>;
  806. #cooling-cells = <2>;
  807. };
  808. };
  809. gpio-keys {
  810. compatible = "gpio-keys";
  811. switch-dock-hall-sensor {
  812. label = "Lid";
  813. gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>;
  814. linux,input-type = <EV_SW>;
  815. linux,code = <SW_LID>;
  816. debounce-interval = <500>;
  817. wakeup-event-action = <EV_ACT_ASSERTED>;
  818. wakeup-source;
  819. };
  820. key-power {
  821. label = "Power";
  822. gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  823. linux,code = <KEY_POWER>;
  824. debounce-interval = <10>;
  825. wakeup-event-action = <EV_ACT_ASSERTED>;
  826. wakeup-source;
  827. };
  828. key-volume-up {
  829. label = "Volume Up";
  830. gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
  831. linux,code = <KEY_VOLUMEUP>;
  832. debounce-interval = <10>;
  833. wakeup-event-action = <EV_ACT_ASSERTED>;
  834. wakeup-source;
  835. };
  836. key-volume-down {
  837. label = "Volume Down";
  838. gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
  839. linux,code = <KEY_VOLUMEDOWN>;
  840. debounce-interval = <10>;
  841. wakeup-event-action = <EV_ACT_ASSERTED>;
  842. wakeup-source;
  843. };
  844. };
  845. display-panel {
  846. compatible = "panel-lvds";
  847. /* AUO B101EW05 using custom timings */
  848. backlight = <&backlight>;
  849. ddc-i2c-bus = <&lvds_ddc>;
  850. power-supply = <&vdd_pnl_reg>;
  851. width-mm = <218>;
  852. height-mm = <135>;
  853. data-mapping = "jeida-18";
  854. panel-timing {
  855. clock-frequency = <71200000>;
  856. hactive = <1280>;
  857. vactive = <800>;
  858. hfront-porch = <8>;
  859. hback-porch = <18>;
  860. hsync-len = <184>;
  861. vsync-len = <3>;
  862. vfront-porch = <4>;
  863. vback-porch = <8>;
  864. };
  865. port {
  866. panel_input: endpoint {
  867. remote-endpoint = <&lvds_encoder_output>;
  868. };
  869. };
  870. };
  871. i2cmux {
  872. compatible = "i2c-mux-pinctrl";
  873. #address-cells = <1>;
  874. #size-cells = <0>;
  875. i2c-parent = <&i2c2>;
  876. pinctrl-names = "ddc", "pta", "idle";
  877. pinctrl-0 = <&state_i2cmux_ddc>;
  878. pinctrl-1 = <&state_i2cmux_pta>;
  879. pinctrl-2 = <&state_i2cmux_idle>;
  880. hdmi_ddc: i2c@0 {
  881. reg = <0>;
  882. #address-cells = <1>;
  883. #size-cells = <0>;
  884. };
  885. lvds_ddc: i2c@1 {
  886. reg = <1>;
  887. #address-cells = <1>;
  888. #size-cells = <0>;
  889. smart-battery@b {
  890. compatible = "ti,bq20z75", "sbs,sbs-battery";
  891. reg = <0xb>;
  892. sbs,i2c-retry-count = <2>;
  893. sbs,poll-retry-count = <10>;
  894. power-supplies = <&mains>;
  895. };
  896. };
  897. };
  898. lvds-encoder {
  899. compatible = "ti,sn75lvds83", "lvds-encoder";
  900. powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>;
  901. power-supply = <&vdd_3v3_sys>;
  902. ports {
  903. #address-cells = <1>;
  904. #size-cells = <0>;
  905. port@0 {
  906. reg = <0>;
  907. lvds_encoder_input: endpoint {
  908. remote-endpoint = <&lcd_output>;
  909. };
  910. };
  911. port@1 {
  912. reg = <1>;
  913. lvds_encoder_output: endpoint {
  914. remote-endpoint = <&panel_input>;
  915. };
  916. };
  917. };
  918. };
  919. vdd_5v0_sys: regulator-5v0 {
  920. compatible = "regulator-fixed";
  921. regulator-name = "vdd_5v0";
  922. regulator-min-microvolt = <5000000>;
  923. regulator-max-microvolt = <5000000>;
  924. regulator-always-on;
  925. };
  926. vdd_3v3_sys: regulator-3v3 {
  927. compatible = "regulator-fixed";
  928. regulator-name = "vdd_3v3_vs";
  929. regulator-min-microvolt = <3300000>;
  930. regulator-max-microvolt = <3300000>;
  931. regulator-always-on;
  932. vin-supply = <&vdd_5v0_sys>;
  933. };
  934. regulator-pcie {
  935. compatible = "regulator-fixed";
  936. regulator-name = "pcie_vdd";
  937. regulator-min-microvolt = <1500000>;
  938. regulator-max-microvolt = <1500000>;
  939. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  940. regulator-always-on;
  941. };
  942. vdd_pnl_reg: regulator-panel {
  943. compatible = "regulator-fixed";
  944. regulator-name = "vdd_pnl";
  945. regulator-min-microvolt = <2800000>;
  946. regulator-max-microvolt = <2800000>;
  947. gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
  948. enable-active-high;
  949. };
  950. vdd_1v8_sys: regulator-1v8 {
  951. compatible = "regulator-fixed";
  952. regulator-name = "vdd_1v8_vs";
  953. regulator-min-microvolt = <1800000>;
  954. regulator-max-microvolt = <1800000>;
  955. regulator-always-on;
  956. vin-supply = <&vdd_5v0_sys>;
  957. };
  958. vdd_hdmi_en: regulator-hdmi {
  959. compatible = "regulator-fixed";
  960. regulator-name = "vdd_5v0_hdmi_en";
  961. regulator-min-microvolt = <5000000>;
  962. regulator-max-microvolt = <5000000>;
  963. regulator-always-on;
  964. vin-supply = <&vdd_5v0_sys>;
  965. gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
  966. enable-active-high;
  967. };
  968. sound {
  969. compatible = "asus,tegra-audio-wm8903-tf101",
  970. "nvidia,tegra-audio-wm8903";
  971. nvidia,model = "Asus EeePad Transformer WM8903";
  972. nvidia,audio-routing =
  973. "Headphone Jack", "HPOUTR",
  974. "Headphone Jack", "HPOUTL",
  975. "Int Spk", "ROP",
  976. "Int Spk", "RON",
  977. "Int Spk", "LOP",
  978. "Int Spk", "LON",
  979. "Mic Jack", "MICBIAS",
  980. "IN1L", "Mic Jack";
  981. nvidia,i2s-controller = <&tegra_i2s1>;
  982. nvidia,audio-codec = <&wm8903>;
  983. nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
  984. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
  985. nvidia,headset;
  986. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  987. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  988. <&tegra_car TEGRA20_CLK_CDEV1>;
  989. clock-names = "pll_a", "pll_a_out0", "mclk";
  990. };
  991. thermal-zones {
  992. /*
  993. * NCT1008 has two sensors:
  994. *
  995. * 0: internal that monitors ambient/skin temperature
  996. * 1: external that is connected to the CPU's diode
  997. *
  998. * Ideally we should use userspace thermal governor,
  999. * but it's a much more complex solution. The "skin"
  1000. * zone is a simpler solution which prevents TF101 from
  1001. * getting too hot from a user's tactile perspective.
  1002. * The CPU zone is intended to protect silicon from damage.
  1003. */
  1004. skin-thermal {
  1005. polling-delay-passive = <1000>; /* milliseconds */
  1006. polling-delay = <5000>; /* milliseconds */
  1007. thermal-sensors = <&nct1008 0>;
  1008. trips {
  1009. trip0: skin-alert {
  1010. /* start throttling at 60C */
  1011. temperature = <60000>;
  1012. hysteresis = <200>;
  1013. type = "passive";
  1014. };
  1015. trip1: skin-crit {
  1016. /* shut down at 70C */
  1017. temperature = <70000>;
  1018. hysteresis = <2000>;
  1019. type = "critical";
  1020. };
  1021. };
  1022. cooling-maps {
  1023. map0 {
  1024. trip = <&trip0>;
  1025. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1026. <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  1027. };
  1028. };
  1029. };
  1030. cpu-thermal {
  1031. polling-delay-passive = <1000>; /* milliseconds */
  1032. polling-delay = <5000>; /* milliseconds */
  1033. thermal-sensors = <&nct1008 1>;
  1034. trips {
  1035. trip2: cpu-alert {
  1036. /* throttle at 85C until temperature drops to 84.8C */
  1037. temperature = <85000>;
  1038. hysteresis = <200>;
  1039. type = "passive";
  1040. };
  1041. trip3: cpu-crit {
  1042. /* shut down at 90C */
  1043. temperature = <90000>;
  1044. hysteresis = <2000>;
  1045. type = "critical";
  1046. };
  1047. };
  1048. cooling-maps {
  1049. map1 {
  1050. trip = <&trip2>;
  1051. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1052. <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  1053. };
  1054. };
  1055. };
  1056. };
  1057. brcm_wifi_pwrseq: wifi-pwrseq {
  1058. compatible = "mmc-pwrseq-simple";
  1059. clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
  1060. clock-names = "ext_clock";
  1061. reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>;
  1062. post-power-on-delay-ms = <200>;
  1063. power-off-delay-us = <200>;
  1064. };
  1065. };
  1066. &emc_icc_dvfs_opp_table {
  1067. /delete-node/ opp-666000000;
  1068. /delete-node/ opp-760000000;
  1069. };