tegra20-acer-a500-picasso.dts 39 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include <dt-bindings/input/atmel-maxtouch.h>
  4. #include <dt-bindings/input/gpio-keys.h>
  5. #include <dt-bindings/input/input.h>
  6. #include <dt-bindings/thermal/thermal.h>
  7. #include "tegra20.dtsi"
  8. #include "tegra20-cpu-opp.dtsi"
  9. #include "tegra20-cpu-opp-microvolt.dtsi"
  10. / {
  11. model = "Acer Iconia Tab A500";
  12. compatible = "acer,picasso", "nvidia,tegra20";
  13. aliases {
  14. mmc0 = &sdmmc4; /* eMMC */
  15. mmc1 = &sdmmc3; /* MicroSD */
  16. mmc2 = &sdmmc1; /* WiFi */
  17. rtc0 = &pmic;
  18. rtc1 = "/rtc@7000e000";
  19. serial0 = &uartd; /* Docking station */
  20. serial1 = &uartc; /* Bluetooth */
  21. serial2 = &uartb; /* GPS */
  22. };
  23. /*
  24. * The decompressor and also some bootloaders rely on a
  25. * pre-existing /chosen node to be available to insert the
  26. * command line and merge other ATAGS info.
  27. */
  28. chosen {};
  29. memory@0 {
  30. reg = <0x00000000 0x40000000>;
  31. };
  32. reserved-memory {
  33. #address-cells = <1>;
  34. #size-cells = <1>;
  35. ranges;
  36. ramoops@2ffe0000 {
  37. compatible = "ramoops";
  38. reg = <0x2ffe0000 0x10000>; /* 64kB */
  39. console-size = <0x8000>; /* 32kB */
  40. record-size = <0x400>; /* 1kB */
  41. ecc-size = <16>;
  42. };
  43. linux,cma@30000000 {
  44. compatible = "shared-dma-pool";
  45. alloc-ranges = <0x30000000 0x10000000>;
  46. size = <0x10000000>; /* 256MiB */
  47. linux,cma-default;
  48. reusable;
  49. };
  50. };
  51. host1x@50000000 {
  52. dc@54200000 {
  53. rgb {
  54. status = "okay";
  55. port@0 {
  56. lcd_output: endpoint {
  57. remote-endpoint = <&lvds_encoder_input>;
  58. bus-width = <18>;
  59. };
  60. };
  61. };
  62. };
  63. hdmi@54280000 {
  64. status = "okay";
  65. vdd-supply = <&hdmi_vdd_reg>;
  66. pll-supply = <&hdmi_pll_reg>;
  67. hdmi-supply = <&vdd_5v0_sys>;
  68. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  69. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  70. GPIO_ACTIVE_HIGH>;
  71. };
  72. };
  73. pinmux@70000014 {
  74. pinctrl-names = "default";
  75. pinctrl-0 = <&state_default>;
  76. state_default: pinmux {
  77. ata {
  78. nvidia,pins = "ata";
  79. nvidia,function = "ide";
  80. };
  81. atb {
  82. nvidia,pins = "atb", "gma", "gme";
  83. nvidia,function = "sdio4";
  84. };
  85. atc {
  86. nvidia,pins = "atc";
  87. nvidia,function = "nand";
  88. };
  89. atd {
  90. nvidia,pins = "atd", "ate", "gmb", "spia",
  91. "spib", "spic";
  92. nvidia,function = "gmi";
  93. };
  94. cdev1 {
  95. nvidia,pins = "cdev1";
  96. nvidia,function = "plla_out";
  97. };
  98. cdev2 {
  99. nvidia,pins = "cdev2";
  100. nvidia,function = "pllp_out4";
  101. };
  102. crtp {
  103. nvidia,pins = "crtp", "lm1";
  104. nvidia,function = "crt";
  105. };
  106. csus {
  107. nvidia,pins = "csus";
  108. nvidia,function = "vi_sensor_clk";
  109. };
  110. dap1 {
  111. nvidia,pins = "dap1";
  112. nvidia,function = "dap1";
  113. };
  114. dap2 {
  115. nvidia,pins = "dap2";
  116. nvidia,function = "dap2";
  117. };
  118. dap3 {
  119. nvidia,pins = "dap3";
  120. nvidia,function = "dap3";
  121. };
  122. dap4 {
  123. nvidia,pins = "dap4";
  124. nvidia,function = "dap4";
  125. };
  126. dta {
  127. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  128. nvidia,function = "vi";
  129. };
  130. dtf {
  131. nvidia,pins = "dtf";
  132. nvidia,function = "i2c3";
  133. };
  134. gmc {
  135. nvidia,pins = "gmc";
  136. nvidia,function = "uartd";
  137. };
  138. gmd {
  139. nvidia,pins = "gmd";
  140. nvidia,function = "sflash";
  141. };
  142. gpu {
  143. nvidia,pins = "gpu";
  144. nvidia,function = "pwm";
  145. };
  146. gpu7 {
  147. nvidia,pins = "gpu7";
  148. nvidia,function = "rtck";
  149. };
  150. gpv {
  151. nvidia,pins = "gpv", "slxa";
  152. nvidia,function = "pcie";
  153. };
  154. hdint {
  155. nvidia,pins = "hdint";
  156. nvidia,function = "hdmi";
  157. };
  158. i2cp {
  159. nvidia,pins = "i2cp";
  160. nvidia,function = "i2cp";
  161. };
  162. irrx {
  163. nvidia,pins = "irrx", "irtx";
  164. nvidia,function = "uartb";
  165. };
  166. kbca {
  167. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  168. "kbce", "kbcf";
  169. nvidia,function = "kbc";
  170. };
  171. lcsn {
  172. nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
  173. "lsdi", "lvp0";
  174. nvidia,function = "rsvd4";
  175. };
  176. ld0 {
  177. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  178. "ld5", "ld6", "ld7", "ld8", "ld9",
  179. "ld10", "ld11", "ld12", "ld13", "ld14",
  180. "ld15", "ld16", "ld17", "ldi", "lhp0",
  181. "lhp1", "lhp2", "lhs", "lpp", "lsc0",
  182. "lsc1", "lsck", "lsda", "lspi", "lvp1",
  183. "lvs";
  184. nvidia,function = "displaya";
  185. };
  186. owc {
  187. nvidia,pins = "owc", "spdi", "spdo", "uac";
  188. nvidia,function = "rsvd2";
  189. };
  190. pmc {
  191. nvidia,pins = "pmc";
  192. nvidia,function = "pwr_on";
  193. };
  194. rm {
  195. nvidia,pins = "rm";
  196. nvidia,function = "i2c1";
  197. };
  198. sdb {
  199. nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk";
  200. nvidia,function = "sdio3";
  201. };
  202. sdio1 {
  203. nvidia,pins = "sdio1";
  204. nvidia,function = "sdio1";
  205. };
  206. slxd {
  207. nvidia,pins = "slxd";
  208. nvidia,function = "spdif";
  209. };
  210. spid {
  211. nvidia,pins = "spid", "spie", "spif";
  212. nvidia,function = "spi1";
  213. };
  214. spig {
  215. nvidia,pins = "spig", "spih";
  216. nvidia,function = "spi2_alt";
  217. };
  218. uaa {
  219. nvidia,pins = "uaa", "uab", "uda";
  220. nvidia,function = "ulpi";
  221. };
  222. uad {
  223. nvidia,pins = "uad";
  224. nvidia,function = "irda";
  225. };
  226. uca {
  227. nvidia,pins = "uca", "ucb";
  228. nvidia,function = "uartc";
  229. };
  230. conf_ata {
  231. nvidia,pins = "ata", "atb", "atc", "atd",
  232. "cdev1", "cdev2", "csus", "dap1",
  233. "dap4", "dte", "dtf", "gma", "gmc",
  234. "gme", "gpu", "gpu7", "gpv", "i2cp",
  235. "irrx", "irtx", "pta", "rm",
  236. "sdc", "sdd", "slxc", "slxd", "slxk",
  237. "spdi", "spdo", "uac", "uad", "uda";
  238. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  239. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  240. };
  241. conf_ate {
  242. nvidia,pins = "ate", "dap2", "dap3",
  243. "gmd", "owc", "spia", "spib", "spic",
  244. "spid", "spie";
  245. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  246. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  247. };
  248. conf_ck32 {
  249. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  250. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  251. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  252. };
  253. conf_crtp {
  254. nvidia,pins = "crtp", "gmb", "slxa", "spig",
  255. "spih";
  256. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  257. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  258. };
  259. conf_dta {
  260. nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb";
  261. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  262. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  263. };
  264. conf_dte {
  265. nvidia,pins = "spif";
  266. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  267. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  268. };
  269. conf_hdint {
  270. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  271. "lpw1", "lsck", "lsda", "lsdi",
  272. "lvp0";
  273. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  274. };
  275. conf_kbca {
  276. nvidia,pins = "kbca", "kbcc", "kbcd",
  277. "kbce", "kbcf", "sdio1", "uaa",
  278. "uab", "uca", "ucb";
  279. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  280. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  281. };
  282. conf_lc {
  283. nvidia,pins = "lc", "ls";
  284. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  285. };
  286. conf_ld0 {
  287. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  288. "ld5", "ld6", "ld7", "ld8", "ld9",
  289. "ld10", "ld11", "ld12", "ld13", "ld14",
  290. "ld15", "ld16", "ld17", "ldi", "lhp0",
  291. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  292. "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
  293. "lvp1", "lvs", "pmc", "sdb";
  294. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  295. };
  296. conf_ld17_0 {
  297. nvidia,pins = "ld17_0";
  298. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  299. };
  300. drive_ddc {
  301. nvidia,pins = "drive_ddc",
  302. "drive_vi1",
  303. "drive_sdio1";
  304. nvidia,pull-up-strength = <31>;
  305. nvidia,pull-down-strength = <31>;
  306. nvidia,schmitt = <TEGRA_PIN_ENABLE>;
  307. nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
  308. nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
  309. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  310. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  311. };
  312. drive_dbg {
  313. nvidia,pins = "drive_dbg",
  314. "drive_vi2",
  315. "drive_at1",
  316. "drive_ao1";
  317. nvidia,pull-up-strength = <31>;
  318. nvidia,pull-down-strength = <31>;
  319. nvidia,schmitt = <TEGRA_PIN_ENABLE>;
  320. nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
  321. nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
  322. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  323. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  324. };
  325. };
  326. state_i2cmux_ddc: pinmux_i2cmux_ddc {
  327. ddc {
  328. nvidia,pins = "ddc";
  329. nvidia,function = "i2c2";
  330. };
  331. pta {
  332. nvidia,pins = "pta";
  333. nvidia,function = "rsvd4";
  334. };
  335. };
  336. state_i2cmux_pta: pinmux_i2cmux_pta {
  337. ddc {
  338. nvidia,pins = "ddc";
  339. nvidia,function = "rsvd4";
  340. };
  341. pta {
  342. nvidia,pins = "pta";
  343. nvidia,function = "i2c2";
  344. };
  345. };
  346. state_i2cmux_idle: pinmux_i2cmux_idle {
  347. ddc {
  348. nvidia,pins = "ddc";
  349. nvidia,function = "rsvd4";
  350. };
  351. pta {
  352. nvidia,pins = "pta";
  353. nvidia,function = "rsvd4";
  354. };
  355. };
  356. };
  357. tegra_spdif: spdif@70002400 {
  358. status = "okay";
  359. nvidia,fixed-parent-rate;
  360. };
  361. tegra_i2s1: i2s@70002800 {
  362. status = "okay";
  363. nvidia,fixed-parent-rate;
  364. };
  365. uartb: serial@70006040 {
  366. compatible = "nvidia,tegra20-hsuart";
  367. /delete-property/ reg-shift;
  368. /* GPS BCM4751 */
  369. };
  370. uartc: serial@70006200 {
  371. compatible = "nvidia,tegra20-hsuart";
  372. /delete-property/ reg-shift;
  373. status = "okay";
  374. /* Azurewave AW-NH665 BCM4329B1 */
  375. bluetooth {
  376. compatible = "brcm,bcm4329-bt";
  377. interrupt-parent = <&gpio>;
  378. interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
  379. interrupt-names = "host-wakeup";
  380. /* PLLP 216MHz / 16 / 4 */
  381. max-speed = <3375000>;
  382. clocks = <&rtc_32k_wifi>;
  383. clock-names = "txco";
  384. vbat-supply = <&vdd_3v3_sys>;
  385. vddio-supply = <&vdd_1v8_sys>;
  386. device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
  387. shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
  388. };
  389. };
  390. uartd: serial@70006300 {
  391. /* Docking station */
  392. };
  393. i2c@7000c000 {
  394. clock-frequency = <400000>;
  395. status = "okay";
  396. wm8903: audio-codec@1a {
  397. compatible = "wlf,wm8903";
  398. reg = <0x1a>;
  399. interrupt-parent = <&gpio>;
  400. interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_EDGE_BOTH>;
  401. gpio-controller;
  402. #gpio-cells = <2>;
  403. micdet-cfg = <0>;
  404. micdet-delay = <100>;
  405. gpio-cfg = <
  406. 0x0000 /* MIC_LR_OUT# GPIO, output, low */
  407. 0x0000 /* FM2018-enable GPIO, output, low */
  408. 0x0000 /* Speaker-enable GPIO, output, low */
  409. 0x0200 /* Interrupt, output */
  410. 0x01a0 /* BCLK, input, active high */
  411. >;
  412. AVDD-supply = <&vdd_1v8_sys>;
  413. CPVDD-supply = <&vdd_1v8_sys>;
  414. DBVDD-supply = <&vdd_1v8_sys>;
  415. DCVDD-supply = <&vdd_1v8_sys>;
  416. };
  417. touchscreen@4c {
  418. compatible = "atmel,maxtouch";
  419. reg = <0x4c>;
  420. interrupt-parent = <&gpio>;
  421. interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_LEVEL_LOW>;
  422. reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>;
  423. vdda-supply = <&vdd_3v3_sys>;
  424. vdd-supply = <&vdd_3v3_sys>;
  425. atmel,wakeup-method = <ATMEL_MXT_WAKEUP_I2C_SCL>;
  426. };
  427. gyroscope@68 {
  428. compatible = "invensense,mpu3050";
  429. reg = <0x68>;
  430. interrupt-parent = <&gpio>;
  431. interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_EDGE_RISING>;
  432. vdd-supply = <&vdd_3v3_sys>;
  433. vlogic-supply = <&vdd_1v8_sys>;
  434. mount-matrix = "0", "1", "0",
  435. "1", "0", "0",
  436. "0", "0", "-1";
  437. i2c-gate {
  438. #address-cells = <1>;
  439. #size-cells = <0>;
  440. accelerometer@f {
  441. compatible = "kionix,kxtf9";
  442. reg = <0x0f>;
  443. interrupt-parent = <&gpio>;
  444. interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>;
  445. vdd-supply = <&vdd_1v8_sys>;
  446. vddio-supply = <&vdd_1v8_sys>;
  447. mount-matrix = "0", "1", "0",
  448. "1", "0", "0",
  449. "0", "0", "-1";
  450. };
  451. };
  452. };
  453. };
  454. i2c@7000c400 {
  455. clock-frequency = <10000>;
  456. status = "okay";
  457. };
  458. i2cmux {
  459. compatible = "i2c-mux-pinctrl";
  460. #address-cells = <1>;
  461. #size-cells = <0>;
  462. i2c-parent = <&{/i2c@7000c400}>;
  463. pinctrl-names = "ddc", "pta", "idle";
  464. pinctrl-0 = <&state_i2cmux_ddc>;
  465. pinctrl-1 = <&state_i2cmux_pta>;
  466. pinctrl-2 = <&state_i2cmux_idle>;
  467. hdmi_ddc: i2c@0 {
  468. reg = <0>;
  469. #address-cells = <1>;
  470. #size-cells = <0>;
  471. };
  472. panel_ddc: i2c@1 {
  473. reg = <1>;
  474. #address-cells = <1>;
  475. #size-cells = <0>;
  476. embedded-controller@58 {
  477. compatible = "acer,a500-iconia-ec", "ene,kb930";
  478. reg = <0x58>;
  479. system-power-controller;
  480. monitored-battery = <&bat1010>;
  481. power-supplies = <&mains>;
  482. };
  483. };
  484. };
  485. pwm: pwm@7000a000 {
  486. status = "okay";
  487. };
  488. i2c@7000d000 {
  489. clock-frequency = <100000>;
  490. status = "okay";
  491. magnetometer@c {
  492. compatible = "asahi-kasei,ak8975";
  493. reg = <0x0c>;
  494. interrupt-parent = <&gpio>;
  495. interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_EDGE_RISING>;
  496. vdd-supply = <&vdd_3v3_sys>;
  497. vid-supply = <&vdd_1v8_sys>;
  498. mount-matrix = "1", "0", "0",
  499. "0", "-1", "0",
  500. "0", "0", "-1";
  501. };
  502. pmic: pmic@34 {
  503. compatible = "ti,tps6586x";
  504. reg = <0x34>;
  505. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  506. #gpio-cells = <2>;
  507. gpio-controller;
  508. sys-supply = <&vdd_5v0_sys>;
  509. vin-sm0-supply = <&sys_reg>;
  510. vin-sm1-supply = <&sys_reg>;
  511. vin-sm2-supply = <&sys_reg>;
  512. vinldo01-supply = <&sm2_reg>;
  513. vinldo23-supply = <&sm2_reg>;
  514. vinldo4-supply = <&sm2_reg>;
  515. vinldo678-supply = <&sm2_reg>;
  516. vinldo9-supply = <&sm2_reg>;
  517. regulators {
  518. sys_reg: sys {
  519. regulator-name = "vdd_sys";
  520. regulator-always-on;
  521. };
  522. vdd_core: sm0 {
  523. regulator-name = "vdd_sm0,vdd_core";
  524. regulator-min-microvolt = <950000>;
  525. regulator-max-microvolt = <1300000>;
  526. regulator-coupled-with = <&rtc_vdd &vdd_cpu>;
  527. regulator-coupled-max-spread = <170000 550000>;
  528. regulator-always-on;
  529. regulator-boot-on;
  530. nvidia,tegra-core-regulator;
  531. };
  532. vdd_cpu: sm1 {
  533. regulator-name = "vdd_sm1,vdd_cpu";
  534. regulator-min-microvolt = <750000>;
  535. regulator-max-microvolt = <1125000>;
  536. regulator-coupled-with = <&vdd_core &rtc_vdd>;
  537. regulator-coupled-max-spread = <550000 550000>;
  538. regulator-always-on;
  539. regulator-boot-on;
  540. nvidia,tegra-cpu-regulator;
  541. };
  542. sm2_reg: sm2 {
  543. regulator-name = "vdd_sm2,vin_ldo*";
  544. regulator-min-microvolt = <3700000>;
  545. regulator-max-microvolt = <3700000>;
  546. regulator-always-on;
  547. };
  548. /* LDO0 is not connected to anything */
  549. ldo1 {
  550. regulator-name = "vdd_ldo1,avdd_pll*";
  551. regulator-min-microvolt = <1100000>;
  552. regulator-max-microvolt = <1100000>;
  553. regulator-always-on;
  554. regulator-boot-on;
  555. };
  556. rtc_vdd: ldo2 {
  557. regulator-name = "vdd_ldo2,vdd_rtc";
  558. regulator-min-microvolt = <950000>;
  559. regulator-max-microvolt = <1300000>;
  560. regulator-coupled-with = <&vdd_core &vdd_cpu>;
  561. regulator-coupled-max-spread = <170000 550000>;
  562. regulator-always-on;
  563. regulator-boot-on;
  564. nvidia,tegra-rtc-regulator;
  565. };
  566. ldo3 {
  567. regulator-name = "vdd_ldo3,avdd_usb*";
  568. regulator-min-microvolt = <3300000>;
  569. regulator-max-microvolt = <3300000>;
  570. regulator-always-on;
  571. };
  572. ldo4 {
  573. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  574. regulator-min-microvolt = <1800000>;
  575. regulator-max-microvolt = <1800000>;
  576. regulator-always-on;
  577. regulator-boot-on;
  578. };
  579. vcore_emmc: ldo5 {
  580. regulator-name = "vdd_ldo5,vcore_mmc";
  581. regulator-min-microvolt = <2850000>;
  582. regulator-max-microvolt = <2850000>;
  583. regulator-always-on;
  584. };
  585. avdd_vdac_reg: ldo6 {
  586. regulator-name = "vdd_ldo6,avdd_vdac";
  587. regulator-min-microvolt = <2850000>;
  588. regulator-max-microvolt = <2850000>;
  589. };
  590. hdmi_vdd_reg: ldo7 {
  591. regulator-name = "vdd_ldo7,avdd_hdmi";
  592. regulator-min-microvolt = <3300000>;
  593. regulator-max-microvolt = <3300000>;
  594. };
  595. hdmi_pll_reg: ldo8 {
  596. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  597. regulator-min-microvolt = <1800000>;
  598. regulator-max-microvolt = <1800000>;
  599. };
  600. ldo9 {
  601. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  602. regulator-min-microvolt = <2850000>;
  603. regulator-max-microvolt = <2850000>;
  604. regulator-always-on;
  605. regulator-boot-on;
  606. };
  607. ldo_rtc {
  608. regulator-name = "vdd_rtc_out,vdd_cell";
  609. regulator-min-microvolt = <3300000>;
  610. regulator-max-microvolt = <3300000>;
  611. regulator-always-on;
  612. regulator-boot-on;
  613. };
  614. };
  615. };
  616. nct1008: temperature-sensor@4c {
  617. compatible = "onnn,nct1008";
  618. reg = <0x4c>;
  619. vcc-supply = <&vdd_3v3_sys>;
  620. interrupt-parent = <&gpio>;
  621. interrupts = <TEGRA_GPIO(N, 6) IRQ_TYPE_EDGE_FALLING>;
  622. #thermal-sensor-cells = <1>;
  623. };
  624. };
  625. pmc@7000e400 {
  626. nvidia,invert-interrupt;
  627. nvidia,suspend-mode = <1>;
  628. nvidia,cpu-pwr-good-time = <2000>;
  629. nvidia,cpu-pwr-off-time = <100>;
  630. nvidia,core-pwr-good-time = <3845 3845>;
  631. nvidia,core-pwr-off-time = <458>;
  632. nvidia,sys-clock-req-active-high;
  633. core-supply = <&vdd_core>;
  634. };
  635. usb@c5000000 {
  636. compatible = "nvidia,tegra20-udc";
  637. status = "okay";
  638. dr_mode = "peripheral";
  639. };
  640. usb-phy@c5000000 {
  641. status = "okay";
  642. dr_mode = "peripheral";
  643. nvidia,xcvr-setup-use-fuses;
  644. nvidia,xcvr-lsfslew = <2>;
  645. nvidia,xcvr-lsrslew = <2>;
  646. };
  647. usb@c5008000 {
  648. status = "okay";
  649. };
  650. usb-phy@c5008000 {
  651. status = "okay";
  652. nvidia,xcvr-setup-use-fuses;
  653. nvidia,xcvr-lsfslew = <2>;
  654. nvidia,xcvr-lsrslew = <2>;
  655. vbus-supply = <&vdd_5v0_sys>;
  656. };
  657. brcm_wifi_pwrseq: wifi-pwrseq {
  658. compatible = "mmc-pwrseq-simple";
  659. clocks = <&rtc_32k_wifi>;
  660. clock-names = "ext_clock";
  661. reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>;
  662. post-power-on-delay-ms = <300>;
  663. power-off-delay-us = <300>;
  664. };
  665. sdmmc1: mmc@c8000000 {
  666. status = "okay";
  667. #address-cells = <1>;
  668. #size-cells = <0>;
  669. assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
  670. assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
  671. assigned-clock-rates = <50000000>;
  672. max-frequency = <50000000>;
  673. keep-power-in-suspend;
  674. bus-width = <4>;
  675. non-removable;
  676. mmc-pwrseq = <&brcm_wifi_pwrseq>;
  677. vmmc-supply = <&vdd_3v3_sys>;
  678. vqmmc-supply = <&vdd_1v8_sys>;
  679. /* Azurewave AW-NH611 BCM4329 */
  680. wifi@1 {
  681. reg = <1>;
  682. compatible = "brcm,bcm4329-fmac";
  683. interrupt-parent = <&gpio>;
  684. interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>;
  685. interrupt-names = "host-wake";
  686. };
  687. };
  688. sdmmc3: mmc@c8000400 {
  689. status = "okay";
  690. bus-width = <4>;
  691. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  692. power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
  693. vmmc-supply = <&vdd_3v3_sys>;
  694. vqmmc-supply = <&vdd_3v3_sys>;
  695. };
  696. sdmmc4: mmc@c8000600 {
  697. status = "okay";
  698. bus-width = <8>;
  699. vmmc-supply = <&vcore_emmc>;
  700. vqmmc-supply = <&vdd_3v3_sys>;
  701. non-removable;
  702. };
  703. mains: ac-adapter-detect {
  704. compatible = "gpio-charger";
  705. charger-type = "mains";
  706. gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
  707. };
  708. backlight: backlight {
  709. compatible = "pwm-backlight";
  710. enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
  711. power-supply = <&vdd_3v3_sys>;
  712. pwms = <&pwm 2 41667>;
  713. brightness-levels = <7 255>;
  714. num-interpolated-steps = <248>;
  715. default-brightness-level = <20>;
  716. };
  717. bat1010: battery-2s1p {
  718. compatible = "simple-battery";
  719. charge-full-design-microamp-hours = <3260000>;
  720. energy-full-design-microwatt-hours = <24000000>;
  721. operating-range-celsius = <0 40>;
  722. };
  723. /* PMIC has a built-in 32KHz oscillator which is used by PMC */
  724. clk32k_in: clock-32k-in {
  725. compatible = "fixed-clock";
  726. #clock-cells = <0>;
  727. clock-frequency = <32768>;
  728. clock-output-names = "tps658621-out32k";
  729. };
  730. /*
  731. * This standalone onboard fixed-clock always-ON 32KHz
  732. * oscillator is used as a reference clock-source by the
  733. * Azurewave WiFi/BT module.
  734. */
  735. rtc_32k_wifi: clock-32k-wifi {
  736. compatible = "fixed-clock";
  737. #clock-cells = <0>;
  738. clock-frequency = <32768>;
  739. clock-output-names = "kk3270032";
  740. };
  741. cpus {
  742. cpu0: cpu@0 {
  743. cpu-supply = <&vdd_cpu>;
  744. operating-points-v2 = <&cpu0_opp_table>;
  745. #cooling-cells = <2>;
  746. };
  747. cpu1: cpu@1 {
  748. cpu-supply = <&vdd_cpu>;
  749. operating-points-v2 = <&cpu0_opp_table>;
  750. #cooling-cells = <2>;
  751. };
  752. };
  753. display-panel {
  754. compatible = "auo,b101ew05", "panel-lvds";
  755. ddc-i2c-bus = <&panel_ddc>;
  756. power-supply = <&vdd_pnl>;
  757. backlight = <&backlight>;
  758. width-mm = <218>;
  759. height-mm = <135>;
  760. data-mapping = "jeida-18";
  761. panel-timing {
  762. clock-frequency = <71200000>;
  763. hactive = <1280>;
  764. vactive = <800>;
  765. hfront-porch = <8>;
  766. hback-porch = <18>;
  767. hsync-len = <184>;
  768. vsync-len = <3>;
  769. vfront-porch = <4>;
  770. vback-porch = <8>;
  771. };
  772. port {
  773. panel_input: endpoint {
  774. remote-endpoint = <&lvds_encoder_output>;
  775. };
  776. };
  777. };
  778. gpio-keys {
  779. compatible = "gpio-keys";
  780. key-power {
  781. label = "Power";
  782. gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
  783. linux,code = <KEY_POWER>;
  784. debounce-interval = <10>;
  785. wakeup-event-action = <EV_ACT_ASSERTED>;
  786. wakeup-source;
  787. };
  788. key-rotation-lock {
  789. label = "Rotate-lock";
  790. gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>;
  791. linux,code = <SW_ROTATE_LOCK>;
  792. linux,input-type = <EV_SW>;
  793. debounce-interval = <10>;
  794. };
  795. key-volume-up {
  796. label = "Volume Up";
  797. gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
  798. linux,code = <KEY_VOLUMEUP>;
  799. debounce-interval = <10>;
  800. wakeup-event-action = <EV_ACT_ASSERTED>;
  801. wakeup-source;
  802. };
  803. key-volume-down {
  804. label = "Volume Down";
  805. gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
  806. linux,code = <KEY_VOLUMEDOWN>;
  807. debounce-interval = <10>;
  808. wakeup-event-action = <EV_ACT_ASSERTED>;
  809. wakeup-source;
  810. };
  811. };
  812. haptic-feedback {
  813. compatible = "gpio-vibrator";
  814. enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
  815. vcc-supply = <&vdd_3v3_sys>;
  816. };
  817. lvds-encoder {
  818. compatible = "ti,sn75lvds83", "lvds-encoder";
  819. powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>;
  820. power-supply = <&vdd_3v3_sys>;
  821. ports {
  822. #address-cells = <1>;
  823. #size-cells = <0>;
  824. port@0 {
  825. reg = <0>;
  826. lvds_encoder_input: endpoint {
  827. remote-endpoint = <&lcd_output>;
  828. };
  829. };
  830. port@1 {
  831. reg = <1>;
  832. lvds_encoder_output: endpoint {
  833. remote-endpoint = <&panel_input>;
  834. };
  835. };
  836. };
  837. };
  838. vdd_5v0_sys: regulator-5v0 {
  839. compatible = "regulator-fixed";
  840. regulator-name = "vdd_5v0";
  841. regulator-min-microvolt = <5000000>;
  842. regulator-max-microvolt = <5000000>;
  843. regulator-always-on;
  844. };
  845. vdd_3v3_sys: regulator-3v3 {
  846. compatible = "regulator-fixed";
  847. regulator-name = "vdd_3v3_vs";
  848. regulator-min-microvolt = <3300000>;
  849. regulator-max-microvolt = <3300000>;
  850. regulator-always-on;
  851. vin-supply = <&vdd_5v0_sys>;
  852. };
  853. vdd_1v8_sys: regulator-1v8 {
  854. compatible = "regulator-fixed";
  855. regulator-name = "vdd_1v8_vs";
  856. regulator-min-microvolt = <1800000>;
  857. regulator-max-microvolt = <1800000>;
  858. regulator-always-on;
  859. vin-supply = <&vdd_5v0_sys>;
  860. };
  861. vdd_pnl: regulator-panel {
  862. compatible = "regulator-fixed";
  863. regulator-name = "vdd_panel";
  864. regulator-min-microvolt = <3300000>;
  865. regulator-max-microvolt = <3300000>;
  866. regulator-enable-ramp-delay = <300000>;
  867. gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
  868. enable-active-high;
  869. vin-supply = <&vdd_5v0_sys>;
  870. };
  871. sound {
  872. compatible = "nvidia,tegra-audio-wm8903-picasso",
  873. "nvidia,tegra-audio-wm8903";
  874. nvidia,model = "Acer Iconia Tab A500 WM8903";
  875. nvidia,audio-routing =
  876. "Headphone Jack", "HPOUTR",
  877. "Headphone Jack", "HPOUTL",
  878. "Int Spk", "LINEOUTL",
  879. "Int Spk", "LINEOUTR",
  880. "Mic Jack", "MICBIAS",
  881. "IN2L", "Mic Jack",
  882. "IN2R", "Mic Jack",
  883. "IN1L", "Int Mic",
  884. "IN1R", "Int Mic";
  885. nvidia,i2s-controller = <&tegra_i2s1>;
  886. nvidia,audio-codec = <&wm8903>;
  887. nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
  888. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
  889. nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>;
  890. nvidia,headset;
  891. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  892. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  893. <&tegra_car TEGRA20_CLK_CDEV1>;
  894. clock-names = "pll_a", "pll_a_out0", "mclk";
  895. };
  896. thermal-zones {
  897. /*
  898. * NCT1008 has two sensors:
  899. *
  900. * 0: internal that monitors ambient/skin temperature
  901. * 1: external that is connected to the CPU's diode
  902. *
  903. * Ideally we should use userspace thermal governor,
  904. * but it's a much more complex solution. The "skin"
  905. * zone is a simpler solution which prevents A500 from
  906. * getting too hot from a user's tactile perspective.
  907. * The CPU zone is intended to protect silicon from damage.
  908. */
  909. skin-thermal {
  910. polling-delay-passive = <1000>; /* milliseconds */
  911. polling-delay = <5000>; /* milliseconds */
  912. thermal-sensors = <&nct1008 0>;
  913. trips {
  914. trip0: skin-alert {
  915. /* start throttling at 60C */
  916. temperature = <60000>;
  917. hysteresis = <200>;
  918. type = "passive";
  919. };
  920. trip1: skin-crit {
  921. /* shut down at 70C */
  922. temperature = <70000>;
  923. hysteresis = <2000>;
  924. type = "critical";
  925. };
  926. };
  927. cooling-maps {
  928. map0 {
  929. trip = <&trip0>;
  930. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  931. <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  932. };
  933. };
  934. };
  935. cpu-thermal {
  936. polling-delay-passive = <1000>; /* milliseconds */
  937. polling-delay = <5000>; /* milliseconds */
  938. thermal-sensors = <&nct1008 1>;
  939. trips {
  940. trip2: cpu-alert {
  941. /* throttle at 85C until temperature drops to 84.8C */
  942. temperature = <85000>;
  943. hysteresis = <200>;
  944. type = "passive";
  945. };
  946. trip3: cpu-crit {
  947. /* shut down at 90C */
  948. temperature = <90000>;
  949. hysteresis = <2000>;
  950. type = "critical";
  951. };
  952. };
  953. cooling-maps {
  954. map1 {
  955. trip = <&trip2>;
  956. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  957. <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  958. };
  959. };
  960. };
  961. };
  962. memory-controller@7000f400 {
  963. nvidia,use-ram-code;
  964. emc-tables@0 {
  965. nvidia,ram-code = <0>; /* elpida-8gb */
  966. reg = <0>;
  967. #address-cells = <1>;
  968. #size-cells = <0>;
  969. emc-table@25000 {
  970. reg = <25000>;
  971. compatible = "nvidia,tegra20-emc-table";
  972. clock-frequency = <25000>;
  973. nvidia,emc-registers = <0x00000002 0x00000006
  974. 0x00000003 0x00000003 0x00000006 0x00000004
  975. 0x00000002 0x00000009 0x00000003 0x00000003
  976. 0x00000002 0x00000002 0x00000002 0x00000004
  977. 0x00000003 0x00000008 0x0000000b 0x0000004d
  978. 0x00000000 0x00000003 0x00000003 0x00000003
  979. 0x00000008 0x00000001 0x0000000a 0x00000004
  980. 0x00000003 0x00000008 0x00000004 0x00000006
  981. 0x00000002 0x00000068 0x00000000 0x00000003
  982. 0x00000000 0x00000000 0x00000282 0xa0ae04ae
  983. 0x00070000 0x00000000 0x00000000 0x00000003
  984. 0x00000000 0x00000000 0x00000000 0x00000000>;
  985. };
  986. emc-table@50000 {
  987. reg = <50000>;
  988. compatible = "nvidia,tegra20-emc-table";
  989. clock-frequency = <50000>;
  990. nvidia,emc-registers = <0x00000003 0x00000007
  991. 0x00000003 0x00000003 0x00000006 0x00000004
  992. 0x00000002 0x00000009 0x00000003 0x00000003
  993. 0x00000002 0x00000002 0x00000002 0x00000005
  994. 0x00000003 0x00000008 0x0000000b 0x0000009f
  995. 0x00000000 0x00000003 0x00000003 0x00000003
  996. 0x00000008 0x00000001 0x0000000a 0x00000007
  997. 0x00000003 0x00000008 0x00000004 0x00000006
  998. 0x00000002 0x000000d0 0x00000000 0x00000000
  999. 0x00000000 0x00000000 0x00000282 0xa0ae04ae
  1000. 0x00070000 0x00000000 0x00000000 0x00000005
  1001. 0x00000000 0x00000000 0x00000000 0x00000000>;
  1002. };
  1003. emc-table@75000 {
  1004. reg = <75000>;
  1005. compatible = "nvidia,tegra20-emc-table";
  1006. clock-frequency = <75000>;
  1007. nvidia,emc-registers = <0x00000005 0x0000000a
  1008. 0x00000004 0x00000003 0x00000006 0x00000004
  1009. 0x00000002 0x00000009 0x00000003 0x00000003
  1010. 0x00000002 0x00000002 0x00000002 0x00000005
  1011. 0x00000003 0x00000008 0x0000000b 0x000000ff
  1012. 0x00000000 0x00000003 0x00000003 0x00000003
  1013. 0x00000008 0x00000001 0x0000000a 0x0000000b
  1014. 0x00000003 0x00000008 0x00000004 0x00000006
  1015. 0x00000002 0x00000138 0x00000000 0x00000000
  1016. 0x00000000 0x00000000 0x00000282 0xa0ae04ae
  1017. 0x00070000 0x00000000 0x00000000 0x00000007
  1018. 0x00000000 0x00000000 0x00000000 0x00000000>;
  1019. };
  1020. emc-table@150000 {
  1021. reg = <150000>;
  1022. compatible = "nvidia,tegra20-emc-table";
  1023. clock-frequency = <150000>;
  1024. nvidia,emc-registers = <0x00000009 0x00000014
  1025. 0x00000007 0x00000003 0x00000006 0x00000004
  1026. 0x00000002 0x00000009 0x00000003 0x00000003
  1027. 0x00000002 0x00000002 0x00000002 0x00000005
  1028. 0x00000003 0x00000008 0x0000000b 0x0000021f
  1029. 0x00000000 0x00000003 0x00000003 0x00000003
  1030. 0x00000008 0x00000001 0x0000000a 0x00000015
  1031. 0x00000003 0x00000008 0x00000004 0x00000006
  1032. 0x00000002 0x00000270 0x00000000 0x00000001
  1033. 0x00000000 0x00000000 0x00000282 0xa07c04ae
  1034. 0x007dd510 0x00000000 0x00000000 0x0000000e
  1035. 0x00000000 0x00000000 0x00000000 0x00000000>;
  1036. };
  1037. emc-table@300000 {
  1038. reg = <300000>;
  1039. compatible = "nvidia,tegra20-emc-table";
  1040. clock-frequency = <300000>;
  1041. nvidia,emc-registers = <0x00000012 0x00000027
  1042. 0x0000000d 0x00000006 0x00000007 0x00000005
  1043. 0x00000003 0x00000009 0x00000006 0x00000006
  1044. 0x00000003 0x00000003 0x00000002 0x00000006
  1045. 0x00000003 0x00000009 0x0000000c 0x0000045f
  1046. 0x00000000 0x00000004 0x00000004 0x00000006
  1047. 0x00000008 0x00000001 0x0000000e 0x0000002a
  1048. 0x00000003 0x0000000f 0x00000007 0x00000005
  1049. 0x00000002 0x000004e1 0x00000005 0x00000002
  1050. 0x00000000 0x00000000 0x00000282 0xe059048b
  1051. 0x007e1510 0x00000000 0x00000000 0x0000001b
  1052. 0x00000000 0x00000000 0x00000000 0x00000000>;
  1053. };
  1054. };
  1055. emc-tables@1 {
  1056. nvidia,ram-code = <1>; /* elpida-4gb */
  1057. reg = <1>;
  1058. #address-cells = <1>;
  1059. #size-cells = <0>;
  1060. emc-table@25000 {
  1061. reg = <25000>;
  1062. compatible = "nvidia,tegra20-emc-table";
  1063. clock-frequency = <25000>;
  1064. nvidia,emc-registers = <0x00000002 0x00000006
  1065. 0x00000003 0x00000003 0x00000006 0x00000004
  1066. 0x00000002 0x00000009 0x00000003 0x00000003
  1067. 0x00000002 0x00000002 0x00000002 0x00000004
  1068. 0x00000003 0x00000008 0x0000000b 0x0000004d
  1069. 0x00000000 0x00000003 0x00000003 0x00000003
  1070. 0x00000008 0x00000001 0x0000000a 0x00000004
  1071. 0x00000003 0x00000008 0x00000004 0x00000006
  1072. 0x00000002 0x00000068 0x00000000 0x00000003
  1073. 0x00000000 0x00000000 0x00000282 0xa0ae04ae
  1074. 0x0007c000 0x00000000 0x00000000 0x00000003
  1075. 0x00000000 0x00000000 0x00000000 0x00000000>;
  1076. };
  1077. emc-table@50000 {
  1078. reg = <50000>;
  1079. compatible = "nvidia,tegra20-emc-table";
  1080. clock-frequency = <50000>;
  1081. nvidia,emc-registers = <0x00000003 0x00000007
  1082. 0x00000003 0x00000003 0x00000006 0x00000004
  1083. 0x00000002 0x00000009 0x00000003 0x00000003
  1084. 0x00000002 0x00000002 0x00000002 0x00000005
  1085. 0x00000003 0x00000008 0x0000000b 0x0000009f
  1086. 0x00000000 0x00000003 0x00000003 0x00000003
  1087. 0x00000008 0x00000001 0x0000000a 0x00000007
  1088. 0x00000003 0x00000008 0x00000004 0x00000006
  1089. 0x00000002 0x000000d0 0x00000000 0x00000000
  1090. 0x00000000 0x00000000 0x00000282 0xa0ae04ae
  1091. 0x0007c000 0x00000000 0x00000000 0x00000005
  1092. 0x00000000 0x00000000 0x00000000 0x00000000>;
  1093. };
  1094. emc-table@75000 {
  1095. reg = <75000>;
  1096. compatible = "nvidia,tegra20-emc-table";
  1097. clock-frequency = <75000>;
  1098. nvidia,emc-registers = <0x00000005 0x0000000a
  1099. 0x00000004 0x00000003 0x00000006 0x00000004
  1100. 0x00000002 0x00000009 0x00000003 0x00000003
  1101. 0x00000002 0x00000002 0x00000002 0x00000005
  1102. 0x00000003 0x00000008 0x0000000b 0x000000ff
  1103. 0x00000000 0x00000003 0x00000003 0x00000003
  1104. 0x00000008 0x00000001 0x0000000a 0x0000000b
  1105. 0x00000003 0x00000008 0x00000004 0x00000006
  1106. 0x00000002 0x00000138 0x00000000 0x00000000
  1107. 0x00000000 0x00000000 0x00000282 0xa0ae04ae
  1108. 0x0007c000 0x00000000 0x00000000 0x00000007
  1109. 0x00000000 0x00000000 0x00000000 0x00000000>;
  1110. };
  1111. emc-table@150000 {
  1112. reg = <150000>;
  1113. compatible = "nvidia,tegra20-emc-table";
  1114. clock-frequency = <150000>;
  1115. nvidia,emc-registers = <0x00000009 0x00000014
  1116. 0x00000007 0x00000003 0x00000006 0x00000004
  1117. 0x00000002 0x00000009 0x00000003 0x00000003
  1118. 0x00000002 0x00000002 0x00000002 0x00000005
  1119. 0x00000003 0x00000008 0x0000000b 0x0000021f
  1120. 0x00000000 0x00000003 0x00000003 0x00000003
  1121. 0x00000008 0x00000001 0x0000000a 0x00000015
  1122. 0x00000003 0x00000008 0x00000004 0x00000006
  1123. 0x00000002 0x00000270 0x00000000 0x00000001
  1124. 0x00000000 0x00000000 0x00000282 0xa07c04ae
  1125. 0x007e4010 0x00000000 0x00000000 0x0000000e
  1126. 0x00000000 0x00000000 0x00000000 0x00000000>;
  1127. };
  1128. emc-table@300000 {
  1129. reg = <300000>;
  1130. compatible = "nvidia,tegra20-emc-table";
  1131. clock-frequency = <300000>;
  1132. nvidia,emc-registers = <0x00000012 0x00000027
  1133. 0x0000000d 0x00000006 0x00000007 0x00000005
  1134. 0x00000003 0x00000009 0x00000006 0x00000006
  1135. 0x00000003 0x00000003 0x00000002 0x00000006
  1136. 0x00000003 0x00000009 0x0000000c 0x0000045f
  1137. 0x00000000 0x00000004 0x00000004 0x00000006
  1138. 0x00000008 0x00000001 0x0000000e 0x0000002a
  1139. 0x00000003 0x0000000f 0x00000007 0x00000005
  1140. 0x00000002 0x000004e1 0x00000005 0x00000002
  1141. 0x00000000 0x00000000 0x00000282 0xe059048b
  1142. 0x007e0010 0x00000000 0x00000000 0x0000001b
  1143. 0x00000000 0x00000000 0x00000000 0x00000000>;
  1144. };
  1145. };
  1146. emc-tables@2 {
  1147. nvidia,ram-code = <2>; /* hynix-8gb */
  1148. reg = <2>;
  1149. #address-cells = <1>;
  1150. #size-cells = <0>;
  1151. emc-table@25000 {
  1152. reg = <25000>;
  1153. compatible = "nvidia,tegra20-emc-table";
  1154. clock-frequency = <25000>;
  1155. nvidia,emc-registers = <0x00000002 0x00000006
  1156. 0x00000003 0x00000003 0x00000006 0x00000004
  1157. 0x00000002 0x00000009 0x00000003 0x00000003
  1158. 0x00000002 0x00000002 0x00000002 0x00000004
  1159. 0x00000003 0x00000008 0x0000000b 0x0000004d
  1160. 0x00000000 0x00000003 0x00000003 0x00000003
  1161. 0x00000008 0x00000001 0x0000000a 0x00000004
  1162. 0x00000003 0x00000008 0x00000004 0x00000006
  1163. 0x00000002 0x00000068 0x00000000 0x00000003
  1164. 0x00000000 0x00000000 0x00000282 0xa0ae04ae
  1165. 0x00070000 0x00000000 0x00000000 0x00000003
  1166. 0x00000000 0x00000000 0x00000000 0x00000000>;
  1167. };
  1168. emc-table@50000 {
  1169. reg = <50000>;
  1170. compatible = "nvidia,tegra20-emc-table";
  1171. clock-frequency = <50000>;
  1172. nvidia,emc-registers = <0x00000003 0x00000007
  1173. 0x00000003 0x00000003 0x00000006 0x00000004
  1174. 0x00000002 0x00000009 0x00000003 0x00000003
  1175. 0x00000002 0x00000002 0x00000002 0x00000005
  1176. 0x00000003 0x00000008 0x0000000b 0x0000009f
  1177. 0x00000000 0x00000003 0x00000003 0x00000003
  1178. 0x00000008 0x00000001 0x0000000a 0x00000007
  1179. 0x00000003 0x00000008 0x00000004 0x00000006
  1180. 0x00000002 0x000000d0 0x00000000 0x00000000
  1181. 0x00000000 0x00000000 0x00000282 0xa0ae04ae
  1182. 0x00070000 0x00000000 0x00000000 0x00000005
  1183. 0x00000000 0x00000000 0x00000000 0x00000000>;
  1184. };
  1185. emc-table@75000 {
  1186. reg = <75000>;
  1187. compatible = "nvidia,tegra20-emc-table";
  1188. clock-frequency = <75000>;
  1189. nvidia,emc-registers = <0x00000005 0x0000000a
  1190. 0x00000004 0x00000003 0x00000006 0x00000004
  1191. 0x00000002 0x00000009 0x00000003 0x00000003
  1192. 0x00000002 0x00000002 0x00000002 0x00000005
  1193. 0x00000003 0x00000008 0x0000000b 0x000000ff
  1194. 0x00000000 0x00000003 0x00000003 0x00000003
  1195. 0x00000008 0x00000001 0x0000000a 0x0000000b
  1196. 0x00000003 0x00000008 0x00000004 0x00000006
  1197. 0x00000002 0x00000138 0x00000000 0x00000000
  1198. 0x00000000 0x00000000 0x00000282 0xa0ae04ae
  1199. 0x00070000 0x00000000 0x00000000 0x00000007
  1200. 0x00000000 0x00000000 0x00000000 0x00000000>;
  1201. };
  1202. emc-table@150000 {
  1203. reg = <150000>;
  1204. compatible = "nvidia,tegra20-emc-table";
  1205. clock-frequency = <150000>;
  1206. nvidia,emc-registers = <0x00000009 0x00000014
  1207. 0x00000007 0x00000003 0x00000006 0x00000004
  1208. 0x00000002 0x00000009 0x00000003 0x00000003
  1209. 0x00000002 0x00000002 0x00000002 0x00000005
  1210. 0x00000003 0x00000008 0x0000000b 0x0000021f
  1211. 0x00000000 0x00000003 0x00000003 0x00000003
  1212. 0x00000008 0x00000001 0x0000000a 0x00000015
  1213. 0x00000003 0x00000008 0x00000004 0x00000006
  1214. 0x00000002 0x00000270 0x00000000 0x00000001
  1215. 0x00000000 0x00000000 0x00000282 0xa07c04ae
  1216. 0x007dd010 0x00000000 0x00000000 0x0000000e
  1217. 0x00000000 0x00000000 0x00000000 0x00000000>;
  1218. };
  1219. emc-table@300000 {
  1220. reg = <300000>;
  1221. compatible = "nvidia,tegra20-emc-table";
  1222. clock-frequency = <300000>;
  1223. nvidia,emc-registers = <0x00000012 0x00000027
  1224. 0x0000000d 0x00000006 0x00000007 0x00000005
  1225. 0x00000003 0x00000009 0x00000006 0x00000006
  1226. 0x00000003 0x00000003 0x00000002 0x00000006
  1227. 0x00000003 0x00000009 0x0000000c 0x0000045f
  1228. 0x00000000 0x00000004 0x00000004 0x00000006
  1229. 0x00000008 0x00000001 0x0000000e 0x0000002a
  1230. 0x00000003 0x0000000f 0x00000007 0x00000005
  1231. 0x00000002 0x000004e1 0x00000005 0x00000002
  1232. 0x00000000 0x00000000 0x00000282 0xe059048b
  1233. 0x007e2010 0x00000000 0x00000000 0x0000001b
  1234. 0x00000000 0x00000000 0x00000000 0x00000000>;
  1235. };
  1236. };
  1237. emc-tables@3 {
  1238. nvidia,ram-code = <3>; /* hynix-4gb */
  1239. reg = <3>;
  1240. #address-cells = <1>;
  1241. #size-cells = <0>;
  1242. emc-table@25000 {
  1243. reg = <25000>;
  1244. compatible = "nvidia,tegra20-emc-table";
  1245. clock-frequency = <25000>;
  1246. nvidia,emc-registers = <0x00000002 0x00000006
  1247. 0x00000003 0x00000003 0x00000006 0x00000004
  1248. 0x00000002 0x00000009 0x00000003 0x00000003
  1249. 0x00000002 0x00000002 0x00000002 0x00000004
  1250. 0x00000003 0x00000008 0x0000000b 0x0000004d
  1251. 0x00000000 0x00000003 0x00000003 0x00000003
  1252. 0x00000008 0x00000001 0x0000000a 0x00000004
  1253. 0x00000003 0x00000008 0x00000004 0x00000006
  1254. 0x00000002 0x00000068 0x00000000 0x00000003
  1255. 0x00000000 0x00000000 0x00000282 0xa0ae04ae
  1256. 0x0007c000 0x00000000 0x00000000 0x00000003
  1257. 0x00000000 0x00000000 0x00000000 0x00000000>;
  1258. };
  1259. emc-table@50000 {
  1260. reg = <50000>;
  1261. compatible = "nvidia,tegra20-emc-table";
  1262. clock-frequency = <50000>;
  1263. nvidia,emc-registers = <0x00000003 0x00000007
  1264. 0x00000003 0x00000003 0x00000006 0x00000004
  1265. 0x00000002 0x00000009 0x00000003 0x00000003
  1266. 0x00000002 0x00000002 0x00000002 0x00000005
  1267. 0x00000003 0x00000008 0x0000000b 0x0000009f
  1268. 0x00000000 0x00000003 0x00000003 0x00000003
  1269. 0x00000008 0x00000001 0x0000000a 0x00000007
  1270. 0x00000003 0x00000008 0x00000004 0x00000006
  1271. 0x00000002 0x000000d0 0x00000000 0x00000000
  1272. 0x00000000 0x00000000 0x00000282 0xa0ae04ae
  1273. 0x0007c000 0x00078000 0x00000000 0x00000005
  1274. 0x00000000 0x00000000 0x00000000 0x00000000>;
  1275. };
  1276. emc-table@75000 {
  1277. reg = <75000>;
  1278. compatible = "nvidia,tegra20-emc-table";
  1279. clock-frequency = <75000>;
  1280. nvidia,emc-registers = <0x00000005 0x0000000a
  1281. 0x00000004 0x00000003 0x00000006 0x00000004
  1282. 0x00000002 0x00000009 0x00000003 0x00000003
  1283. 0x00000002 0x00000002 0x00000002 0x00000005
  1284. 0x00000003 0x00000008 0x0000000b 0x000000ff
  1285. 0x00000000 0x00000003 0x00000003 0x00000003
  1286. 0x00000008 0x00000001 0x0000000a 0x0000000b
  1287. 0x00000003 0x00000008 0x00000004 0x00000006
  1288. 0x00000002 0x00000138 0x00000000 0x00000000
  1289. 0x00000000 0x00000000 0x00000282 0xa0ae04ae
  1290. 0x0007c000 0x00000000 0x00000000 0x00000007
  1291. 0x00000000 0x00000000 0x00000000 0x00000000>;
  1292. };
  1293. emc-table@150000 {
  1294. reg = <150000>;
  1295. compatible = "nvidia,tegra20-emc-table";
  1296. clock-frequency = <150000>;
  1297. nvidia,emc-registers = <0x00000009 0x00000014
  1298. 0x00000007 0x00000003 0x00000006 0x00000004
  1299. 0x00000002 0x00000009 0x00000003 0x00000003
  1300. 0x00000002 0x00000002 0x00000002 0x00000005
  1301. 0x00000003 0x00000008 0x0000000b 0x0000021f
  1302. 0x00000000 0x00000003 0x00000003 0x00000003
  1303. 0x00000008 0x00000001 0x0000000a 0x00000015
  1304. 0x00000003 0x00000008 0x00000004 0x00000006
  1305. 0x00000002 0x00000270 0x00000000 0x00000001
  1306. 0x00000000 0x00000000 0x00000282 0xa07c04ae
  1307. 0x007e4010 0x00000000 0x00000000 0x0000000e
  1308. 0x00000000 0x00000000 0x00000000 0x00000000>;
  1309. };
  1310. emc-table@300000 {
  1311. reg = <300000>;
  1312. compatible = "nvidia,tegra20-emc-table";
  1313. clock-frequency = <300000>;
  1314. nvidia,emc-registers = <0x00000012 0x00000027
  1315. 0x0000000d 0x00000006 0x00000007 0x00000005
  1316. 0x00000003 0x00000009 0x00000006 0x00000006
  1317. 0x00000003 0x00000003 0x00000002 0x00000006
  1318. 0x00000003 0x00000009 0x0000000c 0x0000045f
  1319. 0x00000000 0x00000004 0x00000004 0x00000006
  1320. 0x00000008 0x00000001 0x0000000e 0x0000002a
  1321. 0x00000003 0x0000000f 0x00000007 0x00000005
  1322. 0x00000002 0x000004e1 0x00000005 0x00000002
  1323. 0x00000000 0x00000000 0x00000282 0xe059048b
  1324. 0x007e0010 0x00000000 0x00000000 0x0000001b
  1325. 0x00000000 0x00000000 0x00000000 0x00000000>;
  1326. };
  1327. };
  1328. };
  1329. };
  1330. &emc_icc_dvfs_opp_table {
  1331. /delete-node/ opp-666000000;
  1332. /delete-node/ opp-760000000;
  1333. };