tegra124-nyan-blaze.dts 40 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include "tegra124-nyan.dtsi"
  4. #include "tegra124-nyan-blaze-emc.dtsi"
  5. / {
  6. model = "HP Chromebook 14";
  7. compatible = "google,nyan-blaze-rev10", "google,nyan-blaze-rev9",
  8. "google,nyan-blaze-rev8", "google,nyan-blaze-rev7",
  9. "google,nyan-blaze-rev6", "google,nyan-blaze-rev5",
  10. "google,nyan-blaze-rev4", "google,nyan-blaze-rev3",
  11. "google,nyan-blaze-rev2", "google,nyan-blaze-rev1",
  12. "google,nyan-blaze-rev0", "google,nyan-blaze",
  13. "google,nyan", "nvidia,tegra124";
  14. host1x@50000000 {
  15. dpaux@545c0000 {
  16. aux-bus {
  17. panel: panel {
  18. compatible = "samsung,ltn140at29-301";
  19. backlight = <&backlight>;
  20. };
  21. };
  22. };
  23. };
  24. sound {
  25. compatible = "nvidia,tegra-audio-max98090-nyan-blaze",
  26. "nvidia,tegra-audio-max98090-nyan",
  27. "nvidia,tegra-audio-max98090";
  28. nvidia,model = "GoogleNyanBlaze";
  29. };
  30. pinmux@70000868 {
  31. pinctrl-names = "default";
  32. pinctrl-0 = <&pinmux_default>;
  33. pinmux_default: common {
  34. clk_32k_out_pa0 {
  35. nvidia,pins = "clk_32k_out_pa0";
  36. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  37. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  38. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  39. };
  40. uart3_cts_n_pa1 {
  41. nvidia,pins = "uart3_cts_n_pa1";
  42. nvidia,function = "gmi";
  43. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  44. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  45. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  46. };
  47. dap2_fs_pa2 {
  48. nvidia,pins = "dap2_fs_pa2";
  49. nvidia,function = "i2s1";
  50. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  51. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  52. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  53. };
  54. dap2_sclk_pa3 {
  55. nvidia,pins = "dap2_sclk_pa3";
  56. nvidia,function = "i2s1";
  57. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  58. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  59. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  60. };
  61. dap2_din_pa4 {
  62. nvidia,pins = "dap2_din_pa4";
  63. nvidia,function = "i2s1";
  64. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  65. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  66. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  67. };
  68. dap2_dout_pa5 {
  69. nvidia,pins = "dap2_dout_pa5";
  70. nvidia,function = "i2s1";
  71. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  72. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  73. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  74. };
  75. sdmmc3_clk_pa6 {
  76. nvidia,pins = "sdmmc3_clk_pa6";
  77. nvidia,function = "sdmmc3";
  78. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  79. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  80. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  81. };
  82. sdmmc3_cmd_pa7 {
  83. nvidia,pins = "sdmmc3_cmd_pa7";
  84. nvidia,function = "sdmmc3";
  85. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  86. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  87. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  88. };
  89. pb0 {
  90. nvidia,pins = "pb0";
  91. nvidia,function = "rsvd2";
  92. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  93. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  94. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  95. };
  96. pb1 {
  97. nvidia,pins = "pb1";
  98. nvidia,function = "rsvd2";
  99. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  100. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  101. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  102. };
  103. sdmmc3_dat3_pb4 {
  104. nvidia,pins = "sdmmc3_dat3_pb4";
  105. nvidia,function = "sdmmc3";
  106. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  107. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  108. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  109. };
  110. sdmmc3_dat2_pb5 {
  111. nvidia,pins = "sdmmc3_dat2_pb5";
  112. nvidia,function = "sdmmc3";
  113. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  114. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  115. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  116. };
  117. sdmmc3_dat1_pb6 {
  118. nvidia,pins = "sdmmc3_dat1_pb6";
  119. nvidia,function = "sdmmc3";
  120. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  121. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  122. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  123. };
  124. sdmmc3_dat0_pb7 {
  125. nvidia,pins = "sdmmc3_dat0_pb7";
  126. nvidia,function = "sdmmc3";
  127. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  128. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  129. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  130. };
  131. uart3_rts_n_pc0 {
  132. nvidia,pins = "uart3_rts_n_pc0";
  133. nvidia,function = "gmi";
  134. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  135. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  136. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  137. };
  138. uart2_txd_pc2 {
  139. nvidia,pins = "uart2_txd_pc2";
  140. nvidia,function = "irda";
  141. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  142. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  143. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  144. };
  145. uart2_rxd_pc3 {
  146. nvidia,pins = "uart2_rxd_pc3";
  147. nvidia,function = "irda";
  148. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  149. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  150. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  151. };
  152. gen1_i2c_scl_pc4 {
  153. nvidia,pins = "gen1_i2c_scl_pc4";
  154. nvidia,function = "i2c1";
  155. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  156. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  157. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  158. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  159. };
  160. gen1_i2c_sda_pc5 {
  161. nvidia,pins = "gen1_i2c_sda_pc5";
  162. nvidia,function = "i2c1";
  163. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  164. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  165. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  166. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  167. };
  168. pc7 {
  169. nvidia,pins = "pc7";
  170. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  171. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  172. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  173. };
  174. pg0 {
  175. nvidia,pins = "pg0";
  176. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  177. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  178. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  179. };
  180. pg1 {
  181. nvidia,pins = "pg1";
  182. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  183. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  184. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  185. };
  186. pg2 {
  187. nvidia,pins = "pg2";
  188. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  189. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  190. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  191. };
  192. pg3 {
  193. nvidia,pins = "pg3";
  194. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  195. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  196. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  197. };
  198. pg4 {
  199. nvidia,pins = "pg4";
  200. nvidia,function = "spi4";
  201. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  202. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  203. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  204. };
  205. pg5 {
  206. nvidia,pins = "pg5";
  207. nvidia,function = "spi4";
  208. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  209. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  210. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  211. };
  212. pg6 {
  213. nvidia,pins = "pg6";
  214. nvidia,function = "spi4";
  215. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  216. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  217. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  218. };
  219. pg7 {
  220. nvidia,pins = "pg7";
  221. nvidia,function = "spi4";
  222. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  223. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  224. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  225. };
  226. ph0 {
  227. nvidia,pins = "ph0";
  228. nvidia,function = "gmi";
  229. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  230. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  231. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  232. };
  233. ph1 {
  234. nvidia,pins = "ph1";
  235. nvidia,function = "pwm1";
  236. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  237. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  238. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  239. };
  240. ph2 {
  241. nvidia,pins = "ph2";
  242. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  243. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  244. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  245. };
  246. ph3 {
  247. nvidia,pins = "ph3";
  248. nvidia,function = "gmi";
  249. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  250. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  251. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  252. };
  253. ph4 {
  254. nvidia,pins = "ph4";
  255. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  256. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  257. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  258. };
  259. ph5 {
  260. nvidia,pins = "ph5";
  261. nvidia,function = "rsvd2";
  262. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  263. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  264. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  265. };
  266. ph6 {
  267. nvidia,pins = "ph6";
  268. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  269. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  270. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  271. };
  272. ph7 {
  273. nvidia,pins = "ph7";
  274. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  275. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  276. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  277. };
  278. pi0 {
  279. nvidia,pins = "pi0";
  280. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  281. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  282. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  283. };
  284. pi1 {
  285. nvidia,pins = "pi1";
  286. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  287. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  288. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  289. };
  290. pi2 {
  291. nvidia,pins = "pi2";
  292. nvidia,function = "rsvd4";
  293. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  294. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  295. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  296. };
  297. pi3 {
  298. nvidia,pins = "pi3";
  299. nvidia,function = "spi4";
  300. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  301. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  302. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  303. };
  304. pi4 {
  305. nvidia,pins = "pi4";
  306. nvidia,function = "gmi";
  307. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  308. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  309. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  310. };
  311. pi5 {
  312. nvidia,pins = "pi5";
  313. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  314. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  315. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  316. };
  317. pi6 {
  318. nvidia,pins = "pi6";
  319. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  320. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  321. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  322. };
  323. pi7 {
  324. nvidia,pins = "pi7";
  325. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  326. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  327. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  328. };
  329. pj0 {
  330. nvidia,pins = "pj0";
  331. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  332. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  333. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  334. };
  335. pj2 {
  336. nvidia,pins = "pj2";
  337. nvidia,function = "rsvd1";
  338. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  339. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  340. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  341. };
  342. uart2_cts_n_pj5 {
  343. nvidia,pins = "uart2_cts_n_pj5";
  344. nvidia,function = "gmi";
  345. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  346. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  347. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  348. };
  349. uart2_rts_n_pj6 {
  350. nvidia,pins = "uart2_rts_n_pj6";
  351. nvidia,function = "gmi";
  352. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  353. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  354. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  355. };
  356. pj7 {
  357. nvidia,pins = "pj7";
  358. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  359. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  360. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  361. };
  362. pk0 {
  363. nvidia,pins = "pk0";
  364. nvidia,function = "rsvd1";
  365. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  366. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  367. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  368. };
  369. pk1 {
  370. nvidia,pins = "pk1";
  371. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  372. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  373. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  374. };
  375. pk2 {
  376. nvidia,pins = "pk2";
  377. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  378. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  379. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  380. };
  381. pk3 {
  382. nvidia,pins = "pk3";
  383. nvidia,function = "gmi";
  384. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  385. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  386. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  387. };
  388. pk4 {
  389. nvidia,pins = "pk4";
  390. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  391. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  392. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  393. };
  394. spdif_out_pk5 {
  395. nvidia,pins = "spdif_out_pk5";
  396. nvidia,function = "rsvd2";
  397. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  398. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  399. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  400. };
  401. spdif_in_pk6 {
  402. nvidia,pins = "spdif_in_pk6";
  403. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  404. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  405. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  406. };
  407. pk7 {
  408. nvidia,pins = "pk7";
  409. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  410. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  411. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  412. };
  413. dap1_fs_pn0 {
  414. nvidia,pins = "dap1_fs_pn0";
  415. nvidia,function = "rsvd4";
  416. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  417. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  418. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  419. };
  420. dap1_din_pn1 {
  421. nvidia,pins = "dap1_din_pn1";
  422. nvidia,function = "rsvd4";
  423. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  424. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  425. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  426. };
  427. dap1_dout_pn2 {
  428. nvidia,pins = "dap1_dout_pn2";
  429. nvidia,function = "i2s0";
  430. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  431. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  432. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  433. };
  434. dap1_sclk_pn3 {
  435. nvidia,pins = "dap1_sclk_pn3";
  436. nvidia,function = "rsvd4";
  437. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  438. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  439. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  440. };
  441. usb_vbus_en0_pn4 {
  442. nvidia,pins = "usb_vbus_en0_pn4";
  443. nvidia,function = "usb";
  444. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  445. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  446. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  447. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  448. };
  449. usb_vbus_en1_pn5 {
  450. nvidia,pins = "usb_vbus_en1_pn5";
  451. nvidia,function = "usb";
  452. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  453. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  454. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  455. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  456. };
  457. hdmi_int_pn7 {
  458. nvidia,pins = "hdmi_int_pn7";
  459. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  460. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  461. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  462. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  463. };
  464. ulpi_data7_po0 {
  465. nvidia,pins = "ulpi_data7_po0";
  466. nvidia,function = "ulpi";
  467. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  468. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  469. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  470. };
  471. ulpi_data0_po1 {
  472. nvidia,pins = "ulpi_data0_po1";
  473. nvidia,function = "ulpi";
  474. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  475. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  476. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  477. };
  478. ulpi_data1_po2 {
  479. nvidia,pins = "ulpi_data1_po2";
  480. nvidia,function = "ulpi";
  481. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  482. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  483. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  484. };
  485. ulpi_data2_po3 {
  486. nvidia,pins = "ulpi_data2_po3";
  487. nvidia,function = "ulpi";
  488. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  489. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  490. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  491. };
  492. ulpi_data3_po4 {
  493. nvidia,pins = "ulpi_data3_po4";
  494. nvidia,function = "ulpi";
  495. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  496. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  497. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  498. };
  499. ulpi_data4_po5 {
  500. nvidia,pins = "ulpi_data4_po5";
  501. nvidia,function = "ulpi";
  502. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  503. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  504. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  505. };
  506. ulpi_data5_po6 {
  507. nvidia,pins = "ulpi_data5_po6";
  508. nvidia,function = "ulpi";
  509. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  510. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  511. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  512. };
  513. ulpi_data6_po7 {
  514. nvidia,pins = "ulpi_data6_po7";
  515. nvidia,function = "ulpi";
  516. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  517. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  518. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  519. };
  520. dap3_fs_pp0 {
  521. nvidia,pins = "dap3_fs_pp0";
  522. nvidia,function = "i2s2";
  523. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  524. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  525. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  526. };
  527. dap3_din_pp1 {
  528. nvidia,pins = "dap3_din_pp1";
  529. nvidia,function = "i2s2";
  530. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  531. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  532. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  533. };
  534. dap3_dout_pp2 {
  535. nvidia,pins = "dap3_dout_pp2";
  536. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  537. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  538. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  539. };
  540. dap3_sclk_pp3 {
  541. nvidia,pins = "dap3_sclk_pp3";
  542. nvidia,function = "rsvd3";
  543. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  544. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  545. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  546. };
  547. dap4_fs_pp4 {
  548. nvidia,pins = "dap4_fs_pp4";
  549. nvidia,function = "rsvd4";
  550. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  551. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  552. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  553. };
  554. dap4_din_pp5 {
  555. nvidia,pins = "dap4_din_pp5";
  556. nvidia,function = "rsvd3";
  557. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  558. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  559. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  560. };
  561. dap4_dout_pp6 {
  562. nvidia,pins = "dap4_dout_pp6";
  563. nvidia,function = "rsvd4";
  564. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  565. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  566. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  567. };
  568. dap4_sclk_pp7 {
  569. nvidia,pins = "dap4_sclk_pp7";
  570. nvidia,function = "rsvd3";
  571. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  572. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  573. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  574. };
  575. kb_col0_pq0 {
  576. nvidia,pins = "kb_col0_pq0";
  577. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  578. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  579. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  580. };
  581. kb_col1_pq1 {
  582. nvidia,pins = "kb_col1_pq1";
  583. nvidia,function = "rsvd2";
  584. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  585. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  586. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  587. };
  588. kb_col2_pq2 {
  589. nvidia,pins = "kb_col2_pq2";
  590. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  591. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  592. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  593. };
  594. kb_col3_pq3 {
  595. nvidia,pins = "kb_col3_pq3";
  596. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  597. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  598. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  599. };
  600. kb_col4_pq4 {
  601. nvidia,pins = "kb_col4_pq4";
  602. nvidia,function = "sdmmc3";
  603. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  604. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  605. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  606. };
  607. kb_col5_pq5 {
  608. nvidia,pins = "kb_col5_pq5";
  609. nvidia,function = "rsvd2";
  610. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  611. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  612. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  613. };
  614. kb_col6_pq6 {
  615. nvidia,pins = "kb_col6_pq6";
  616. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  617. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  618. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  619. };
  620. kb_col7_pq7 {
  621. nvidia,pins = "kb_col7_pq7";
  622. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  623. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  624. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  625. };
  626. kb_row0_pr0 {
  627. nvidia,pins = "kb_row0_pr0";
  628. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  629. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  630. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  631. };
  632. kb_row1_pr1 {
  633. nvidia,pins = "kb_row1_pr1";
  634. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  635. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  636. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  637. };
  638. kb_row2_pr2 {
  639. nvidia,pins = "kb_row2_pr2";
  640. nvidia,function = "rsvd2";
  641. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  642. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  643. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  644. };
  645. kb_row3_pr3 {
  646. nvidia,pins = "kb_row3_pr3";
  647. nvidia,function = "kbc";
  648. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  649. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  650. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  651. };
  652. kb_row4_pr4 {
  653. nvidia,pins = "kb_row4_pr4";
  654. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  655. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  656. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  657. };
  658. kb_row5_pr5 {
  659. nvidia,pins = "kb_row5_pr5";
  660. nvidia,function = "rsvd3";
  661. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  662. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  663. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  664. };
  665. kb_row6_pr6 {
  666. nvidia,pins = "kb_row6_pr6";
  667. nvidia,function = "kbc";
  668. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  669. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  670. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  671. };
  672. kb_row7_pr7 {
  673. nvidia,pins = "kb_row7_pr7";
  674. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  675. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  676. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  677. };
  678. kb_row8_ps0 {
  679. nvidia,pins = "kb_row8_ps0";
  680. nvidia,function = "rsvd2";
  681. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  682. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  683. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  684. };
  685. kb_row9_ps1 {
  686. nvidia,pins = "kb_row9_ps1";
  687. nvidia,function = "uarta";
  688. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  689. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  690. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  691. };
  692. kb_row10_ps2 {
  693. nvidia,pins = "kb_row10_ps2";
  694. nvidia,function = "uarta";
  695. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  696. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  697. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  698. };
  699. kb_row11_ps3 {
  700. nvidia,pins = "kb_row11_ps3";
  701. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  702. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  703. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  704. };
  705. kb_row12_ps4 {
  706. nvidia,pins = "kb_row12_ps4";
  707. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  708. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  709. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  710. };
  711. kb_row13_ps5 {
  712. nvidia,pins = "kb_row13_ps5";
  713. nvidia,function = "rsvd2";
  714. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  715. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  716. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  717. };
  718. kb_row14_ps6 {
  719. nvidia,pins = "kb_row14_ps6";
  720. nvidia,function = "rsvd2";
  721. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  722. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  723. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  724. };
  725. kb_row15_ps7 {
  726. nvidia,pins = "kb_row15_ps7";
  727. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  728. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  729. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  730. };
  731. kb_row16_pt0 {
  732. nvidia,pins = "kb_row16_pt0";
  733. nvidia,function = "rsvd2";
  734. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  735. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  736. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  737. };
  738. kb_row17_pt1 {
  739. nvidia,pins = "kb_row17_pt1";
  740. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  741. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  742. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  743. };
  744. gen2_i2c_scl_pt5 {
  745. nvidia,pins = "gen2_i2c_scl_pt5";
  746. nvidia,function = "i2c2";
  747. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  748. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  749. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  750. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  751. };
  752. gen2_i2c_sda_pt6 {
  753. nvidia,pins = "gen2_i2c_sda_pt6";
  754. nvidia,function = "i2c2";
  755. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  756. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  757. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  758. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  759. };
  760. sdmmc4_cmd_pt7 {
  761. nvidia,pins = "sdmmc4_cmd_pt7";
  762. nvidia,function = "sdmmc4";
  763. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  764. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  765. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  766. };
  767. pu0 {
  768. nvidia,pins = "pu0";
  769. nvidia,function = "rsvd4";
  770. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  771. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  772. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  773. };
  774. pu1 {
  775. nvidia,pins = "pu1";
  776. nvidia,function = "rsvd1";
  777. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  778. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  779. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  780. };
  781. pu2 {
  782. nvidia,pins = "pu2";
  783. nvidia,function = "rsvd1";
  784. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  785. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  786. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  787. };
  788. pu3 {
  789. nvidia,pins = "pu3";
  790. nvidia,function = "gmi";
  791. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  792. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  793. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  794. };
  795. pu4 {
  796. nvidia,pins = "pu4";
  797. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  798. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  799. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  800. };
  801. pu5 {
  802. nvidia,pins = "pu5";
  803. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  804. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  805. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  806. };
  807. pu6 {
  808. nvidia,pins = "pu6";
  809. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  810. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  811. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  812. };
  813. pv0 {
  814. nvidia,pins = "pv0";
  815. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  816. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  817. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  818. };
  819. pv1 {
  820. nvidia,pins = "pv1";
  821. nvidia,function = "rsvd1";
  822. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  823. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  824. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  825. };
  826. sdmmc3_cd_n_pv2 {
  827. nvidia,pins = "sdmmc3_cd_n_pv2";
  828. nvidia,function = "sdmmc3";
  829. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  830. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  831. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  832. };
  833. sdmmc1_wp_n_pv3 {
  834. nvidia,pins = "sdmmc1_wp_n_pv3";
  835. nvidia,function = "sdmmc1";
  836. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  837. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  838. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  839. };
  840. ddc_scl_pv4 {
  841. nvidia,pins = "ddc_scl_pv4";
  842. nvidia,function = "i2c4";
  843. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  844. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  845. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  846. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  847. };
  848. ddc_sda_pv5 {
  849. nvidia,pins = "ddc_sda_pv5";
  850. nvidia,function = "i2c4";
  851. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  852. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  853. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  854. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  855. };
  856. gpio_w2_aud_pw2 {
  857. nvidia,pins = "gpio_w2_aud_pw2";
  858. nvidia,function = "rsvd2";
  859. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  860. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  861. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  862. };
  863. gpio_w3_aud_pw3 {
  864. nvidia,pins = "gpio_w3_aud_pw3";
  865. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  866. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  867. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  868. };
  869. dap_mclk1_pw4 {
  870. nvidia,pins = "dap_mclk1_pw4";
  871. nvidia,function = "extperiph1";
  872. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  873. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  874. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  875. };
  876. clk2_out_pw5 {
  877. nvidia,pins = "clk2_out_pw5";
  878. nvidia,function = "rsvd2";
  879. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  880. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  881. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  882. };
  883. uart3_txd_pw6 {
  884. nvidia,pins = "uart3_txd_pw6";
  885. nvidia,function = "rsvd2";
  886. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  887. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  888. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  889. };
  890. uart3_rxd_pw7 {
  891. nvidia,pins = "uart3_rxd_pw7";
  892. nvidia,function = "rsvd2";
  893. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  894. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  895. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  896. };
  897. dvfs_pwm_px0 {
  898. nvidia,pins = "dvfs_pwm_px0";
  899. nvidia,function = "cldvfs";
  900. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  901. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  902. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  903. };
  904. gpio_x1_aud_px1 {
  905. nvidia,pins = "gpio_x1_aud_px1";
  906. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  907. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  908. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  909. };
  910. dvfs_clk_px2 {
  911. nvidia,pins = "dvfs_clk_px2";
  912. nvidia,function = "cldvfs";
  913. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  914. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  915. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  916. };
  917. gpio_x3_aud_px3 {
  918. nvidia,pins = "gpio_x3_aud_px3";
  919. nvidia,function = "rsvd4";
  920. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  921. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  922. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  923. };
  924. gpio_x4_aud_px4 {
  925. nvidia,pins = "gpio_x4_aud_px4";
  926. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  927. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  928. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  929. };
  930. gpio_x5_aud_px5 {
  931. nvidia,pins = "gpio_x5_aud_px5";
  932. nvidia,function = "rsvd4";
  933. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  934. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  935. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  936. };
  937. gpio_x6_aud_px6 {
  938. nvidia,pins = "gpio_x6_aud_px6";
  939. nvidia,function = "gmi";
  940. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  941. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  942. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  943. };
  944. gpio_x7_aud_px7 {
  945. nvidia,pins = "gpio_x7_aud_px7";
  946. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  947. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  948. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  949. };
  950. ulpi_clk_py0 {
  951. nvidia,pins = "ulpi_clk_py0";
  952. nvidia,function = "spi1";
  953. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  954. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  955. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  956. };
  957. ulpi_dir_py1 {
  958. nvidia,pins = "ulpi_dir_py1";
  959. nvidia,function = "spi1";
  960. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  961. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  962. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  963. };
  964. ulpi_nxt_py2 {
  965. nvidia,pins = "ulpi_nxt_py2";
  966. nvidia,function = "spi1";
  967. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  968. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  969. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  970. };
  971. ulpi_stp_py3 {
  972. nvidia,pins = "ulpi_stp_py3";
  973. nvidia,function = "spi1";
  974. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  975. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  976. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  977. };
  978. sdmmc1_dat3_py4 {
  979. nvidia,pins = "sdmmc1_dat3_py4";
  980. nvidia,function = "sdmmc1";
  981. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  982. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  983. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  984. };
  985. sdmmc1_dat2_py5 {
  986. nvidia,pins = "sdmmc1_dat2_py5";
  987. nvidia,function = "sdmmc1";
  988. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  989. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  990. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  991. };
  992. sdmmc1_dat1_py6 {
  993. nvidia,pins = "sdmmc1_dat1_py6";
  994. nvidia,function = "sdmmc1";
  995. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  996. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  997. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  998. };
  999. sdmmc1_dat0_py7 {
  1000. nvidia,pins = "sdmmc1_dat0_py7";
  1001. nvidia,function = "sdmmc1";
  1002. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1003. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1004. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1005. };
  1006. sdmmc1_clk_pz0 {
  1007. nvidia,pins = "sdmmc1_clk_pz0";
  1008. nvidia,function = "sdmmc1";
  1009. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1010. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1011. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1012. };
  1013. sdmmc1_cmd_pz1 {
  1014. nvidia,pins = "sdmmc1_cmd_pz1";
  1015. nvidia,function = "sdmmc1";
  1016. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1017. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1018. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1019. };
  1020. pwr_i2c_scl_pz6 {
  1021. nvidia,pins = "pwr_i2c_scl_pz6";
  1022. nvidia,function = "i2cpwr";
  1023. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1024. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1025. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1026. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1027. };
  1028. pwr_i2c_sda_pz7 {
  1029. nvidia,pins = "pwr_i2c_sda_pz7";
  1030. nvidia,function = "i2cpwr";
  1031. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1032. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1033. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1034. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1035. };
  1036. sdmmc4_dat0_paa0 {
  1037. nvidia,pins = "sdmmc4_dat0_paa0";
  1038. nvidia,function = "sdmmc4";
  1039. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1040. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1041. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1042. };
  1043. sdmmc4_dat1_paa1 {
  1044. nvidia,pins = "sdmmc4_dat1_paa1";
  1045. nvidia,function = "sdmmc4";
  1046. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1047. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1048. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1049. };
  1050. sdmmc4_dat2_paa2 {
  1051. nvidia,pins = "sdmmc4_dat2_paa2";
  1052. nvidia,function = "sdmmc4";
  1053. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1054. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1055. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1056. };
  1057. sdmmc4_dat3_paa3 {
  1058. nvidia,pins = "sdmmc4_dat3_paa3";
  1059. nvidia,function = "sdmmc4";
  1060. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1061. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1062. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1063. };
  1064. sdmmc4_dat4_paa4 {
  1065. nvidia,pins = "sdmmc4_dat4_paa4";
  1066. nvidia,function = "sdmmc4";
  1067. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1068. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1069. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1070. };
  1071. sdmmc4_dat5_paa5 {
  1072. nvidia,pins = "sdmmc4_dat5_paa5";
  1073. nvidia,function = "sdmmc4";
  1074. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1075. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1076. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1077. };
  1078. sdmmc4_dat6_paa6 {
  1079. nvidia,pins = "sdmmc4_dat6_paa6";
  1080. nvidia,function = "sdmmc4";
  1081. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1082. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1083. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1084. };
  1085. sdmmc4_dat7_paa7 {
  1086. nvidia,pins = "sdmmc4_dat7_paa7";
  1087. nvidia,function = "sdmmc4";
  1088. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1089. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1090. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1091. };
  1092. pbb0 {
  1093. nvidia,pins = "pbb0";
  1094. nvidia,function = "vgp6";
  1095. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1096. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1097. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1098. };
  1099. cam_i2c_scl_pbb1 {
  1100. nvidia,pins = "cam_i2c_scl_pbb1";
  1101. nvidia,function = "i2c3";
  1102. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1103. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1104. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1105. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1106. };
  1107. cam_i2c_sda_pbb2 {
  1108. nvidia,pins = "cam_i2c_sda_pbb2";
  1109. nvidia,function = "i2c3";
  1110. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1111. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1112. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1113. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1114. };
  1115. pbb3 {
  1116. nvidia,pins = "pbb3";
  1117. nvidia,function = "vgp3";
  1118. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1119. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1120. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1121. };
  1122. pbb4 {
  1123. nvidia,pins = "pbb4";
  1124. nvidia,function = "vgp4";
  1125. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1126. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1127. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1128. };
  1129. pbb5 {
  1130. nvidia,pins = "pbb5";
  1131. nvidia,function = "rsvd3";
  1132. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1133. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1134. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1135. };
  1136. pbb6 {
  1137. nvidia,pins = "pbb6";
  1138. nvidia,function = "rsvd2";
  1139. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1140. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1141. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1142. };
  1143. pbb7 {
  1144. nvidia,pins = "pbb7";
  1145. nvidia,function = "rsvd2";
  1146. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1147. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1148. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1149. };
  1150. cam_mclk_pcc0 {
  1151. nvidia,pins = "cam_mclk_pcc0";
  1152. nvidia,function = "vi";
  1153. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1154. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1155. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1156. };
  1157. pcc1 {
  1158. nvidia,pins = "pcc1";
  1159. nvidia,function = "rsvd2";
  1160. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1161. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1162. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1163. };
  1164. pcc2 {
  1165. nvidia,pins = "pcc2";
  1166. nvidia,function = "rsvd2";
  1167. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1168. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1169. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1170. };
  1171. sdmmc4_clk_pcc4 {
  1172. nvidia,pins = "sdmmc4_clk_pcc4";
  1173. nvidia,function = "sdmmc4";
  1174. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1175. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1176. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1177. };
  1178. clk2_req_pcc5 {
  1179. nvidia,pins = "clk2_req_pcc5";
  1180. nvidia,function = "rsvd2";
  1181. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1182. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1183. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1184. };
  1185. pex_l0_rst_n_pdd1 {
  1186. nvidia,pins = "pex_l0_rst_n_pdd1";
  1187. nvidia,function = "rsvd2";
  1188. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1189. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1190. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1191. };
  1192. pex_l0_clkreq_n_pdd2 {
  1193. nvidia,pins = "pex_l0_clkreq_n_pdd2";
  1194. nvidia,function = "rsvd2";
  1195. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1196. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1197. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1198. };
  1199. pex_wake_n_pdd3 {
  1200. nvidia,pins = "pex_wake_n_pdd3";
  1201. nvidia,function = "rsvd2";
  1202. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1203. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1204. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1205. };
  1206. pex_l1_rst_n_pdd5 {
  1207. nvidia,pins = "pex_l1_rst_n_pdd5";
  1208. nvidia,function = "rsvd2";
  1209. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1210. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1211. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1212. };
  1213. pex_l1_clkreq_n_pdd6 {
  1214. nvidia,pins = "pex_l1_clkreq_n_pdd6";
  1215. nvidia,function = "rsvd2";
  1216. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1217. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1218. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1219. };
  1220. clk3_out_pee0 {
  1221. nvidia,pins = "clk3_out_pee0";
  1222. nvidia,function = "rsvd2";
  1223. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1224. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1225. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1226. };
  1227. clk3_req_pee1 {
  1228. nvidia,pins = "clk3_req_pee1";
  1229. nvidia,function = "rsvd2";
  1230. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1231. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1232. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1233. };
  1234. dap_mclk1_req_pee2 {
  1235. nvidia,pins = "dap_mclk1_req_pee2";
  1236. nvidia,function = "rsvd4";
  1237. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1238. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1239. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1240. };
  1241. hdmi_cec_pee3 {
  1242. nvidia,pins = "hdmi_cec_pee3";
  1243. nvidia,function = "cec";
  1244. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1245. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1246. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1247. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1248. };
  1249. sdmmc3_clk_lb_out_pee4 {
  1250. nvidia,pins = "sdmmc3_clk_lb_out_pee4";
  1251. nvidia,function = "sdmmc3";
  1252. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1253. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1254. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1255. };
  1256. sdmmc3_clk_lb_in_pee5 {
  1257. nvidia,pins = "sdmmc3_clk_lb_in_pee5";
  1258. nvidia,function = "sdmmc3";
  1259. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1260. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1261. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1262. };
  1263. dp_hpd_pff0 {
  1264. nvidia,pins = "dp_hpd_pff0";
  1265. nvidia,function = "dp";
  1266. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1267. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1268. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1269. };
  1270. usb_vbus_en2_pff1 {
  1271. nvidia,pins = "usb_vbus_en2_pff1";
  1272. nvidia,function = "rsvd2";
  1273. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1274. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1275. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1276. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1277. };
  1278. pff2 {
  1279. nvidia,pins = "pff2";
  1280. nvidia,function = "rsvd2";
  1281. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1282. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1283. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1284. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1285. };
  1286. core_pwr_req {
  1287. nvidia,pins = "core_pwr_req";
  1288. nvidia,function = "pwron";
  1289. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1290. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1291. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1292. };
  1293. cpu_pwr_req {
  1294. nvidia,pins = "cpu_pwr_req";
  1295. nvidia,function = "cpu";
  1296. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1297. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1298. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1299. };
  1300. pwr_int_n {
  1301. nvidia,pins = "pwr_int_n";
  1302. nvidia,function = "pmi";
  1303. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1304. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1305. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1306. };
  1307. reset_out_n {
  1308. nvidia,pins = "reset_out_n";
  1309. nvidia,function = "reset_out_n";
  1310. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1311. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1312. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1313. };
  1314. owr {
  1315. nvidia,pins = "owr";
  1316. nvidia,function = "rsvd2";
  1317. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1318. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1319. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1320. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  1321. };
  1322. clk_32k_in {
  1323. nvidia,pins = "clk_32k_in";
  1324. nvidia,function = "clk";
  1325. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1326. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1327. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1328. };
  1329. jtag_rtck {
  1330. nvidia,pins = "jtag_rtck";
  1331. nvidia,function = "rtck";
  1332. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1333. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1334. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1335. };
  1336. };
  1337. };
  1338. };