tegra124-nyan-big.dts 40 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include "tegra124-nyan.dtsi"
  4. #include "tegra124-nyan-big-emc.dtsi"
  5. / {
  6. model = "Acer Chromebook 13 CB5-311";
  7. compatible = "google,nyan-big-rev7", "google,nyan-big-rev6",
  8. "google,nyan-big-rev5", "google,nyan-big-rev4",
  9. "google,nyan-big-rev3", "google,nyan-big-rev2",
  10. "google,nyan-big-rev1", "google,nyan-big-rev0",
  11. "google,nyan-big", "google,nyan", "nvidia,tegra124";
  12. host1x@50000000 {
  13. dpaux@545c0000 {
  14. aux-bus {
  15. panel: panel {
  16. compatible = "auo,b133xtn01";
  17. backlight = <&backlight>;
  18. };
  19. };
  20. };
  21. };
  22. mmc@700b0400 { /* SD Card on this bus */
  23. wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
  24. };
  25. sound {
  26. compatible = "nvidia,tegra-audio-max98090-nyan-big",
  27. "nvidia,tegra-audio-max98090-nyan",
  28. "nvidia,tegra-audio-max98090";
  29. nvidia,model = "GoogleNyanBig";
  30. };
  31. pinmux@70000868 {
  32. pinctrl-names = "default";
  33. pinctrl-0 = <&pinmux_default>;
  34. pinmux_default: common {
  35. clk_32k_out_pa0 {
  36. nvidia,pins = "clk_32k_out_pa0";
  37. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  38. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  39. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  40. };
  41. uart3_cts_n_pa1 {
  42. nvidia,pins = "uart3_cts_n_pa1";
  43. nvidia,function = "gmi";
  44. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  45. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  46. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  47. };
  48. dap2_fs_pa2 {
  49. nvidia,pins = "dap2_fs_pa2";
  50. nvidia,function = "i2s1";
  51. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  52. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  53. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  54. };
  55. dap2_sclk_pa3 {
  56. nvidia,pins = "dap2_sclk_pa3";
  57. nvidia,function = "i2s1";
  58. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  59. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  60. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  61. };
  62. dap2_din_pa4 {
  63. nvidia,pins = "dap2_din_pa4";
  64. nvidia,function = "i2s1";
  65. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  66. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  67. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  68. };
  69. dap2_dout_pa5 {
  70. nvidia,pins = "dap2_dout_pa5";
  71. nvidia,function = "i2s1";
  72. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  73. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  74. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  75. };
  76. sdmmc3_clk_pa6 {
  77. nvidia,pins = "sdmmc3_clk_pa6";
  78. nvidia,function = "sdmmc3";
  79. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  80. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  81. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  82. };
  83. sdmmc3_cmd_pa7 {
  84. nvidia,pins = "sdmmc3_cmd_pa7";
  85. nvidia,function = "sdmmc3";
  86. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  87. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  88. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  89. };
  90. pb0 {
  91. nvidia,pins = "pb0";
  92. nvidia,function = "rsvd2";
  93. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  94. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  95. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  96. };
  97. pb1 {
  98. nvidia,pins = "pb1";
  99. nvidia,function = "rsvd2";
  100. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  101. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  102. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  103. };
  104. sdmmc3_dat3_pb4 {
  105. nvidia,pins = "sdmmc3_dat3_pb4";
  106. nvidia,function = "sdmmc3";
  107. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  108. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  109. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  110. };
  111. sdmmc3_dat2_pb5 {
  112. nvidia,pins = "sdmmc3_dat2_pb5";
  113. nvidia,function = "sdmmc3";
  114. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  115. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  116. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  117. };
  118. sdmmc3_dat1_pb6 {
  119. nvidia,pins = "sdmmc3_dat1_pb6";
  120. nvidia,function = "sdmmc3";
  121. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  122. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  123. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  124. };
  125. sdmmc3_dat0_pb7 {
  126. nvidia,pins = "sdmmc3_dat0_pb7";
  127. nvidia,function = "sdmmc3";
  128. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  129. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  130. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  131. };
  132. uart3_rts_n_pc0 {
  133. nvidia,pins = "uart3_rts_n_pc0";
  134. nvidia,function = "gmi";
  135. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  136. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  137. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  138. };
  139. uart2_txd_pc2 {
  140. nvidia,pins = "uart2_txd_pc2";
  141. nvidia,function = "irda";
  142. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  143. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  144. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  145. };
  146. uart2_rxd_pc3 {
  147. nvidia,pins = "uart2_rxd_pc3";
  148. nvidia,function = "irda";
  149. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  150. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  151. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  152. };
  153. gen1_i2c_scl_pc4 {
  154. nvidia,pins = "gen1_i2c_scl_pc4";
  155. nvidia,function = "i2c1";
  156. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  157. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  158. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  159. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  160. };
  161. gen1_i2c_sda_pc5 {
  162. nvidia,pins = "gen1_i2c_sda_pc5";
  163. nvidia,function = "i2c1";
  164. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  165. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  166. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  167. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  168. };
  169. pc7 {
  170. nvidia,pins = "pc7";
  171. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  172. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  173. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  174. };
  175. pg0 {
  176. nvidia,pins = "pg0";
  177. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  178. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  179. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  180. };
  181. pg1 {
  182. nvidia,pins = "pg1";
  183. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  184. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  185. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  186. };
  187. pg2 {
  188. nvidia,pins = "pg2";
  189. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  190. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  191. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  192. };
  193. pg3 {
  194. nvidia,pins = "pg3";
  195. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  196. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  197. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  198. };
  199. pg4 {
  200. nvidia,pins = "pg4";
  201. nvidia,function = "spi4";
  202. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  203. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  204. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  205. };
  206. pg5 {
  207. nvidia,pins = "pg5";
  208. nvidia,function = "spi4";
  209. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  210. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  211. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  212. };
  213. pg6 {
  214. nvidia,pins = "pg6";
  215. nvidia,function = "spi4";
  216. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  217. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  218. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  219. };
  220. pg7 {
  221. nvidia,pins = "pg7";
  222. nvidia,function = "spi4";
  223. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  224. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  225. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  226. };
  227. ph0 {
  228. nvidia,pins = "ph0";
  229. nvidia,function = "gmi";
  230. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  231. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  232. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  233. };
  234. ph1 {
  235. nvidia,pins = "ph1";
  236. nvidia,function = "pwm1";
  237. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  238. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  239. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  240. };
  241. ph2 {
  242. nvidia,pins = "ph2";
  243. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  244. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  245. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  246. };
  247. ph3 {
  248. nvidia,pins = "ph3";
  249. nvidia,function = "gmi";
  250. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  251. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  252. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  253. };
  254. ph4 {
  255. nvidia,pins = "ph4";
  256. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  257. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  258. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  259. };
  260. ph5 {
  261. nvidia,pins = "ph5";
  262. nvidia,function = "rsvd2";
  263. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  264. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  265. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  266. };
  267. ph6 {
  268. nvidia,pins = "ph6";
  269. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  270. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  271. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  272. };
  273. ph7 {
  274. nvidia,pins = "ph7";
  275. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  276. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  277. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  278. };
  279. pi0 {
  280. nvidia,pins = "pi0";
  281. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  282. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  283. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  284. };
  285. pi1 {
  286. nvidia,pins = "pi1";
  287. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  288. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  289. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  290. };
  291. pi2 {
  292. nvidia,pins = "pi2";
  293. nvidia,function = "rsvd4";
  294. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  295. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  296. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  297. };
  298. pi3 {
  299. nvidia,pins = "pi3";
  300. nvidia,function = "spi4";
  301. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  302. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  303. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  304. };
  305. pi4 {
  306. nvidia,pins = "pi4";
  307. nvidia,function = "gmi";
  308. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  309. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  310. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  311. };
  312. pi5 {
  313. nvidia,pins = "pi5";
  314. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  315. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  316. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  317. };
  318. pi6 {
  319. nvidia,pins = "pi6";
  320. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  321. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  322. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  323. };
  324. pi7 {
  325. nvidia,pins = "pi7";
  326. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  327. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  328. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  329. };
  330. pj0 {
  331. nvidia,pins = "pj0";
  332. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  333. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  334. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  335. };
  336. pj2 {
  337. nvidia,pins = "pj2";
  338. nvidia,function = "rsvd1";
  339. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  340. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  341. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  342. };
  343. uart2_cts_n_pj5 {
  344. nvidia,pins = "uart2_cts_n_pj5";
  345. nvidia,function = "gmi";
  346. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  347. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  348. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  349. };
  350. uart2_rts_n_pj6 {
  351. nvidia,pins = "uart2_rts_n_pj6";
  352. nvidia,function = "gmi";
  353. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  354. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  355. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  356. };
  357. pj7 {
  358. nvidia,pins = "pj7";
  359. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  360. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  361. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  362. };
  363. pk0 {
  364. nvidia,pins = "pk0";
  365. nvidia,function = "rsvd1";
  366. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  367. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  368. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  369. };
  370. pk1 {
  371. nvidia,pins = "pk1";
  372. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  373. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  374. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  375. };
  376. pk2 {
  377. nvidia,pins = "pk2";
  378. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  379. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  380. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  381. };
  382. pk3 {
  383. nvidia,pins = "pk3";
  384. nvidia,function = "gmi";
  385. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  386. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  387. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  388. };
  389. pk4 {
  390. nvidia,pins = "pk4";
  391. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  392. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  393. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  394. };
  395. spdif_out_pk5 {
  396. nvidia,pins = "spdif_out_pk5";
  397. nvidia,function = "rsvd2";
  398. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  399. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  400. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  401. };
  402. spdif_in_pk6 {
  403. nvidia,pins = "spdif_in_pk6";
  404. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  405. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  406. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  407. };
  408. pk7 {
  409. nvidia,pins = "pk7";
  410. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  411. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  412. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  413. };
  414. dap1_fs_pn0 {
  415. nvidia,pins = "dap1_fs_pn0";
  416. nvidia,function = "rsvd4";
  417. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  418. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  419. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  420. };
  421. dap1_din_pn1 {
  422. nvidia,pins = "dap1_din_pn1";
  423. nvidia,function = "rsvd4";
  424. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  425. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  426. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  427. };
  428. dap1_dout_pn2 {
  429. nvidia,pins = "dap1_dout_pn2";
  430. nvidia,function = "i2s0";
  431. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  432. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  433. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  434. };
  435. dap1_sclk_pn3 {
  436. nvidia,pins = "dap1_sclk_pn3";
  437. nvidia,function = "rsvd4";
  438. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  439. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  440. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  441. };
  442. usb_vbus_en0_pn4 {
  443. nvidia,pins = "usb_vbus_en0_pn4";
  444. nvidia,function = "usb";
  445. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  446. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  447. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  448. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  449. };
  450. usb_vbus_en1_pn5 {
  451. nvidia,pins = "usb_vbus_en1_pn5";
  452. nvidia,function = "usb";
  453. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  454. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  455. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  456. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  457. };
  458. hdmi_int_pn7 {
  459. nvidia,pins = "hdmi_int_pn7";
  460. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  461. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  462. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  463. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  464. };
  465. ulpi_data7_po0 {
  466. nvidia,pins = "ulpi_data7_po0";
  467. nvidia,function = "ulpi";
  468. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  469. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  470. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  471. };
  472. ulpi_data0_po1 {
  473. nvidia,pins = "ulpi_data0_po1";
  474. nvidia,function = "ulpi";
  475. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  476. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  477. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  478. };
  479. ulpi_data1_po2 {
  480. nvidia,pins = "ulpi_data1_po2";
  481. nvidia,function = "ulpi";
  482. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  483. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  484. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  485. };
  486. ulpi_data2_po3 {
  487. nvidia,pins = "ulpi_data2_po3";
  488. nvidia,function = "ulpi";
  489. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  490. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  491. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  492. };
  493. ulpi_data3_po4 {
  494. nvidia,pins = "ulpi_data3_po4";
  495. nvidia,function = "ulpi";
  496. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  497. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  498. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  499. };
  500. ulpi_data4_po5 {
  501. nvidia,pins = "ulpi_data4_po5";
  502. nvidia,function = "ulpi";
  503. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  504. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  505. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  506. };
  507. ulpi_data5_po6 {
  508. nvidia,pins = "ulpi_data5_po6";
  509. nvidia,function = "ulpi";
  510. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  511. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  512. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  513. };
  514. ulpi_data6_po7 {
  515. nvidia,pins = "ulpi_data6_po7";
  516. nvidia,function = "ulpi";
  517. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  518. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  519. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  520. };
  521. dap3_fs_pp0 {
  522. nvidia,pins = "dap3_fs_pp0";
  523. nvidia,function = "i2s2";
  524. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  525. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  526. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  527. };
  528. dap3_din_pp1 {
  529. nvidia,pins = "dap3_din_pp1";
  530. nvidia,function = "i2s2";
  531. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  532. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  533. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  534. };
  535. dap3_dout_pp2 {
  536. nvidia,pins = "dap3_dout_pp2";
  537. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  538. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  539. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  540. };
  541. dap3_sclk_pp3 {
  542. nvidia,pins = "dap3_sclk_pp3";
  543. nvidia,function = "rsvd3";
  544. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  545. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  546. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  547. };
  548. dap4_fs_pp4 {
  549. nvidia,pins = "dap4_fs_pp4";
  550. nvidia,function = "rsvd4";
  551. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  552. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  553. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  554. };
  555. dap4_din_pp5 {
  556. nvidia,pins = "dap4_din_pp5";
  557. nvidia,function = "rsvd3";
  558. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  559. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  560. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  561. };
  562. dap4_dout_pp6 {
  563. nvidia,pins = "dap4_dout_pp6";
  564. nvidia,function = "rsvd4";
  565. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  566. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  567. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  568. };
  569. dap4_sclk_pp7 {
  570. nvidia,pins = "dap4_sclk_pp7";
  571. nvidia,function = "rsvd3";
  572. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  573. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  574. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  575. };
  576. kb_col0_pq0 {
  577. nvidia,pins = "kb_col0_pq0";
  578. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  579. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  580. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  581. };
  582. kb_col1_pq1 {
  583. nvidia,pins = "kb_col1_pq1";
  584. nvidia,function = "rsvd2";
  585. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  586. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  587. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  588. };
  589. kb_col2_pq2 {
  590. nvidia,pins = "kb_col2_pq2";
  591. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  592. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  593. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  594. };
  595. kb_col3_pq3 {
  596. nvidia,pins = "kb_col3_pq3";
  597. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  598. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  599. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  600. };
  601. kb_col4_pq4 {
  602. nvidia,pins = "kb_col4_pq4";
  603. nvidia,function = "sdmmc3";
  604. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  605. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  606. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  607. };
  608. kb_col5_pq5 {
  609. nvidia,pins = "kb_col5_pq5";
  610. nvidia,function = "rsvd2";
  611. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  612. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  613. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  614. };
  615. kb_col6_pq6 {
  616. nvidia,pins = "kb_col6_pq6";
  617. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  618. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  619. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  620. };
  621. kb_col7_pq7 {
  622. nvidia,pins = "kb_col7_pq7";
  623. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  624. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  625. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  626. };
  627. kb_row0_pr0 {
  628. nvidia,pins = "kb_row0_pr0";
  629. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  630. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  631. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  632. };
  633. kb_row1_pr1 {
  634. nvidia,pins = "kb_row1_pr1";
  635. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  636. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  637. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  638. };
  639. kb_row2_pr2 {
  640. nvidia,pins = "kb_row2_pr2";
  641. nvidia,function = "rsvd2";
  642. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  643. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  644. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  645. };
  646. kb_row3_pr3 {
  647. nvidia,pins = "kb_row3_pr3";
  648. nvidia,function = "kbc";
  649. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  650. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  651. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  652. };
  653. kb_row4_pr4 {
  654. nvidia,pins = "kb_row4_pr4";
  655. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  656. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  657. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  658. };
  659. kb_row5_pr5 {
  660. nvidia,pins = "kb_row5_pr5";
  661. nvidia,function = "rsvd3";
  662. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  663. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  664. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  665. };
  666. kb_row6_pr6 {
  667. nvidia,pins = "kb_row6_pr6";
  668. nvidia,function = "kbc";
  669. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  670. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  671. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  672. };
  673. kb_row7_pr7 {
  674. nvidia,pins = "kb_row7_pr7";
  675. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  676. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  677. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  678. };
  679. kb_row8_ps0 {
  680. nvidia,pins = "kb_row8_ps0";
  681. nvidia,function = "rsvd2";
  682. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  683. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  684. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  685. };
  686. kb_row9_ps1 {
  687. nvidia,pins = "kb_row9_ps1";
  688. nvidia,function = "uarta";
  689. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  690. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  691. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  692. };
  693. kb_row10_ps2 {
  694. nvidia,pins = "kb_row10_ps2";
  695. nvidia,function = "uarta";
  696. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  697. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  698. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  699. };
  700. kb_row11_ps3 {
  701. nvidia,pins = "kb_row11_ps3";
  702. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  703. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  704. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  705. };
  706. kb_row12_ps4 {
  707. nvidia,pins = "kb_row12_ps4";
  708. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  709. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  710. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  711. };
  712. kb_row13_ps5 {
  713. nvidia,pins = "kb_row13_ps5";
  714. nvidia,function = "rsvd2";
  715. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  716. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  717. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  718. };
  719. kb_row14_ps6 {
  720. nvidia,pins = "kb_row14_ps6";
  721. nvidia,function = "rsvd2";
  722. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  723. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  724. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  725. };
  726. kb_row15_ps7 {
  727. nvidia,pins = "kb_row15_ps7";
  728. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  729. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  730. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  731. };
  732. kb_row16_pt0 {
  733. nvidia,pins = "kb_row16_pt0";
  734. nvidia,function = "rsvd2";
  735. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  736. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  737. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  738. };
  739. kb_row17_pt1 {
  740. nvidia,pins = "kb_row17_pt1";
  741. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  742. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  743. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  744. };
  745. gen2_i2c_scl_pt5 {
  746. nvidia,pins = "gen2_i2c_scl_pt5";
  747. nvidia,function = "i2c2";
  748. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  749. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  750. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  751. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  752. };
  753. gen2_i2c_sda_pt6 {
  754. nvidia,pins = "gen2_i2c_sda_pt6";
  755. nvidia,function = "i2c2";
  756. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  757. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  758. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  759. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  760. };
  761. sdmmc4_cmd_pt7 {
  762. nvidia,pins = "sdmmc4_cmd_pt7";
  763. nvidia,function = "sdmmc4";
  764. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  765. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  766. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  767. };
  768. pu0 {
  769. nvidia,pins = "pu0";
  770. nvidia,function = "rsvd4";
  771. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  772. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  773. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  774. };
  775. pu1 {
  776. nvidia,pins = "pu1";
  777. nvidia,function = "rsvd1";
  778. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  779. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  780. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  781. };
  782. pu2 {
  783. nvidia,pins = "pu2";
  784. nvidia,function = "rsvd1";
  785. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  786. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  787. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  788. };
  789. pu3 {
  790. nvidia,pins = "pu3";
  791. nvidia,function = "gmi";
  792. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  793. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  794. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  795. };
  796. pu4 {
  797. nvidia,pins = "pu4";
  798. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  799. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  800. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  801. };
  802. pu5 {
  803. nvidia,pins = "pu5";
  804. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  805. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  806. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  807. };
  808. pu6 {
  809. nvidia,pins = "pu6";
  810. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  811. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  812. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  813. };
  814. pv0 {
  815. nvidia,pins = "pv0";
  816. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  817. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  818. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  819. };
  820. pv1 {
  821. nvidia,pins = "pv1";
  822. nvidia,function = "rsvd1";
  823. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  824. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  825. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  826. };
  827. sdmmc3_cd_n_pv2 {
  828. nvidia,pins = "sdmmc3_cd_n_pv2";
  829. nvidia,function = "sdmmc3";
  830. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  831. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  832. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  833. };
  834. sdmmc1_wp_n_pv3 {
  835. nvidia,pins = "sdmmc1_wp_n_pv3";
  836. nvidia,function = "sdmmc1";
  837. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  838. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  839. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  840. };
  841. ddc_scl_pv4 {
  842. nvidia,pins = "ddc_scl_pv4";
  843. nvidia,function = "i2c4";
  844. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  845. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  846. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  847. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  848. };
  849. ddc_sda_pv5 {
  850. nvidia,pins = "ddc_sda_pv5";
  851. nvidia,function = "i2c4";
  852. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  853. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  854. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  855. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  856. };
  857. gpio_w2_aud_pw2 {
  858. nvidia,pins = "gpio_w2_aud_pw2";
  859. nvidia,function = "rsvd2";
  860. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  861. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  862. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  863. };
  864. gpio_w3_aud_pw3 {
  865. nvidia,pins = "gpio_w3_aud_pw3";
  866. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  867. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  868. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  869. };
  870. dap_mclk1_pw4 {
  871. nvidia,pins = "dap_mclk1_pw4";
  872. nvidia,function = "extperiph1";
  873. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  874. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  875. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  876. };
  877. clk2_out_pw5 {
  878. nvidia,pins = "clk2_out_pw5";
  879. nvidia,function = "rsvd2";
  880. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  881. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  882. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  883. };
  884. uart3_txd_pw6 {
  885. nvidia,pins = "uart3_txd_pw6";
  886. nvidia,function = "rsvd2";
  887. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  888. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  889. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  890. };
  891. uart3_rxd_pw7 {
  892. nvidia,pins = "uart3_rxd_pw7";
  893. nvidia,function = "rsvd2";
  894. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  895. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  896. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  897. };
  898. dvfs_pwm_px0 {
  899. nvidia,pins = "dvfs_pwm_px0";
  900. nvidia,function = "cldvfs";
  901. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  902. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  903. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  904. };
  905. gpio_x1_aud_px1 {
  906. nvidia,pins = "gpio_x1_aud_px1";
  907. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  908. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  909. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  910. };
  911. dvfs_clk_px2 {
  912. nvidia,pins = "dvfs_clk_px2";
  913. nvidia,function = "cldvfs";
  914. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  915. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  916. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  917. };
  918. gpio_x3_aud_px3 {
  919. nvidia,pins = "gpio_x3_aud_px3";
  920. nvidia,function = "rsvd4";
  921. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  922. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  923. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  924. };
  925. gpio_x4_aud_px4 {
  926. nvidia,pins = "gpio_x4_aud_px4";
  927. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  928. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  929. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  930. };
  931. gpio_x5_aud_px5 {
  932. nvidia,pins = "gpio_x5_aud_px5";
  933. nvidia,function = "rsvd4";
  934. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  935. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  936. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  937. };
  938. gpio_x6_aud_px6 {
  939. nvidia,pins = "gpio_x6_aud_px6";
  940. nvidia,function = "gmi";
  941. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  942. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  943. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  944. };
  945. gpio_x7_aud_px7 {
  946. nvidia,pins = "gpio_x7_aud_px7";
  947. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  948. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  949. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  950. };
  951. ulpi_clk_py0 {
  952. nvidia,pins = "ulpi_clk_py0";
  953. nvidia,function = "spi1";
  954. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  955. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  956. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  957. };
  958. ulpi_dir_py1 {
  959. nvidia,pins = "ulpi_dir_py1";
  960. nvidia,function = "spi1";
  961. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  962. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  963. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  964. };
  965. ulpi_nxt_py2 {
  966. nvidia,pins = "ulpi_nxt_py2";
  967. nvidia,function = "spi1";
  968. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  969. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  970. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  971. };
  972. ulpi_stp_py3 {
  973. nvidia,pins = "ulpi_stp_py3";
  974. nvidia,function = "spi1";
  975. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  976. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  977. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  978. };
  979. sdmmc1_dat3_py4 {
  980. nvidia,pins = "sdmmc1_dat3_py4";
  981. nvidia,function = "sdmmc1";
  982. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  983. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  984. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  985. };
  986. sdmmc1_dat2_py5 {
  987. nvidia,pins = "sdmmc1_dat2_py5";
  988. nvidia,function = "sdmmc1";
  989. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  990. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  991. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  992. };
  993. sdmmc1_dat1_py6 {
  994. nvidia,pins = "sdmmc1_dat1_py6";
  995. nvidia,function = "sdmmc1";
  996. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  997. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  998. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  999. };
  1000. sdmmc1_dat0_py7 {
  1001. nvidia,pins = "sdmmc1_dat0_py7";
  1002. nvidia,function = "sdmmc1";
  1003. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1004. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1005. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1006. };
  1007. sdmmc1_clk_pz0 {
  1008. nvidia,pins = "sdmmc1_clk_pz0";
  1009. nvidia,function = "sdmmc1";
  1010. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1011. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1012. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1013. };
  1014. sdmmc1_cmd_pz1 {
  1015. nvidia,pins = "sdmmc1_cmd_pz1";
  1016. nvidia,function = "sdmmc1";
  1017. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1018. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1019. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1020. };
  1021. pwr_i2c_scl_pz6 {
  1022. nvidia,pins = "pwr_i2c_scl_pz6";
  1023. nvidia,function = "i2cpwr";
  1024. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1025. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1026. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1027. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1028. };
  1029. pwr_i2c_sda_pz7 {
  1030. nvidia,pins = "pwr_i2c_sda_pz7";
  1031. nvidia,function = "i2cpwr";
  1032. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1033. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1034. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1035. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1036. };
  1037. sdmmc4_dat0_paa0 {
  1038. nvidia,pins = "sdmmc4_dat0_paa0";
  1039. nvidia,function = "sdmmc4";
  1040. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1041. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1042. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1043. };
  1044. sdmmc4_dat1_paa1 {
  1045. nvidia,pins = "sdmmc4_dat1_paa1";
  1046. nvidia,function = "sdmmc4";
  1047. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1048. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1049. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1050. };
  1051. sdmmc4_dat2_paa2 {
  1052. nvidia,pins = "sdmmc4_dat2_paa2";
  1053. nvidia,function = "sdmmc4";
  1054. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1055. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1056. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1057. };
  1058. sdmmc4_dat3_paa3 {
  1059. nvidia,pins = "sdmmc4_dat3_paa3";
  1060. nvidia,function = "sdmmc4";
  1061. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1062. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1063. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1064. };
  1065. sdmmc4_dat4_paa4 {
  1066. nvidia,pins = "sdmmc4_dat4_paa4";
  1067. nvidia,function = "sdmmc4";
  1068. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1069. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1070. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1071. };
  1072. sdmmc4_dat5_paa5 {
  1073. nvidia,pins = "sdmmc4_dat5_paa5";
  1074. nvidia,function = "sdmmc4";
  1075. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1076. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1077. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1078. };
  1079. sdmmc4_dat6_paa6 {
  1080. nvidia,pins = "sdmmc4_dat6_paa6";
  1081. nvidia,function = "sdmmc4";
  1082. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1083. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1084. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1085. };
  1086. sdmmc4_dat7_paa7 {
  1087. nvidia,pins = "sdmmc4_dat7_paa7";
  1088. nvidia,function = "sdmmc4";
  1089. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1090. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1091. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1092. };
  1093. pbb0 {
  1094. nvidia,pins = "pbb0";
  1095. nvidia,function = "vgp6";
  1096. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1097. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1098. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1099. };
  1100. cam_i2c_scl_pbb1 {
  1101. nvidia,pins = "cam_i2c_scl_pbb1";
  1102. nvidia,function = "i2c3";
  1103. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1104. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1105. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1106. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1107. };
  1108. cam_i2c_sda_pbb2 {
  1109. nvidia,pins = "cam_i2c_sda_pbb2";
  1110. nvidia,function = "i2c3";
  1111. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1112. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1113. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1114. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1115. };
  1116. pbb3 {
  1117. nvidia,pins = "pbb3";
  1118. nvidia,function = "vgp3";
  1119. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1120. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1121. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1122. };
  1123. pbb4 {
  1124. nvidia,pins = "pbb4";
  1125. nvidia,function = "vgp4";
  1126. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1127. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1128. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1129. };
  1130. pbb5 {
  1131. nvidia,pins = "pbb5";
  1132. nvidia,function = "rsvd3";
  1133. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1134. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1135. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1136. };
  1137. pbb6 {
  1138. nvidia,pins = "pbb6";
  1139. nvidia,function = "rsvd2";
  1140. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1141. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1142. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1143. };
  1144. pbb7 {
  1145. nvidia,pins = "pbb7";
  1146. nvidia,function = "rsvd2";
  1147. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1148. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1149. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1150. };
  1151. cam_mclk_pcc0 {
  1152. nvidia,pins = "cam_mclk_pcc0";
  1153. nvidia,function = "vi";
  1154. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1155. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1156. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1157. };
  1158. pcc1 {
  1159. nvidia,pins = "pcc1";
  1160. nvidia,function = "rsvd2";
  1161. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1162. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1163. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1164. };
  1165. pcc2 {
  1166. nvidia,pins = "pcc2";
  1167. nvidia,function = "rsvd2";
  1168. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1169. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1170. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1171. };
  1172. sdmmc4_clk_pcc4 {
  1173. nvidia,pins = "sdmmc4_clk_pcc4";
  1174. nvidia,function = "sdmmc4";
  1175. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1176. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1177. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1178. };
  1179. clk2_req_pcc5 {
  1180. nvidia,pins = "clk2_req_pcc5";
  1181. nvidia,function = "rsvd2";
  1182. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1183. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1184. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1185. };
  1186. pex_l0_rst_n_pdd1 {
  1187. nvidia,pins = "pex_l0_rst_n_pdd1";
  1188. nvidia,function = "rsvd2";
  1189. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1190. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1191. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1192. };
  1193. pex_l0_clkreq_n_pdd2 {
  1194. nvidia,pins = "pex_l0_clkreq_n_pdd2";
  1195. nvidia,function = "rsvd2";
  1196. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1197. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1198. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1199. };
  1200. pex_wake_n_pdd3 {
  1201. nvidia,pins = "pex_wake_n_pdd3";
  1202. nvidia,function = "rsvd2";
  1203. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1204. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1205. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1206. };
  1207. pex_l1_rst_n_pdd5 {
  1208. nvidia,pins = "pex_l1_rst_n_pdd5";
  1209. nvidia,function = "rsvd2";
  1210. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1211. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1212. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1213. };
  1214. pex_l1_clkreq_n_pdd6 {
  1215. nvidia,pins = "pex_l1_clkreq_n_pdd6";
  1216. nvidia,function = "rsvd2";
  1217. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1218. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1219. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1220. };
  1221. clk3_out_pee0 {
  1222. nvidia,pins = "clk3_out_pee0";
  1223. nvidia,function = "rsvd2";
  1224. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1225. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1226. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1227. };
  1228. clk3_req_pee1 {
  1229. nvidia,pins = "clk3_req_pee1";
  1230. nvidia,function = "rsvd2";
  1231. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1232. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1233. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1234. };
  1235. dap_mclk1_req_pee2 {
  1236. nvidia,pins = "dap_mclk1_req_pee2";
  1237. nvidia,function = "rsvd4";
  1238. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1239. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1240. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1241. };
  1242. hdmi_cec_pee3 {
  1243. nvidia,pins = "hdmi_cec_pee3";
  1244. nvidia,function = "cec";
  1245. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1246. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1247. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1248. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1249. };
  1250. sdmmc3_clk_lb_out_pee4 {
  1251. nvidia,pins = "sdmmc3_clk_lb_out_pee4";
  1252. nvidia,function = "sdmmc3";
  1253. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1254. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1255. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1256. };
  1257. sdmmc3_clk_lb_in_pee5 {
  1258. nvidia,pins = "sdmmc3_clk_lb_in_pee5";
  1259. nvidia,function = "sdmmc3";
  1260. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1261. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1262. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1263. };
  1264. dp_hpd_pff0 {
  1265. nvidia,pins = "dp_hpd_pff0";
  1266. nvidia,function = "dp";
  1267. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1268. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1269. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1270. };
  1271. usb_vbus_en2_pff1 {
  1272. nvidia,pins = "usb_vbus_en2_pff1";
  1273. nvidia,function = "rsvd2";
  1274. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1275. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1276. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1277. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1278. };
  1279. pff2 {
  1280. nvidia,pins = "pff2";
  1281. nvidia,function = "rsvd2";
  1282. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1283. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1284. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1285. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1286. };
  1287. core_pwr_req {
  1288. nvidia,pins = "core_pwr_req";
  1289. nvidia,function = "pwron";
  1290. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1291. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1292. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1293. };
  1294. cpu_pwr_req {
  1295. nvidia,pins = "cpu_pwr_req";
  1296. nvidia,function = "cpu";
  1297. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1298. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1299. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1300. };
  1301. pwr_int_n {
  1302. nvidia,pins = "pwr_int_n";
  1303. nvidia,function = "pmi";
  1304. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1305. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1306. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1307. };
  1308. reset_out_n {
  1309. nvidia,pins = "reset_out_n";
  1310. nvidia,function = "reset_out_n";
  1311. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1312. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1313. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1314. };
  1315. owr {
  1316. nvidia,pins = "owr";
  1317. nvidia,function = "rsvd2";
  1318. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1319. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1320. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1321. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  1322. };
  1323. clk_32k_in {
  1324. nvidia,pins = "clk_32k_in";
  1325. nvidia,function = "clk";
  1326. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1327. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1328. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1329. };
  1330. jtag_rtck {
  1331. nvidia,pins = "jtag_rtck";
  1332. nvidia,function = "rtck";
  1333. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1334. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1335. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1336. };
  1337. };
  1338. };
  1339. };