tegra124-jetson-tk1.dts 56 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include <dt-bindings/input/input.h>
  4. #include "tegra124.dtsi"
  5. #include "tegra124-jetson-tk1-emc.dtsi"
  6. / {
  7. model = "NVIDIA Tegra124 Jetson TK1";
  8. compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
  9. aliases {
  10. rtc0 = "/i2c@7000d000/pmic@40";
  11. rtc1 = "/rtc@7000e000";
  12. /* This order keeps the mapping DB9 connector <-> ttyS0 */
  13. serial0 = &uartd;
  14. serial1 = &uarta;
  15. serial2 = &uartb;
  16. };
  17. chosen {
  18. stdout-path = "serial0:115200n8";
  19. };
  20. memory@80000000 {
  21. reg = <0x0 0x80000000 0x0 0x80000000>;
  22. };
  23. pcie@1003000 {
  24. status = "okay";
  25. avddio-pex-supply = <&vdd_1v05_run>;
  26. dvddio-pex-supply = <&vdd_1v05_run>;
  27. avdd-pex-pll-supply = <&vdd_1v05_run>;
  28. hvdd-pex-supply = <&vdd_3v3_lp0>;
  29. hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
  30. vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
  31. avdd-pll-erefe-supply = <&avdd_1v05_run>;
  32. /* Mini PCIe */
  33. pci@1,0 {
  34. phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
  35. phy-names = "pcie-0";
  36. status = "okay";
  37. };
  38. /* Gigabit Ethernet */
  39. pci@2,0 {
  40. phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
  41. phy-names = "pcie-0";
  42. status = "okay";
  43. };
  44. };
  45. host1x@50000000 {
  46. hdmi@54280000 {
  47. status = "okay";
  48. hdmi-supply = <&vdd_5v0_hdmi>;
  49. pll-supply = <&vdd_hdmi_pll>;
  50. vdd-supply = <&vdd_3v3_hdmi>;
  51. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  52. nvidia,hpd-gpio =
  53. <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  54. };
  55. };
  56. cec@70015000 {
  57. status = "okay";
  58. };
  59. gpu@57000000 {
  60. /*
  61. * Node left disabled on purpose - the bootloader will enable
  62. * it after having set the VPR up
  63. */
  64. vdd-supply = <&vdd_gpu>;
  65. };
  66. pinmux: pinmux@70000868 {
  67. pinctrl-names = "boot";
  68. pinctrl-0 = <&state_boot>;
  69. state_boot: pinmux {
  70. clk_32k_out_pa0 {
  71. nvidia,pins = "clk_32k_out_pa0";
  72. nvidia,function = "soc";
  73. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  74. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  75. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  76. };
  77. uart3_cts_n_pa1 {
  78. nvidia,pins = "uart3_cts_n_pa1";
  79. nvidia,function = "gmi";
  80. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  81. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  82. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  83. };
  84. dap2_fs_pa2 {
  85. nvidia,pins = "dap2_fs_pa2";
  86. nvidia,function = "i2s1";
  87. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  88. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  89. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  90. };
  91. dap2_sclk_pa3 {
  92. nvidia,pins = "dap2_sclk_pa3";
  93. nvidia,function = "i2s1";
  94. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  95. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  96. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  97. };
  98. dap2_din_pa4 {
  99. nvidia,pins = "dap2_din_pa4";
  100. nvidia,function = "i2s1";
  101. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  102. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  103. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  104. };
  105. dap2_dout_pa5 {
  106. nvidia,pins = "dap2_dout_pa5";
  107. nvidia,function = "i2s1";
  108. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  109. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  110. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  111. };
  112. sdmmc3_clk_pa6 {
  113. nvidia,pins = "sdmmc3_clk_pa6";
  114. nvidia,function = "sdmmc3";
  115. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  116. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  117. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  118. };
  119. sdmmc3_cmd_pa7 {
  120. nvidia,pins = "sdmmc3_cmd_pa7";
  121. nvidia,function = "sdmmc3";
  122. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  123. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  124. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  125. };
  126. pb0 {
  127. nvidia,pins = "pb0";
  128. nvidia,function = "uartd";
  129. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  130. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  131. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  132. };
  133. pb1 {
  134. nvidia,pins = "pb1";
  135. nvidia,function = "uartd";
  136. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  137. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  138. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  139. };
  140. sdmmc3_dat3_pb4 {
  141. nvidia,pins = "sdmmc3_dat3_pb4";
  142. nvidia,function = "sdmmc3";
  143. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  144. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  145. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  146. };
  147. sdmmc3_dat2_pb5 {
  148. nvidia,pins = "sdmmc3_dat2_pb5";
  149. nvidia,function = "sdmmc3";
  150. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  151. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  152. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  153. };
  154. sdmmc3_dat1_pb6 {
  155. nvidia,pins = "sdmmc3_dat1_pb6";
  156. nvidia,function = "sdmmc3";
  157. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  158. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  159. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  160. };
  161. sdmmc3_dat0_pb7 {
  162. nvidia,pins = "sdmmc3_dat0_pb7";
  163. nvidia,function = "sdmmc3";
  164. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  165. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  166. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  167. };
  168. uart3_rts_n_pc0 {
  169. nvidia,pins = "uart3_rts_n_pc0";
  170. nvidia,function = "gmi";
  171. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  172. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  173. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  174. };
  175. uart2_txd_pc2 {
  176. nvidia,pins = "uart2_txd_pc2";
  177. nvidia,function = "irda";
  178. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  179. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  180. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  181. };
  182. uart2_rxd_pc3 {
  183. nvidia,pins = "uart2_rxd_pc3";
  184. nvidia,function = "irda";
  185. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  186. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  187. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  188. };
  189. gen1_i2c_scl_pc4 {
  190. nvidia,pins = "gen1_i2c_scl_pc4";
  191. nvidia,function = "i2c1";
  192. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  193. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  194. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  195. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  196. };
  197. gen1_i2c_sda_pc5 {
  198. nvidia,pins = "gen1_i2c_sda_pc5";
  199. nvidia,function = "i2c1";
  200. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  201. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  202. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  203. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  204. };
  205. pc7 {
  206. nvidia,pins = "pc7";
  207. nvidia,function = "rsvd1";
  208. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  209. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  210. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  211. };
  212. pg0 {
  213. nvidia,pins = "pg0";
  214. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  215. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  216. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  217. };
  218. pg1 {
  219. nvidia,pins = "pg1";
  220. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  221. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  222. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  223. };
  224. pg2 {
  225. nvidia,pins = "pg2";
  226. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  227. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  228. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  229. };
  230. pg3 {
  231. nvidia,pins = "pg3";
  232. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  233. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  234. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  235. };
  236. pg4 {
  237. nvidia,pins = "pg4";
  238. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  239. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  240. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  241. };
  242. pg5 {
  243. nvidia,pins = "pg5";
  244. nvidia,function = "spi4";
  245. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  246. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  247. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  248. };
  249. pg6 {
  250. nvidia,pins = "pg6";
  251. nvidia,function = "spi4";
  252. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  253. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  254. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  255. };
  256. pg7 {
  257. nvidia,pins = "pg7";
  258. nvidia,function = "spi4";
  259. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  260. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  261. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  262. };
  263. ph0 {
  264. nvidia,pins = "ph0";
  265. nvidia,function = "gmi";
  266. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  267. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  268. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  269. };
  270. ph1 {
  271. nvidia,pins = "ph1";
  272. nvidia,function = "pwm1";
  273. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  274. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  275. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  276. };
  277. ph2 {
  278. nvidia,pins = "ph2";
  279. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  280. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  281. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  282. };
  283. ph3 {
  284. nvidia,pins = "ph3";
  285. nvidia,function = "gmi";
  286. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  287. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  288. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  289. };
  290. ph4 {
  291. nvidia,pins = "ph4";
  292. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  293. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  294. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  295. };
  296. ph5 {
  297. nvidia,pins = "ph5";
  298. nvidia,function = "rsvd2";
  299. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  300. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  301. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  302. };
  303. ph6 {
  304. nvidia,pins = "ph6";
  305. nvidia,function = "gmi";
  306. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  307. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  308. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  309. };
  310. ph7 {
  311. nvidia,pins = "ph7";
  312. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  313. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  314. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  315. };
  316. pi0 {
  317. nvidia,pins = "pi0";
  318. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  319. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  320. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  321. };
  322. pi1 {
  323. nvidia,pins = "pi1";
  324. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  325. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  326. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  327. };
  328. pi2 {
  329. nvidia,pins = "pi2";
  330. nvidia,function = "rsvd4";
  331. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  332. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  333. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  334. };
  335. pi3 {
  336. nvidia,pins = "pi3";
  337. nvidia,function = "spi4";
  338. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  339. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  340. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  341. };
  342. pi4 {
  343. nvidia,pins = "pi4";
  344. nvidia,function = "gmi";
  345. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  346. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  347. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  348. };
  349. pi5 {
  350. nvidia,pins = "pi5";
  351. nvidia,function = "rsvd2";
  352. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  353. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  354. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  355. };
  356. pi6 {
  357. nvidia,pins = "pi6";
  358. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  359. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  360. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  361. };
  362. pi7 {
  363. nvidia,pins = "pi7";
  364. nvidia,function = "rsvd1";
  365. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  366. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  367. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  368. };
  369. pj0 {
  370. nvidia,pins = "pj0";
  371. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  372. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  373. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  374. };
  375. pj2 {
  376. nvidia,pins = "pj2";
  377. nvidia,function = "rsvd1";
  378. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  379. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  380. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  381. };
  382. uart2_cts_n_pj5 {
  383. nvidia,pins = "uart2_cts_n_pj5";
  384. nvidia,function = "uartb";
  385. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  386. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  387. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  388. };
  389. uart2_rts_n_pj6 {
  390. nvidia,pins = "uart2_rts_n_pj6";
  391. nvidia,function = "uartb";
  392. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  393. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  394. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  395. };
  396. pj7 {
  397. nvidia,pins = "pj7";
  398. nvidia,function = "uartd";
  399. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  400. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  401. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  402. };
  403. pk0 {
  404. nvidia,pins = "pk0";
  405. nvidia,function = "rsvd1";
  406. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  407. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  408. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  409. };
  410. pk1 {
  411. nvidia,pins = "pk1";
  412. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  413. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  414. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  415. };
  416. pk2 {
  417. nvidia,pins = "pk2";
  418. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  419. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  420. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  421. };
  422. pk3 {
  423. nvidia,pins = "pk3";
  424. nvidia,function = "gmi";
  425. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  426. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  427. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  428. };
  429. pk4 {
  430. nvidia,pins = "pk4";
  431. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  432. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  433. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  434. };
  435. spdif_out_pk5 {
  436. nvidia,pins = "spdif_out_pk5";
  437. nvidia,function = "rsvd2";
  438. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  439. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  440. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  441. };
  442. spdif_in_pk6 {
  443. nvidia,pins = "spdif_in_pk6";
  444. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  445. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  446. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  447. };
  448. pk7 {
  449. nvidia,pins = "pk7";
  450. nvidia,function = "uartd";
  451. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  452. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  453. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  454. };
  455. dap1_fs_pn0 {
  456. nvidia,pins = "dap1_fs_pn0";
  457. nvidia,function = "rsvd4";
  458. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  459. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  460. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  461. };
  462. dap1_din_pn1 {
  463. nvidia,pins = "dap1_din_pn1";
  464. nvidia,function = "rsvd4";
  465. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  466. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  467. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  468. };
  469. dap1_dout_pn2 {
  470. nvidia,pins = "dap1_dout_pn2";
  471. nvidia,function = "sata";
  472. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  473. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  474. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  475. };
  476. dap1_sclk_pn3 {
  477. nvidia,pins = "dap1_sclk_pn3";
  478. nvidia,function = "rsvd4";
  479. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  480. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  481. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  482. };
  483. usb_vbus_en0_pn4 {
  484. nvidia,pins = "usb_vbus_en0_pn4";
  485. nvidia,function = "usb";
  486. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  487. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  488. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  489. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  490. };
  491. usb_vbus_en1_pn5 {
  492. nvidia,pins = "usb_vbus_en1_pn5";
  493. nvidia,function = "usb";
  494. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  495. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  496. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  497. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  498. };
  499. hdmi_int_pn7 {
  500. nvidia,pins = "hdmi_int_pn7";
  501. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  502. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  503. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  504. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  505. };
  506. ulpi_data7_po0 {
  507. nvidia,pins = "ulpi_data7_po0";
  508. nvidia,function = "ulpi";
  509. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  510. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  511. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  512. };
  513. ulpi_data0_po1 {
  514. nvidia,pins = "ulpi_data0_po1";
  515. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  516. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  517. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  518. };
  519. ulpi_data1_po2 {
  520. nvidia,pins = "ulpi_data1_po2";
  521. nvidia,function = "ulpi";
  522. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  523. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  524. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  525. };
  526. ulpi_data2_po3 {
  527. nvidia,pins = "ulpi_data2_po3";
  528. nvidia,function = "ulpi";
  529. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  530. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  531. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  532. };
  533. ulpi_data3_po4 {
  534. nvidia,pins = "ulpi_data3_po4";
  535. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  536. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  537. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  538. };
  539. ulpi_data4_po5 {
  540. nvidia,pins = "ulpi_data4_po5";
  541. nvidia,function = "ulpi";
  542. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  543. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  544. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  545. };
  546. ulpi_data5_po6 {
  547. nvidia,pins = "ulpi_data5_po6";
  548. nvidia,function = "ulpi";
  549. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  550. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  551. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  552. };
  553. ulpi_data6_po7 {
  554. nvidia,pins = "ulpi_data6_po7";
  555. nvidia,function = "ulpi";
  556. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  557. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  558. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  559. };
  560. dap3_fs_pp0 {
  561. nvidia,pins = "dap3_fs_pp0";
  562. nvidia,function = "i2s2";
  563. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  564. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  565. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  566. };
  567. dap3_din_pp1 {
  568. nvidia,pins = "dap3_din_pp1";
  569. nvidia,function = "i2s2";
  570. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  571. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  572. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  573. };
  574. dap3_dout_pp2 {
  575. nvidia,pins = "dap3_dout_pp2";
  576. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  577. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  578. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  579. };
  580. dap3_sclk_pp3 {
  581. nvidia,pins = "dap3_sclk_pp3";
  582. nvidia,function = "rsvd3";
  583. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  584. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  585. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  586. };
  587. dap4_fs_pp4 {
  588. nvidia,pins = "dap4_fs_pp4";
  589. nvidia,function = "rsvd4";
  590. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  591. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  592. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  593. };
  594. dap4_din_pp5 {
  595. nvidia,pins = "dap4_din_pp5";
  596. nvidia,function = "rsvd3";
  597. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  598. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  599. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  600. };
  601. dap4_dout_pp6 {
  602. nvidia,pins = "dap4_dout_pp6";
  603. nvidia,function = "rsvd4";
  604. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  605. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  606. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  607. };
  608. dap4_sclk_pp7 {
  609. nvidia,pins = "dap4_sclk_pp7";
  610. nvidia,function = "rsvd3";
  611. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  612. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  613. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  614. };
  615. kb_col0_pq0 {
  616. nvidia,pins = "kb_col0_pq0";
  617. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  618. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  619. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  620. };
  621. kb_col1_pq1 {
  622. nvidia,pins = "kb_col1_pq1";
  623. nvidia,function = "rsvd2";
  624. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  625. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  626. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  627. };
  628. kb_col2_pq2 {
  629. nvidia,pins = "kb_col2_pq2";
  630. nvidia,function = "rsvd2";
  631. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  632. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  633. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  634. };
  635. kb_col3_pq3 {
  636. nvidia,pins = "kb_col3_pq3";
  637. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  638. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  639. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  640. };
  641. kb_col4_pq4 {
  642. nvidia,pins = "kb_col4_pq4";
  643. nvidia,function = "sdmmc3";
  644. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  645. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  646. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  647. };
  648. kb_col5_pq5 {
  649. nvidia,pins = "kb_col5_pq5";
  650. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  651. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  652. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  653. };
  654. kb_col6_pq6 {
  655. nvidia,pins = "kb_col6_pq6";
  656. nvidia,function = "rsvd2";
  657. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  658. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  659. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  660. };
  661. kb_col7_pq7 {
  662. nvidia,pins = "kb_col7_pq7";
  663. nvidia,function = "rsvd2";
  664. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  665. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  666. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  667. };
  668. kb_row0_pr0 {
  669. nvidia,pins = "kb_row0_pr0";
  670. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  671. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  672. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  673. };
  674. kb_row1_pr1 {
  675. nvidia,pins = "kb_row1_pr1";
  676. nvidia,function = "rsvd2";
  677. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  678. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  679. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  680. };
  681. kb_row2_pr2 {
  682. nvidia,pins = "kb_row2_pr2";
  683. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  684. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  685. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  686. };
  687. kb_row3_pr3 {
  688. nvidia,pins = "kb_row3_pr3";
  689. nvidia,function = "kbc";
  690. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  691. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  692. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  693. };
  694. kb_row4_pr4 {
  695. nvidia,pins = "kb_row4_pr4";
  696. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  697. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  698. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  699. };
  700. kb_row5_pr5 {
  701. nvidia,pins = "kb_row5_pr5";
  702. nvidia,function = "rsvd3";
  703. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  704. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  705. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  706. };
  707. kb_row6_pr6 {
  708. nvidia,pins = "kb_row6_pr6";
  709. nvidia,function = "displaya_alt";
  710. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  711. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  712. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  713. };
  714. kb_row7_pr7 {
  715. nvidia,pins = "kb_row7_pr7";
  716. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  717. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  718. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  719. };
  720. kb_row8_ps0 {
  721. nvidia,pins = "kb_row8_ps0";
  722. nvidia,function = "rsvd2";
  723. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  724. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  725. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  726. };
  727. kb_row9_ps1 {
  728. nvidia,pins = "kb_row9_ps1";
  729. nvidia,function = "uarta";
  730. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  731. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  732. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  733. };
  734. kb_row10_ps2 {
  735. nvidia,pins = "kb_row10_ps2";
  736. nvidia,function = "uarta";
  737. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  738. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  739. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  740. };
  741. kb_row11_ps3 {
  742. nvidia,pins = "kb_row11_ps3";
  743. nvidia,function = "rsvd2";
  744. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  745. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  746. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  747. };
  748. kb_row12_ps4 {
  749. nvidia,pins = "kb_row12_ps4";
  750. nvidia,function = "rsvd2";
  751. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  752. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  753. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  754. };
  755. kb_row13_ps5 {
  756. nvidia,pins = "kb_row13_ps5";
  757. nvidia,function = "rsvd2";
  758. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  759. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  760. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  761. };
  762. kb_row14_ps6 {
  763. nvidia,pins = "kb_row14_ps6";
  764. nvidia,function = "rsvd2";
  765. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  766. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  767. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  768. };
  769. kb_row15_ps7 {
  770. nvidia,pins = "kb_row15_ps7";
  771. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  772. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  773. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  774. };
  775. kb_row16_pt0 {
  776. nvidia,pins = "kb_row16_pt0";
  777. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  778. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  779. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  780. };
  781. kb_row17_pt1 {
  782. nvidia,pins = "kb_row17_pt1";
  783. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  784. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  785. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  786. };
  787. gen2_i2c_scl_pt5 {
  788. nvidia,pins = "gen2_i2c_scl_pt5";
  789. nvidia,function = "i2c2";
  790. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  791. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  792. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  793. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  794. };
  795. gen2_i2c_sda_pt6 {
  796. nvidia,pins = "gen2_i2c_sda_pt6";
  797. nvidia,function = "i2c2";
  798. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  799. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  800. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  801. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  802. };
  803. sdmmc4_cmd_pt7 {
  804. nvidia,pins = "sdmmc4_cmd_pt7";
  805. nvidia,function = "sdmmc4";
  806. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  807. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  808. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  809. };
  810. pu0 {
  811. nvidia,pins = "pu0";
  812. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  813. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  814. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  815. };
  816. pu1 {
  817. nvidia,pins = "pu1";
  818. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  819. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  820. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  821. };
  822. pu2 {
  823. nvidia,pins = "pu2";
  824. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  825. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  826. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  827. };
  828. pu3 {
  829. nvidia,pins = "pu3";
  830. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  831. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  832. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  833. };
  834. pu4 {
  835. nvidia,pins = "pu4";
  836. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  837. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  838. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  839. };
  840. pu5 {
  841. nvidia,pins = "pu5";
  842. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  843. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  844. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  845. };
  846. pu6 {
  847. nvidia,pins = "pu6";
  848. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  849. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  850. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  851. };
  852. pv0 {
  853. nvidia,pins = "pv0";
  854. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  855. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  856. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  857. };
  858. pv1 {
  859. nvidia,pins = "pv1";
  860. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  861. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  862. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  863. };
  864. sdmmc3_cd_n_pv2 {
  865. nvidia,pins = "sdmmc3_cd_n_pv2";
  866. nvidia,function = "sdmmc3";
  867. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  868. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  869. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  870. };
  871. sdmmc1_wp_n_pv3 {
  872. nvidia,pins = "sdmmc1_wp_n_pv3";
  873. nvidia,function = "sdmmc1";
  874. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  875. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  876. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  877. };
  878. ddc_scl_pv4 {
  879. nvidia,pins = "ddc_scl_pv4";
  880. nvidia,function = "i2c4";
  881. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  882. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  883. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  884. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  885. };
  886. ddc_sda_pv5 {
  887. nvidia,pins = "ddc_sda_pv5";
  888. nvidia,function = "i2c4";
  889. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  890. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  891. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  892. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  893. };
  894. gpio_w2_aud_pw2 {
  895. nvidia,pins = "gpio_w2_aud_pw2";
  896. nvidia,function = "rsvd2";
  897. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  898. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  899. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  900. };
  901. gpio_w3_aud_pw3 {
  902. nvidia,pins = "gpio_w3_aud_pw3";
  903. nvidia,function = "spi6";
  904. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  905. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  906. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  907. };
  908. dap_mclk1_pw4 {
  909. nvidia,pins = "dap_mclk1_pw4";
  910. nvidia,function = "extperiph1";
  911. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  912. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  913. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  914. };
  915. clk2_out_pw5 {
  916. nvidia,pins = "clk2_out_pw5";
  917. nvidia,function = "extperiph2";
  918. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  919. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  920. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  921. };
  922. uart3_txd_pw6 {
  923. nvidia,pins = "uart3_txd_pw6";
  924. nvidia,function = "rsvd2";
  925. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  926. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  927. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  928. };
  929. uart3_rxd_pw7 {
  930. nvidia,pins = "uart3_rxd_pw7";
  931. nvidia,function = "rsvd2";
  932. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  933. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  934. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  935. };
  936. dvfs_pwm_px0 {
  937. nvidia,pins = "dvfs_pwm_px0";
  938. nvidia,function = "cldvfs";
  939. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  940. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  941. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  942. };
  943. gpio_x1_aud_px1 {
  944. nvidia,pins = "gpio_x1_aud_px1";
  945. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  946. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  947. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  948. };
  949. dvfs_clk_px2 {
  950. nvidia,pins = "dvfs_clk_px2";
  951. nvidia,function = "cldvfs";
  952. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  953. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  954. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  955. };
  956. gpio_x3_aud_px3 {
  957. nvidia,pins = "gpio_x3_aud_px3";
  958. nvidia,function = "rsvd4";
  959. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  960. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  961. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  962. };
  963. gpio_x4_aud_px4 {
  964. nvidia,pins = "gpio_x4_aud_px4";
  965. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  966. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  967. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  968. };
  969. gpio_x5_aud_px5 {
  970. nvidia,pins = "gpio_x5_aud_px5";
  971. nvidia,function = "rsvd4";
  972. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  973. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  974. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  975. };
  976. gpio_x6_aud_px6 {
  977. nvidia,pins = "gpio_x6_aud_px6";
  978. nvidia,function = "gmi";
  979. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  980. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  981. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  982. };
  983. gpio_x7_aud_px7 {
  984. nvidia,pins = "gpio_x7_aud_px7";
  985. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  986. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  987. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  988. };
  989. ulpi_clk_py0 {
  990. nvidia,pins = "ulpi_clk_py0";
  991. nvidia,function = "spi1";
  992. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  993. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  994. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  995. };
  996. ulpi_dir_py1 {
  997. nvidia,pins = "ulpi_dir_py1";
  998. nvidia,function = "spi1";
  999. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1000. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1001. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1002. };
  1003. ulpi_nxt_py2 {
  1004. nvidia,pins = "ulpi_nxt_py2";
  1005. nvidia,function = "spi1";
  1006. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1007. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1008. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1009. };
  1010. ulpi_stp_py3 {
  1011. nvidia,pins = "ulpi_stp_py3";
  1012. nvidia,function = "spi1";
  1013. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1014. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1015. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1016. };
  1017. sdmmc1_dat3_py4 {
  1018. nvidia,pins = "sdmmc1_dat3_py4";
  1019. nvidia,function = "sdmmc1";
  1020. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1021. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1022. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1023. };
  1024. sdmmc1_dat2_py5 {
  1025. nvidia,pins = "sdmmc1_dat2_py5";
  1026. nvidia,function = "sdmmc1";
  1027. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1028. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1029. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1030. };
  1031. sdmmc1_dat1_py6 {
  1032. nvidia,pins = "sdmmc1_dat1_py6";
  1033. nvidia,function = "sdmmc1";
  1034. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1035. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1036. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1037. };
  1038. sdmmc1_dat0_py7 {
  1039. nvidia,pins = "sdmmc1_dat0_py7";
  1040. nvidia,function = "rsvd2";
  1041. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1042. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1043. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1044. };
  1045. sdmmc1_clk_pz0 {
  1046. nvidia,pins = "sdmmc1_clk_pz0";
  1047. nvidia,function = "rsvd3";
  1048. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1049. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1050. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1051. };
  1052. sdmmc1_cmd_pz1 {
  1053. nvidia,pins = "sdmmc1_cmd_pz1";
  1054. nvidia,function = "sdmmc1";
  1055. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1056. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1057. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1058. };
  1059. pwr_i2c_scl_pz6 {
  1060. nvidia,pins = "pwr_i2c_scl_pz6";
  1061. nvidia,function = "i2cpwr";
  1062. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1063. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1064. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1065. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1066. };
  1067. pwr_i2c_sda_pz7 {
  1068. nvidia,pins = "pwr_i2c_sda_pz7";
  1069. nvidia,function = "i2cpwr";
  1070. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1071. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1072. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1073. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1074. };
  1075. sdmmc4_dat0_paa0 {
  1076. nvidia,pins = "sdmmc4_dat0_paa0";
  1077. nvidia,function = "sdmmc4";
  1078. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1079. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1080. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1081. };
  1082. sdmmc4_dat1_paa1 {
  1083. nvidia,pins = "sdmmc4_dat1_paa1";
  1084. nvidia,function = "sdmmc4";
  1085. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1086. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1087. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1088. };
  1089. sdmmc4_dat2_paa2 {
  1090. nvidia,pins = "sdmmc4_dat2_paa2";
  1091. nvidia,function = "sdmmc4";
  1092. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1093. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1094. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1095. };
  1096. sdmmc4_dat3_paa3 {
  1097. nvidia,pins = "sdmmc4_dat3_paa3";
  1098. nvidia,function = "sdmmc4";
  1099. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1100. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1101. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1102. };
  1103. sdmmc4_dat4_paa4 {
  1104. nvidia,pins = "sdmmc4_dat4_paa4";
  1105. nvidia,function = "sdmmc4";
  1106. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1107. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1108. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1109. };
  1110. sdmmc4_dat5_paa5 {
  1111. nvidia,pins = "sdmmc4_dat5_paa5";
  1112. nvidia,function = "sdmmc4";
  1113. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1114. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1115. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1116. };
  1117. sdmmc4_dat6_paa6 {
  1118. nvidia,pins = "sdmmc4_dat6_paa6";
  1119. nvidia,function = "sdmmc4";
  1120. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1121. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1122. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1123. };
  1124. sdmmc4_dat7_paa7 {
  1125. nvidia,pins = "sdmmc4_dat7_paa7";
  1126. nvidia,function = "sdmmc4";
  1127. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1128. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1129. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1130. };
  1131. pbb0 {
  1132. nvidia,pins = "pbb0";
  1133. nvidia,function = "vimclk2_alt";
  1134. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1135. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1136. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1137. };
  1138. cam_i2c_scl_pbb1 {
  1139. nvidia,pins = "cam_i2c_scl_pbb1";
  1140. nvidia,function = "i2c3";
  1141. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1142. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1143. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1144. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1145. };
  1146. cam_i2c_sda_pbb2 {
  1147. nvidia,pins = "cam_i2c_sda_pbb2";
  1148. nvidia,function = "i2c3";
  1149. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1150. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1151. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1152. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1153. };
  1154. pbb3 {
  1155. nvidia,pins = "pbb3";
  1156. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1157. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1158. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1159. };
  1160. pbb4 {
  1161. nvidia,pins = "pbb4";
  1162. nvidia,function = "vgp4";
  1163. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1164. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1165. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1166. };
  1167. pbb5 {
  1168. nvidia,pins = "pbb5";
  1169. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1170. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1171. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1172. };
  1173. pbb6 {
  1174. nvidia,pins = "pbb6";
  1175. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1176. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1177. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1178. };
  1179. pbb7 {
  1180. nvidia,pins = "pbb7";
  1181. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1182. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1183. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1184. };
  1185. cam_mclk_pcc0 {
  1186. nvidia,pins = "cam_mclk_pcc0";
  1187. nvidia,function = "vi_alt3";
  1188. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1189. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1190. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1191. };
  1192. pcc1 {
  1193. nvidia,pins = "pcc1";
  1194. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1195. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1196. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1197. };
  1198. pcc2 {
  1199. nvidia,pins = "pcc2";
  1200. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1201. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1202. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1203. };
  1204. sdmmc4_clk_pcc4 {
  1205. nvidia,pins = "sdmmc4_clk_pcc4";
  1206. nvidia,function = "sdmmc4";
  1207. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1208. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1209. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1210. };
  1211. clk2_req_pcc5 {
  1212. nvidia,pins = "clk2_req_pcc5";
  1213. nvidia,function = "rsvd2";
  1214. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1215. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1216. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1217. };
  1218. pex_l0_rst_n_pdd1 {
  1219. nvidia,pins = "pex_l0_rst_n_pdd1";
  1220. nvidia,function = "pe0";
  1221. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1222. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1223. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1224. };
  1225. pex_l0_clkreq_n_pdd2 {
  1226. nvidia,pins = "pex_l0_clkreq_n_pdd2";
  1227. nvidia,function = "pe0";
  1228. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1229. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1230. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1231. };
  1232. pex_wake_n_pdd3 {
  1233. nvidia,pins = "pex_wake_n_pdd3";
  1234. nvidia,function = "pe";
  1235. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1236. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1237. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1238. };
  1239. pex_l1_rst_n_pdd5 {
  1240. nvidia,pins = "pex_l1_rst_n_pdd5";
  1241. nvidia,function = "pe1";
  1242. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1243. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1244. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1245. };
  1246. pex_l1_clkreq_n_pdd6 {
  1247. nvidia,pins = "pex_l1_clkreq_n_pdd6";
  1248. nvidia,function = "pe1";
  1249. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1250. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1251. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1252. };
  1253. clk3_out_pee0 {
  1254. nvidia,pins = "clk3_out_pee0";
  1255. nvidia,function = "extperiph3";
  1256. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1257. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1258. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1259. };
  1260. clk3_req_pee1 {
  1261. nvidia,pins = "clk3_req_pee1";
  1262. nvidia,function = "rsvd2";
  1263. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1264. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1265. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1266. };
  1267. dap_mclk1_req_pee2 {
  1268. nvidia,pins = "dap_mclk1_req_pee2";
  1269. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1270. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1271. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1272. };
  1273. hdmi_cec_pee3 {
  1274. nvidia,pins = "hdmi_cec_pee3";
  1275. nvidia,function = "cec";
  1276. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1277. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1278. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1279. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1280. };
  1281. sdmmc3_clk_lb_out_pee4 {
  1282. nvidia,pins = "sdmmc3_clk_lb_out_pee4";
  1283. nvidia,function = "sdmmc3";
  1284. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1285. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1286. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1287. };
  1288. sdmmc3_clk_lb_in_pee5 {
  1289. nvidia,pins = "sdmmc3_clk_lb_in_pee5";
  1290. nvidia,function = "sdmmc3";
  1291. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1292. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1293. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1294. };
  1295. dp_hpd_pff0 {
  1296. nvidia,pins = "dp_hpd_pff0";
  1297. nvidia,function = "dp";
  1298. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1299. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1300. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1301. };
  1302. usb_vbus_en2_pff1 {
  1303. nvidia,pins = "usb_vbus_en2_pff1";
  1304. nvidia,function = "rsvd2";
  1305. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1306. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1307. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1308. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1309. };
  1310. pff2 {
  1311. nvidia,pins = "pff2";
  1312. nvidia,function = "rsvd2";
  1313. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1314. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1315. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1316. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1317. };
  1318. core_pwr_req {
  1319. nvidia,pins = "core_pwr_req";
  1320. nvidia,function = "pwron";
  1321. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1322. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1323. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1324. };
  1325. cpu_pwr_req {
  1326. nvidia,pins = "cpu_pwr_req";
  1327. nvidia,function = "cpu";
  1328. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1329. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1330. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1331. };
  1332. pwr_int_n {
  1333. nvidia,pins = "pwr_int_n";
  1334. nvidia,function = "pmi";
  1335. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1336. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1337. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1338. };
  1339. reset_out_n {
  1340. nvidia,pins = "reset_out_n";
  1341. nvidia,function = "reset_out_n";
  1342. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1343. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1344. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1345. };
  1346. clk_32k_in {
  1347. nvidia,pins = "clk_32k_in";
  1348. nvidia,function = "clk";
  1349. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1350. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1351. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1352. };
  1353. jtag_rtck {
  1354. nvidia,pins = "jtag_rtck";
  1355. nvidia,function = "rtck";
  1356. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1357. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1358. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1359. };
  1360. dsi_b {
  1361. nvidia,pins = "mipi_pad_ctrl_dsi_b";
  1362. nvidia,function = "dsi_b";
  1363. };
  1364. };
  1365. };
  1366. /*
  1367. * First high speed UART, exposed on the expansion connector J3A2
  1368. * Pin 41: BR_UART1_TXD
  1369. * Pin 44: BR_UART1_RXD
  1370. */
  1371. serial@70006000 {
  1372. compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
  1373. /delete-property/ reg-shift;
  1374. status = "okay";
  1375. };
  1376. /*
  1377. * Second high speed UART, exposed on the expansion connector J3A2
  1378. * Pin 65: UART2_RXD
  1379. * Pin 68: UART2_TXD
  1380. * Pin 71: UART2_CTS_L
  1381. * Pin 74: UART2_RTS_L
  1382. */
  1383. serial@70006040 {
  1384. compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
  1385. /delete-property/ reg-shift;
  1386. status = "okay";
  1387. };
  1388. /* DB9 serial port */
  1389. serial@70006300 {
  1390. status = "okay";
  1391. };
  1392. /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */
  1393. i2c@7000c000 {
  1394. status = "okay";
  1395. clock-frequency = <100000>;
  1396. rt5639: audio-codec@1c {
  1397. compatible = "realtek,rt5639";
  1398. reg = <0x1c>;
  1399. interrupt-parent = <&gpio>;
  1400. interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
  1401. realtek,ldo1-en-gpios =
  1402. <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
  1403. };
  1404. temperature-sensor@4c {
  1405. compatible = "ti,tmp451";
  1406. reg = <0x4c>;
  1407. interrupt-parent = <&gpio>;
  1408. interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_EDGE_FALLING>;
  1409. };
  1410. eeprom@56 {
  1411. compatible = "atmel,24c02";
  1412. reg = <0x56>;
  1413. pagesize = <8>;
  1414. };
  1415. };
  1416. /* Expansion GEN2_I2C_* */
  1417. i2c@7000c400 {
  1418. status = "okay";
  1419. clock-frequency = <100000>;
  1420. };
  1421. /* Expansion CAM_I2C_* */
  1422. i2c@7000c500 {
  1423. status = "okay";
  1424. clock-frequency = <100000>;
  1425. };
  1426. /* HDMI DDC */
  1427. hdmi_ddc: i2c@7000c700 {
  1428. status = "okay";
  1429. clock-frequency = <100000>;
  1430. };
  1431. /* Expansion PWR_I2C_*, on-board components */
  1432. i2c@7000d000 {
  1433. status = "okay";
  1434. clock-frequency = <400000>;
  1435. pmic: pmic@40 {
  1436. compatible = "ams,as3722";
  1437. reg = <0x40>;
  1438. interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
  1439. ams,system-power-controller;
  1440. #interrupt-cells = <2>;
  1441. interrupt-controller;
  1442. gpio-controller;
  1443. #gpio-cells = <2>;
  1444. pinctrl-names = "default";
  1445. pinctrl-0 = <&as3722_default>;
  1446. as3722_default: pinmux {
  1447. gpio0 {
  1448. pins = "gpio0";
  1449. function = "gpio";
  1450. bias-pull-down;
  1451. };
  1452. gpio1_2_4_7 {
  1453. pins = "gpio1", "gpio2", "gpio4", "gpio7";
  1454. function = "gpio";
  1455. bias-pull-up;
  1456. };
  1457. gpio3_5_6 {
  1458. pins = "gpio3", "gpio5", "gpio6";
  1459. bias-high-impedance;
  1460. };
  1461. };
  1462. regulators {
  1463. vsup-sd2-supply = <&vdd_5v0_sys>;
  1464. vsup-sd3-supply = <&vdd_5v0_sys>;
  1465. vsup-sd4-supply = <&vdd_5v0_sys>;
  1466. vsup-sd5-supply = <&vdd_5v0_sys>;
  1467. vin-ldo0-supply = <&vdd_1v35_lp0>;
  1468. vin-ldo1-6-supply = <&vdd_3v3_run>;
  1469. vin-ldo2-5-7-supply = <&vddio_1v8>;
  1470. vin-ldo3-4-supply = <&vdd_3v3_sys>;
  1471. vin-ldo9-10-supply = <&vdd_5v0_sys>;
  1472. vin-ldo11-supply = <&vdd_3v3_run>;
  1473. vdd_cpu: sd0 {
  1474. regulator-name = "+VDD_CPU_AP";
  1475. regulator-min-microvolt = <700000>;
  1476. regulator-max-microvolt = <1400000>;
  1477. regulator-min-microamp = <3500000>;
  1478. regulator-max-microamp = <3500000>;
  1479. regulator-always-on;
  1480. regulator-boot-on;
  1481. ams,ext-control = <2>;
  1482. };
  1483. sd1 {
  1484. regulator-name = "+VDD_CORE";
  1485. regulator-min-microvolt = <700000>;
  1486. regulator-max-microvolt = <1350000>;
  1487. regulator-min-microamp = <2500000>;
  1488. regulator-max-microamp = <2500000>;
  1489. regulator-always-on;
  1490. regulator-boot-on;
  1491. ams,ext-control = <1>;
  1492. };
  1493. vdd_1v35_lp0: sd2 {
  1494. regulator-name = "+1.35V_LP0(sd2)";
  1495. regulator-min-microvolt = <1350000>;
  1496. regulator-max-microvolt = <1350000>;
  1497. regulator-always-on;
  1498. regulator-boot-on;
  1499. };
  1500. sd3 {
  1501. regulator-name = "+1.35V_LP0(sd3)";
  1502. regulator-min-microvolt = <1350000>;
  1503. regulator-max-microvolt = <1350000>;
  1504. regulator-always-on;
  1505. regulator-boot-on;
  1506. };
  1507. vdd_1v05_run: sd4 {
  1508. regulator-name = "+1.05V_RUN";
  1509. regulator-min-microvolt = <1050000>;
  1510. regulator-max-microvolt = <1050000>;
  1511. };
  1512. vddio_1v8: sd5 {
  1513. regulator-name = "+1.8V_VDDIO";
  1514. regulator-min-microvolt = <1800000>;
  1515. regulator-max-microvolt = <1800000>;
  1516. regulator-boot-on;
  1517. regulator-always-on;
  1518. };
  1519. vdd_gpu: sd6 {
  1520. regulator-name = "+VDD_GPU_AP";
  1521. regulator-min-microvolt = <650000>;
  1522. regulator-max-microvolt = <1200000>;
  1523. regulator-min-microamp = <3500000>;
  1524. regulator-max-microamp = <3500000>;
  1525. regulator-boot-on;
  1526. regulator-always-on;
  1527. };
  1528. avdd_1v05_run: ldo0 {
  1529. regulator-name = "+1.05V_RUN_AVDD";
  1530. regulator-min-microvolt = <1050000>;
  1531. regulator-max-microvolt = <1050000>;
  1532. regulator-boot-on;
  1533. regulator-always-on;
  1534. ams,ext-control = <1>;
  1535. };
  1536. ldo1 {
  1537. regulator-name = "+1.8V_RUN_CAM";
  1538. regulator-min-microvolt = <1800000>;
  1539. regulator-max-microvolt = <1800000>;
  1540. };
  1541. ldo2 {
  1542. regulator-name = "+1.2V_GEN_AVDD";
  1543. regulator-min-microvolt = <1200000>;
  1544. regulator-max-microvolt = <1200000>;
  1545. regulator-boot-on;
  1546. regulator-always-on;
  1547. };
  1548. ldo3 {
  1549. regulator-name = "+1.05V_LP0_VDD_RTC";
  1550. regulator-min-microvolt = <1000000>;
  1551. regulator-max-microvolt = <1000000>;
  1552. regulator-boot-on;
  1553. regulator-always-on;
  1554. ams,enable-tracking;
  1555. };
  1556. ldo4 {
  1557. regulator-name = "+2.8V_RUN_CAM";
  1558. regulator-min-microvolt = <2800000>;
  1559. regulator-max-microvolt = <2800000>;
  1560. };
  1561. ldo5 {
  1562. regulator-name = "+1.2V_RUN_CAM_FRONT";
  1563. regulator-min-microvolt = <1200000>;
  1564. regulator-max-microvolt = <1200000>;
  1565. };
  1566. vddio_sdmmc3: ldo6 {
  1567. regulator-name = "+VDDIO_SDMMC3";
  1568. regulator-min-microvolt = <1800000>;
  1569. regulator-max-microvolt = <3300000>;
  1570. };
  1571. ldo7 {
  1572. regulator-name = "+1.05V_RUN_CAM_REAR";
  1573. regulator-min-microvolt = <1050000>;
  1574. regulator-max-microvolt = <1050000>;
  1575. };
  1576. ldo9 {
  1577. regulator-name = "+3.3V_RUN_TOUCH";
  1578. regulator-min-microvolt = <2800000>;
  1579. regulator-max-microvolt = <2800000>;
  1580. };
  1581. ldo10 {
  1582. regulator-name = "+2.8V_RUN_CAM_AF";
  1583. regulator-min-microvolt = <2800000>;
  1584. regulator-max-microvolt = <2800000>;
  1585. };
  1586. ldo11 {
  1587. regulator-name = "+1.8V_RUN_VPP_FUSE";
  1588. regulator-min-microvolt = <1800000>;
  1589. regulator-max-microvolt = <1800000>;
  1590. };
  1591. };
  1592. };
  1593. };
  1594. /* Expansion TS_SPI_* */
  1595. spi@7000d400 {
  1596. status = "okay";
  1597. };
  1598. /* Internal SPI */
  1599. spi@7000da00 {
  1600. status = "okay";
  1601. spi-max-frequency = <25000000>;
  1602. flash@0 {
  1603. compatible = "winbond,w25q32dw", "jedec,spi-nor";
  1604. reg = <0>;
  1605. spi-max-frequency = <20000000>;
  1606. };
  1607. };
  1608. pmc@7000e400 {
  1609. nvidia,invert-interrupt;
  1610. nvidia,suspend-mode = <1>;
  1611. nvidia,cpu-pwr-good-time = <500>;
  1612. nvidia,cpu-pwr-off-time = <300>;
  1613. nvidia,core-pwr-good-time = <641 3845>;
  1614. nvidia,core-pwr-off-time = <61036>;
  1615. nvidia,core-power-req-active-high;
  1616. nvidia,sys-clock-req-active-high;
  1617. i2c-thermtrip {
  1618. nvidia,i2c-controller-id = <4>;
  1619. nvidia,bus-addr = <0x40>;
  1620. nvidia,reg-addr = <0x36>;
  1621. nvidia,reg-data = <0x2>;
  1622. };
  1623. };
  1624. /* Serial ATA */
  1625. sata@70020000 {
  1626. status = "okay";
  1627. phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
  1628. phy-names = "sata-0";
  1629. hvdd-supply = <&vdd_3v3_lp0>;
  1630. vddio-supply = <&vdd_1v05_run>;
  1631. avdd-supply = <&vdd_1v05_run>;
  1632. target-5v-supply = <&vdd_5v0_sata>;
  1633. target-12v-supply = <&vdd_12v0_sata>;
  1634. };
  1635. hda@70030000 {
  1636. status = "okay";
  1637. };
  1638. usb@70090000 {
  1639. phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */
  1640. <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */
  1641. <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */
  1642. <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */
  1643. phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
  1644. avddio-pex-supply = <&vdd_1v05_run>;
  1645. dvddio-pex-supply = <&vdd_1v05_run>;
  1646. avdd-usb-supply = <&vdd_3v3_lp0>;
  1647. avdd-pll-utmip-supply = <&vddio_1v8>;
  1648. avdd-pll-erefe-supply = <&avdd_1v05_run>;
  1649. avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
  1650. hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
  1651. hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
  1652. status = "okay";
  1653. };
  1654. padctl@7009f000 {
  1655. status = "okay";
  1656. avdd-pll-utmip-supply = <&vddio_1v8>;
  1657. avdd-pll-erefe-supply = <&avdd_1v05_run>;
  1658. avdd-pex-pll-supply = <&vdd_1v05_run>;
  1659. hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
  1660. pads {
  1661. usb2 {
  1662. status = "okay";
  1663. lanes {
  1664. usb2-0 {
  1665. nvidia,function = "snps";
  1666. status = "okay";
  1667. };
  1668. usb2-1 {
  1669. nvidia,function = "xusb";
  1670. status = "okay";
  1671. };
  1672. usb2-2 {
  1673. nvidia,function = "xusb";
  1674. status = "okay";
  1675. };
  1676. };
  1677. };
  1678. pcie {
  1679. status = "okay";
  1680. lanes {
  1681. pcie-0 {
  1682. nvidia,function = "usb3-ss";
  1683. status = "okay";
  1684. };
  1685. pcie-2 {
  1686. nvidia,function = "pcie";
  1687. status = "okay";
  1688. };
  1689. pcie-4 {
  1690. nvidia,function = "pcie";
  1691. status = "okay";
  1692. };
  1693. };
  1694. };
  1695. sata {
  1696. status = "okay";
  1697. lanes {
  1698. sata-0 {
  1699. nvidia,function = "sata";
  1700. status = "okay";
  1701. };
  1702. };
  1703. };
  1704. };
  1705. ports {
  1706. /* Micro A/B */
  1707. usb2-0 {
  1708. status = "okay";
  1709. mode = "host";
  1710. };
  1711. /* Mini PCIe */
  1712. usb2-1 {
  1713. status = "okay";
  1714. mode = "host";
  1715. };
  1716. /* USB3 */
  1717. usb2-2 {
  1718. status = "okay";
  1719. mode = "host";
  1720. vbus-supply = <&vdd_usb3_vbus>;
  1721. };
  1722. usb3-0 {
  1723. nvidia,usb2-companion = <2>;
  1724. status = "okay";
  1725. };
  1726. };
  1727. };
  1728. /* SD card */
  1729. mmc@700b0400 {
  1730. status = "okay";
  1731. cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  1732. power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
  1733. wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
  1734. bus-width = <4>;
  1735. vqmmc-supply = <&vddio_sdmmc3>;
  1736. };
  1737. /* eMMC */
  1738. mmc@700b0600 {
  1739. status = "okay";
  1740. bus-width = <8>;
  1741. non-removable;
  1742. };
  1743. /* CPU DFLL clock */
  1744. clock@70110000 {
  1745. status = "okay";
  1746. vdd-cpu-supply = <&vdd_cpu>;
  1747. nvidia,i2c-fs-rate = <400000>;
  1748. };
  1749. ahub@70300000 {
  1750. i2s@70301100 {
  1751. status = "okay";
  1752. };
  1753. };
  1754. usb@7d000000 {
  1755. compatible = "nvidia,tegra124-udc";
  1756. status = "okay";
  1757. dr_mode = "peripheral";
  1758. };
  1759. usb-phy@7d000000 {
  1760. status = "okay";
  1761. };
  1762. /* mini-PCIe USB */
  1763. usb@7d004000 {
  1764. status = "okay";
  1765. };
  1766. usb-phy@7d004000 {
  1767. status = "okay";
  1768. };
  1769. /* USB A connector */
  1770. usb@7d008000 {
  1771. status = "okay";
  1772. };
  1773. usb-phy@7d008000 {
  1774. status = "okay";
  1775. vbus-supply = <&vdd_usb3_vbus>;
  1776. };
  1777. clk32k_in: clock-32k {
  1778. compatible = "fixed-clock";
  1779. clock-frequency = <32768>;
  1780. #clock-cells = <0>;
  1781. };
  1782. cpus {
  1783. cpu@0 {
  1784. vdd-cpu-supply = <&vdd_cpu>;
  1785. };
  1786. };
  1787. gpio-keys {
  1788. compatible = "gpio-keys";
  1789. key-power {
  1790. label = "Power";
  1791. gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
  1792. linux,code = <KEY_POWER>;
  1793. debounce-interval = <10>;
  1794. wakeup-source;
  1795. };
  1796. };
  1797. vdd_mux: regulator-mux {
  1798. compatible = "regulator-fixed";
  1799. regulator-name = "+VDD_MUX";
  1800. regulator-min-microvolt = <12000000>;
  1801. regulator-max-microvolt = <12000000>;
  1802. regulator-always-on;
  1803. regulator-boot-on;
  1804. };
  1805. vdd_5v0_sys: regulator-5v0sys {
  1806. compatible = "regulator-fixed";
  1807. regulator-name = "+5V_SYS";
  1808. regulator-min-microvolt = <5000000>;
  1809. regulator-max-microvolt = <5000000>;
  1810. regulator-always-on;
  1811. regulator-boot-on;
  1812. vin-supply = <&vdd_mux>;
  1813. };
  1814. vdd_3v3_sys: regulator-3v3sys {
  1815. compatible = "regulator-fixed";
  1816. regulator-name = "+3.3V_SYS";
  1817. regulator-min-microvolt = <3300000>;
  1818. regulator-max-microvolt = <3300000>;
  1819. regulator-always-on;
  1820. regulator-boot-on;
  1821. vin-supply = <&vdd_mux>;
  1822. };
  1823. vdd_3v3_run: regulator-3v3run {
  1824. compatible = "regulator-fixed";
  1825. regulator-name = "+3.3V_RUN";
  1826. regulator-min-microvolt = <3300000>;
  1827. regulator-max-microvolt = <3300000>;
  1828. regulator-always-on;
  1829. regulator-boot-on;
  1830. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  1831. enable-active-high;
  1832. vin-supply = <&vdd_3v3_sys>;
  1833. };
  1834. vdd_3v3_hdmi: regulator-3v3hdmi {
  1835. compatible = "regulator-fixed";
  1836. regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
  1837. regulator-min-microvolt = <3300000>;
  1838. regulator-max-microvolt = <3300000>;
  1839. vin-supply = <&vdd_3v3_run>;
  1840. };
  1841. vdd_usb1_vbus: regulator-usb1 {
  1842. compatible = "regulator-fixed";
  1843. regulator-name = "+USB0_VBUS_SW";
  1844. regulator-min-microvolt = <5000000>;
  1845. regulator-max-microvolt = <5000000>;
  1846. gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
  1847. enable-active-high;
  1848. gpio-open-drain;
  1849. vin-supply = <&vdd_5v0_sys>;
  1850. };
  1851. vdd_usb3_vbus: regulator-usb3 {
  1852. compatible = "regulator-fixed";
  1853. regulator-name = "+5V_USB_HS";
  1854. regulator-min-microvolt = <5000000>;
  1855. regulator-max-microvolt = <5000000>;
  1856. gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
  1857. enable-active-high;
  1858. gpio-open-drain;
  1859. vin-supply = <&vdd_5v0_sys>;
  1860. };
  1861. vdd_3v3_lp0: regulator-lp0 {
  1862. compatible = "regulator-fixed";
  1863. regulator-name = "+3.3V_LP0";
  1864. regulator-min-microvolt = <3300000>;
  1865. regulator-max-microvolt = <3300000>;
  1866. regulator-always-on;
  1867. regulator-boot-on;
  1868. gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
  1869. enable-active-high;
  1870. vin-supply = <&vdd_3v3_sys>;
  1871. };
  1872. vdd_hdmi_pll: regulator-hdmipll {
  1873. compatible = "regulator-fixed";
  1874. regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
  1875. regulator-min-microvolt = <1050000>;
  1876. regulator-max-microvolt = <1050000>;
  1877. gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
  1878. vin-supply = <&vdd_1v05_run>;
  1879. };
  1880. vdd_5v0_hdmi: regulator-hdmicon {
  1881. compatible = "regulator-fixed";
  1882. regulator-name = "+5V_HDMI_CON";
  1883. regulator-min-microvolt = <5000000>;
  1884. regulator-max-microvolt = <5000000>;
  1885. gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  1886. enable-active-high;
  1887. vin-supply = <&vdd_5v0_sys>;
  1888. };
  1889. /* Molex power connector */
  1890. vdd_5v0_sata: regulator-5v0sata {
  1891. compatible = "regulator-fixed";
  1892. regulator-name = "+5V_SATA";
  1893. regulator-min-microvolt = <5000000>;
  1894. regulator-max-microvolt = <5000000>;
  1895. gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
  1896. enable-active-high;
  1897. vin-supply = <&vdd_5v0_sys>;
  1898. };
  1899. vdd_12v0_sata: regulator-12v0sata {
  1900. compatible = "regulator-fixed";
  1901. regulator-name = "+12V_SATA";
  1902. regulator-min-microvolt = <12000000>;
  1903. regulator-max-microvolt = <12000000>;
  1904. gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
  1905. enable-active-high;
  1906. vin-supply = <&vdd_mux>;
  1907. };
  1908. sound {
  1909. compatible = "nvidia,tegra-audio-rt5640-jetson-tk1",
  1910. "nvidia,tegra-audio-rt5640";
  1911. nvidia,model = "NVIDIA Tegra Jetson TK1";
  1912. nvidia,audio-routing =
  1913. "Headphones", "HPOR",
  1914. "Headphones", "HPOL",
  1915. "Mic Jack", "MICBIAS1",
  1916. "IN2P", "Mic Jack";
  1917. nvidia,i2s-controller = <&tegra_i2s1>;
  1918. nvidia,audio-codec = <&rt5639>;
  1919. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>;
  1920. clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
  1921. <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
  1922. <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
  1923. clock-names = "pll_a", "pll_a_out0", "mclk";
  1924. assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
  1925. <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
  1926. assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
  1927. <&tegra_car TEGRA124_CLK_EXTERN1>;
  1928. };
  1929. thermal-zones {
  1930. cpu-thermal {
  1931. trips {
  1932. cpu-shutdown-trip {
  1933. temperature = <101000>;
  1934. hysteresis = <0>;
  1935. type = "critical";
  1936. };
  1937. };
  1938. };
  1939. mem-thermal {
  1940. trips {
  1941. mem-shutdown-trip {
  1942. temperature = <101000>;
  1943. hysteresis = <0>;
  1944. type = "critical";
  1945. };
  1946. };
  1947. };
  1948. gpu-thermal {
  1949. trips {
  1950. gpu-shutdown-trip {
  1951. temperature = <101000>;
  1952. hysteresis = <0>;
  1953. type = "critical";
  1954. };
  1955. };
  1956. };
  1957. };
  1958. };