tegra114-roth.dts 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include <dt-bindings/input/input.h>
  4. #include "tegra114.dtsi"
  5. / {
  6. model = "NVIDIA SHIELD";
  7. compatible = "nvidia,roth", "nvidia,tegra114";
  8. chosen {
  9. /* SHIELD's bootloader's arguments need to be overridden */
  10. bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:1";
  11. /* SHIELD's bootloader will place initrd at this address */
  12. linux,initrd-start = <0x82000000>;
  13. linux,initrd-end = <0x82800000>;
  14. };
  15. aliases {
  16. serial0 = &uartd;
  17. };
  18. firmware {
  19. trusted-foundations {
  20. compatible = "tlm,trusted-foundations";
  21. tlm,version-major = <2>;
  22. tlm,version-minor = <8>;
  23. };
  24. };
  25. memory@80000000 {
  26. /* memory >= 0x79600000 is reserved for firmware usage */
  27. reg = <0x80000000 0x79600000>;
  28. };
  29. host1x@50000000 {
  30. dsi@54300000 {
  31. status = "okay";
  32. avdd-dsi-csi-supply = <&vdd_1v2_ap>;
  33. panel@0 {
  34. compatible = "lg,lh500wx1-sd03";
  35. reg = <0>;
  36. power-supply = <&vdd_lcd>;
  37. backlight = <&backlight>;
  38. };
  39. };
  40. };
  41. pinmux@70000868 {
  42. pinctrl-names = "default";
  43. pinctrl-0 = <&state_default>;
  44. state_default: pinmux {
  45. clk1_out_pw4 {
  46. nvidia,pins = "clk1_out_pw4";
  47. nvidia,function = "extperiph1";
  48. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  49. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  50. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  51. };
  52. dap1_din_pn1 {
  53. nvidia,pins = "dap1_din_pn1";
  54. nvidia,function = "i2s0";
  55. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  56. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  57. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  58. };
  59. dap1_dout_pn2 {
  60. nvidia,pins = "dap1_dout_pn2",
  61. "dap1_fs_pn0",
  62. "dap1_sclk_pn3";
  63. nvidia,function = "i2s0";
  64. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  65. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  66. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  67. };
  68. dap2_din_pa4 {
  69. nvidia,pins = "dap2_din_pa4";
  70. nvidia,function = "i2s1";
  71. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  72. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  73. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  74. };
  75. dap2_dout_pa5 {
  76. nvidia,pins = "dap2_dout_pa5",
  77. "dap2_fs_pa2",
  78. "dap2_sclk_pa3";
  79. nvidia,function = "i2s1";
  80. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  81. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  82. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  83. };
  84. dap4_din_pp5 {
  85. nvidia,pins = "dap4_din_pp5",
  86. "dap4_dout_pp6",
  87. "dap4_fs_pp4",
  88. "dap4_sclk_pp7";
  89. nvidia,function = "i2s3";
  90. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  91. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  92. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  93. };
  94. dvfs_pwm_px0 {
  95. nvidia,pins = "dvfs_pwm_px0",
  96. "dvfs_clk_px2";
  97. nvidia,function = "cldvfs";
  98. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  99. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  100. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  101. };
  102. ulpi_clk_py0 {
  103. nvidia,pins = "ulpi_clk_py0",
  104. "ulpi_data0_po1",
  105. "ulpi_data1_po2",
  106. "ulpi_data2_po3",
  107. "ulpi_data3_po4",
  108. "ulpi_data4_po5",
  109. "ulpi_data5_po6",
  110. "ulpi_data6_po7",
  111. "ulpi_data7_po0";
  112. nvidia,function = "ulpi";
  113. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  114. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  115. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  116. };
  117. ulpi_dir_py1 {
  118. nvidia,pins = "ulpi_dir_py1",
  119. "ulpi_nxt_py2";
  120. nvidia,function = "ulpi";
  121. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  122. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  123. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  124. };
  125. ulpi_stp_py3 {
  126. nvidia,pins = "ulpi_stp_py3";
  127. nvidia,function = "ulpi";
  128. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  129. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  130. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  131. };
  132. cam_i2c_scl_pbb1 {
  133. nvidia,pins = "cam_i2c_scl_pbb1",
  134. "cam_i2c_sda_pbb2";
  135. nvidia,function = "i2c3";
  136. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  137. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  138. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  139. nvidia,lock = <TEGRA_PIN_DISABLE>;
  140. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  141. };
  142. cam_mclk_pcc0 {
  143. nvidia,pins = "cam_mclk_pcc0",
  144. "pbb0";
  145. nvidia,function = "vi_alt3";
  146. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  147. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  148. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  149. nvidia,lock = <TEGRA_PIN_DISABLE>;
  150. };
  151. pbb4 {
  152. nvidia,pins = "pbb4";
  153. nvidia,function = "vgp4";
  154. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  155. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  156. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  157. nvidia,lock = <TEGRA_PIN_DISABLE>;
  158. };
  159. gen2_i2c_scl_pt5 {
  160. nvidia,pins = "gen2_i2c_scl_pt5",
  161. "gen2_i2c_sda_pt6";
  162. nvidia,function = "i2c2";
  163. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  164. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  165. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  166. nvidia,lock = <TEGRA_PIN_DISABLE>;
  167. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  168. };
  169. gmi_a16_pj7 {
  170. nvidia,pins = "gmi_a16_pj7",
  171. "gmi_a19_pk7";
  172. nvidia,function = "uartd";
  173. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  174. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  175. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  176. };
  177. gmi_a17_pb0 {
  178. nvidia,pins = "gmi_a17_pb0",
  179. "gmi_a18_pb1";
  180. nvidia,function = "uartd";
  181. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  182. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  183. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  184. };
  185. gmi_ad5_pg5 {
  186. nvidia,pins = "gmi_ad5_pg5",
  187. "gmi_wr_n_pi0";
  188. nvidia,function = "spi4";
  189. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  190. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  191. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  192. };
  193. gmi_ad6_pg6 {
  194. nvidia,pins = "gmi_ad6_pg6",
  195. "gmi_ad7_pg7";
  196. nvidia,function = "spi4";
  197. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  198. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  199. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  200. };
  201. gmi_ad12_ph4 {
  202. nvidia,pins = "gmi_ad12_ph4";
  203. nvidia,function = "rsvd4";
  204. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  205. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  206. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  207. };
  208. gmi_cs6_n_pi13 {
  209. nvidia,pins = "gmi_cs6_n_pi3";
  210. nvidia,function = "nand";
  211. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  212. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  213. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  214. };
  215. gmi_ad9_ph1 {
  216. nvidia,pins = "gmi_ad9_ph1";
  217. nvidia,function = "pwm1";
  218. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  219. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  220. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  221. };
  222. gmi_cs1_n_pj2 {
  223. nvidia,pins = "gmi_cs1_n_pj2",
  224. "gmi_oe_n_pi1";
  225. nvidia,function = "soc";
  226. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  227. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  228. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  229. };
  230. gmi_rst_n_pi4 {
  231. nvidia,pins = "gmi_rst_n_pi4";
  232. nvidia,function = "gmi";
  233. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  234. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  235. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  236. };
  237. gmi_iordy_pi5 {
  238. nvidia,pins = "gmi_iordy_pi5";
  239. nvidia,function = "gmi";
  240. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  241. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  242. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  243. };
  244. clk2_out_pw5 {
  245. nvidia,pins = "clk2_out_pw5";
  246. nvidia,function = "extperiph2";
  247. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  248. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  249. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  250. };
  251. sdmmc1_clk_pz0 {
  252. nvidia,pins = "sdmmc1_clk_pz0";
  253. nvidia,function = "sdmmc1";
  254. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  255. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  256. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  257. };
  258. sdmmc1_cmd_pz1 {
  259. nvidia,pins = "sdmmc1_cmd_pz1",
  260. "sdmmc1_dat0_py7",
  261. "sdmmc1_dat1_py6",
  262. "sdmmc1_dat2_py5",
  263. "sdmmc1_dat3_py4";
  264. nvidia,function = "sdmmc1";
  265. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  266. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  267. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  268. };
  269. sdmmc3_clk_pa6 {
  270. nvidia,pins = "sdmmc3_clk_pa6";
  271. nvidia,function = "sdmmc3";
  272. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  273. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  274. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  275. };
  276. sdmmc3_cmd_pa7 {
  277. nvidia,pins = "sdmmc3_cmd_pa7",
  278. "sdmmc3_dat0_pb7",
  279. "sdmmc3_dat1_pb6",
  280. "sdmmc3_dat2_pb5",
  281. "sdmmc3_dat3_pb4",
  282. "sdmmc3_cd_n_pv2",
  283. "sdmmc3_clk_lb_out_pee4",
  284. "sdmmc3_clk_lb_in_pee5";
  285. nvidia,function = "sdmmc3";
  286. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  287. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  288. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  289. };
  290. kb_col4_pq4 {
  291. nvidia,pins = "kb_col4_pq4";
  292. nvidia,function = "sdmmc3";
  293. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  294. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  295. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  296. };
  297. sdmmc4_clk_pcc4 {
  298. nvidia,pins = "sdmmc4_clk_pcc4";
  299. nvidia,function = "sdmmc4";
  300. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  301. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  302. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  303. };
  304. sdmmc4_cmd_pt7 {
  305. nvidia,pins = "sdmmc4_cmd_pt7",
  306. "sdmmc4_dat0_paa0",
  307. "sdmmc4_dat1_paa1",
  308. "sdmmc4_dat2_paa2",
  309. "sdmmc4_dat3_paa3",
  310. "sdmmc4_dat4_paa4",
  311. "sdmmc4_dat5_paa5",
  312. "sdmmc4_dat6_paa6",
  313. "sdmmc4_dat7_paa7";
  314. nvidia,function = "sdmmc4";
  315. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  316. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  317. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  318. };
  319. clk_32k_out_pa0 {
  320. nvidia,pins = "clk_32k_out_pa0";
  321. nvidia,function = "blink";
  322. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  323. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  324. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  325. };
  326. kb_col0_pq0 {
  327. nvidia,pins = "kb_col0_pq0",
  328. "kb_col1_pq1",
  329. "kb_col2_pq2",
  330. "kb_row0_pr0",
  331. "kb_row1_pr1",
  332. "kb_row2_pr2",
  333. "kb_row8_ps0";
  334. nvidia,function = "kbc";
  335. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  336. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  337. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  338. };
  339. kb_row7_pr7 {
  340. nvidia,pins = "kb_row7_pr7";
  341. nvidia,function = "rsvd2";
  342. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  343. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  344. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  345. };
  346. kb_row10_ps2 {
  347. nvidia,pins = "kb_row10_ps2";
  348. nvidia,function = "uarta";
  349. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  350. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  351. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  352. };
  353. kb_row9_ps1 {
  354. nvidia,pins = "kb_row9_ps1";
  355. nvidia,function = "uarta";
  356. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  357. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  358. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  359. };
  360. pwr_i2c_scl_pz6 {
  361. nvidia,pins = "pwr_i2c_scl_pz6",
  362. "pwr_i2c_sda_pz7";
  363. nvidia,function = "i2cpwr";
  364. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  365. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  366. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  367. nvidia,lock = <TEGRA_PIN_DISABLE>;
  368. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  369. };
  370. sys_clk_req_pz5 {
  371. nvidia,pins = "sys_clk_req_pz5";
  372. nvidia,function = "sysclk";
  373. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  374. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  375. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  376. };
  377. core_pwr_req {
  378. nvidia,pins = "core_pwr_req";
  379. nvidia,function = "pwron";
  380. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  381. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  382. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  383. };
  384. cpu_pwr_req {
  385. nvidia,pins = "cpu_pwr_req";
  386. nvidia,function = "cpu";
  387. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  388. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  389. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  390. };
  391. pwr_int_n {
  392. nvidia,pins = "pwr_int_n";
  393. nvidia,function = "pmi";
  394. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  395. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  396. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  397. };
  398. reset_out_n {
  399. nvidia,pins = "reset_out_n";
  400. nvidia,function = "reset_out_n";
  401. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  402. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  403. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  404. };
  405. clk3_out_pee0 {
  406. nvidia,pins = "clk3_out_pee0";
  407. nvidia,function = "extperiph3";
  408. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  409. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  410. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  411. };
  412. gen1_i2c_scl_pc4 {
  413. nvidia,pins = "gen1_i2c_scl_pc4",
  414. "gen1_i2c_sda_pc5";
  415. nvidia,function = "i2c1";
  416. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  417. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  418. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  419. nvidia,lock = <TEGRA_PIN_DISABLE>;
  420. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  421. };
  422. uart2_cts_n_pj5 {
  423. nvidia,pins = "uart2_cts_n_pj5";
  424. nvidia,function = "uartb";
  425. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  426. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  427. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  428. };
  429. uart2_rts_n_pj6 {
  430. nvidia,pins = "uart2_rts_n_pj6";
  431. nvidia,function = "uartb";
  432. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  433. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  434. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  435. };
  436. uart2_rxd_pc3 {
  437. nvidia,pins = "uart2_rxd_pc3";
  438. nvidia,function = "irda";
  439. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  440. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  441. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  442. };
  443. uart2_txd_pc2 {
  444. nvidia,pins = "uart2_txd_pc2";
  445. nvidia,function = "irda";
  446. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  447. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  448. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  449. };
  450. uart3_cts_n_pa1 {
  451. nvidia,pins = "uart3_cts_n_pa1",
  452. "uart3_rxd_pw7";
  453. nvidia,function = "uartc";
  454. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  455. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  456. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  457. };
  458. uart3_rts_n_pc0 {
  459. nvidia,pins = "uart3_rts_n_pc0",
  460. "uart3_txd_pw6";
  461. nvidia,function = "uartc";
  462. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  463. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  464. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  465. };
  466. owr {
  467. nvidia,pins = "owr";
  468. nvidia,function = "owr";
  469. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  470. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  471. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  472. };
  473. hdmi_cec_pee3 {
  474. nvidia,pins = "hdmi_cec_pee3";
  475. nvidia,function = "cec";
  476. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  477. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  478. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  479. nvidia,lock = <TEGRA_PIN_DISABLE>;
  480. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  481. };
  482. ddc_scl_pv4 {
  483. nvidia,pins = "ddc_scl_pv4",
  484. "ddc_sda_pv5";
  485. nvidia,function = "i2c4";
  486. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  487. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  488. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  489. nvidia,lock = <TEGRA_PIN_DISABLE>;
  490. nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
  491. };
  492. spdif_in_pk6 {
  493. nvidia,pins = "spdif_in_pk6";
  494. nvidia,function = "usb";
  495. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  496. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  497. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  498. nvidia,lock = <TEGRA_PIN_DISABLE>;
  499. };
  500. usb_vbus_en0_pn4 {
  501. nvidia,pins = "usb_vbus_en0_pn4";
  502. nvidia,function = "usb";
  503. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  504. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  505. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  506. nvidia,lock = <TEGRA_PIN_DISABLE>;
  507. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  508. };
  509. gpio_x6_aud_px6 {
  510. nvidia,pins = "gpio_x6_aud_px6";
  511. nvidia,function = "spi6";
  512. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  513. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  514. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  515. };
  516. gpio_x1_aud_px1 {
  517. nvidia,pins = "gpio_x1_aud_px1";
  518. nvidia,function = "rsvd2";
  519. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  520. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  521. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  522. };
  523. gpio_x7_aud_px7 {
  524. nvidia,pins = "gpio_x7_aud_px7";
  525. nvidia,function = "rsvd1";
  526. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  527. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  528. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  529. };
  530. gmi_adv_n_pk0 {
  531. nvidia,pins = "gmi_adv_n_pk0";
  532. nvidia,function = "gmi";
  533. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  534. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  535. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  536. };
  537. gmi_cs0_n_pj0 {
  538. nvidia,pins = "gmi_cs0_n_pj0";
  539. nvidia,function = "gmi";
  540. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  541. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  542. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  543. };
  544. pu3 {
  545. nvidia,pins = "pu3";
  546. nvidia,function = "pwm0";
  547. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  548. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  549. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  550. };
  551. gpio_x4_aud_px4 {
  552. nvidia,pins = "gpio_x4_aud_px4",
  553. "gpio_x5_aud_px5";
  554. nvidia,function = "rsvd1";
  555. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  556. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  557. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  558. };
  559. gpio_x3_aud_px3 {
  560. nvidia,pins = "gpio_x3_aud_px3";
  561. nvidia,function = "rsvd4";
  562. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  563. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  564. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  565. };
  566. gpio_w2_aud_pw2 {
  567. nvidia,pins = "gpio_w2_aud_pw2";
  568. nvidia,function = "rsvd2";
  569. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  570. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  571. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  572. };
  573. gpio_w3_aud_pw3 {
  574. nvidia,pins = "gpio_w3_aud_pw3";
  575. nvidia,function = "spi6";
  576. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  577. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  578. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  579. };
  580. dap3_fs_pp0 {
  581. nvidia,pins = "dap3_fs_pp0",
  582. "dap3_din_pp1",
  583. "dap3_dout_pp2",
  584. "dap3_sclk_pp3";
  585. nvidia,function = "i2s2";
  586. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  587. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  588. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  589. };
  590. pv0 {
  591. nvidia,pins = "pv0";
  592. nvidia,function = "rsvd4";
  593. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  594. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  595. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  596. };
  597. pv1 {
  598. nvidia,pins = "pv1";
  599. nvidia,function = "rsvd1";
  600. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  601. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  602. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  603. };
  604. pbb3 {
  605. nvidia,pins = "pbb3",
  606. "pbb5",
  607. "pbb6",
  608. "pbb7";
  609. nvidia,function = "rsvd4";
  610. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  611. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  612. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  613. };
  614. pcc1 {
  615. nvidia,pins = "pcc1",
  616. "pcc2";
  617. nvidia,function = "rsvd4";
  618. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  619. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  620. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  621. };
  622. gmi_ad0_pg0 {
  623. nvidia,pins = "gmi_ad0_pg0",
  624. "gmi_ad1_pg1";
  625. nvidia,function = "gmi";
  626. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  627. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  628. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  629. };
  630. gmi_ad10_ph2 {
  631. nvidia,pins = "gmi_ad10_ph2",
  632. "gmi_ad12_ph4",
  633. "gmi_ad15_ph7",
  634. "gmi_cs3_n_pk4";
  635. nvidia,function = "gmi";
  636. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  637. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  638. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  639. };
  640. gmi_ad11_ph3 {
  641. nvidia,pins = "gmi_ad11_ph3",
  642. "gmi_ad13_ph5",
  643. "gmi_ad8_ph0",
  644. "gmi_clk_pk1",
  645. "gmi_cs2_n_pk3";
  646. nvidia,function = "gmi";
  647. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  648. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  649. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  650. };
  651. gmi_ad14_ph6 {
  652. nvidia,pins = "gmi_ad14_ph6",
  653. "gmi_cs0_n_pj0",
  654. "gmi_cs4_n_pk2",
  655. "gmi_cs7_n_pi6",
  656. "gmi_dqs_p_pj3",
  657. "gmi_wp_n_pc7";
  658. nvidia,function = "gmi";
  659. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  660. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  661. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  662. };
  663. gmi_ad2_pg2 {
  664. nvidia,pins = "gmi_ad2_pg2",
  665. "gmi_ad3_pg3";
  666. nvidia,function = "gmi";
  667. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  668. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  669. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  670. };
  671. sdmmc1_wp_n_pv3 {
  672. nvidia,pins = "sdmmc1_wp_n_pv3";
  673. nvidia,function = "spi4";
  674. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  675. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  676. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  677. };
  678. clk2_req_pcc5 {
  679. nvidia,pins = "clk2_req_pcc5";
  680. nvidia,function = "rsvd4";
  681. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  682. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  683. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  684. };
  685. kb_col3_pq3 {
  686. nvidia,pins = "kb_col3_pq3";
  687. nvidia,function = "pwm2";
  688. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  689. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  690. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  691. };
  692. kb_col5_pq5 {
  693. nvidia,pins = "kb_col5_pq5";
  694. nvidia,function = "kbc";
  695. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  696. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  697. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  698. };
  699. kb_col6_pq6 {
  700. nvidia,pins = "kb_col6_pq6",
  701. "kb_col7_pq7";
  702. nvidia,function = "kbc";
  703. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  704. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  705. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  706. };
  707. kb_row3_pr3 {
  708. nvidia,pins = "kb_row3_pr3",
  709. "kb_row4_pr4",
  710. "kb_row6_pr6";
  711. nvidia,function = "kbc";
  712. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  713. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  714. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  715. };
  716. clk3_req_pee1 {
  717. nvidia,pins = "clk3_req_pee1";
  718. nvidia,function = "rsvd4";
  719. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  720. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  721. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  722. };
  723. pu2 {
  724. nvidia,pins = "pu2";
  725. nvidia,function = "rsvd1";
  726. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  727. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  728. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  729. };
  730. hdmi_int_pn7 {
  731. nvidia,pins = "hdmi_int_pn7";
  732. nvidia,function = "rsvd1";
  733. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  734. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  735. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  736. };
  737. drive_sdio1 {
  738. nvidia,pins = "drive_sdio1";
  739. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  740. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  741. nvidia,pull-down-strength = <36>;
  742. nvidia,pull-up-strength = <20>;
  743. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
  744. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
  745. };
  746. drive_sdio3 {
  747. nvidia,pins = "drive_sdio3";
  748. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  749. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  750. nvidia,pull-down-strength = <36>;
  751. nvidia,pull-up-strength = <20>;
  752. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  753. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  754. };
  755. drive_gma {
  756. nvidia,pins = "drive_gma";
  757. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  758. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  759. nvidia,pull-down-strength = <2>;
  760. nvidia,pull-up-strength = <2>;
  761. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  762. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  763. };
  764. };
  765. };
  766. /* Usable on reworked devices only */
  767. serial@70006300 {
  768. status = "okay";
  769. };
  770. pwm@7000a000 {
  771. status = "okay";
  772. };
  773. i2c@7000d000 {
  774. status = "okay";
  775. clock-frequency = <400000>;
  776. regulator@43 {
  777. compatible = "ti,tps51632";
  778. reg = <0x43>;
  779. regulator-name = "vdd-cpu";
  780. regulator-min-microvolt = <500000>;
  781. regulator-max-microvolt = <1520000>;
  782. regulator-always-on;
  783. regulator-boot-on;
  784. };
  785. palmas: pmic@58 {
  786. compatible = "ti,tps65913", "ti,palmas";
  787. reg = <0x58>;
  788. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  789. #interrupt-cells = <2>;
  790. interrupt-controller;
  791. ti,system-power-controller;
  792. palmas_gpio: gpio {
  793. compatible = "ti,palmas-gpio";
  794. gpio-controller;
  795. #gpio-cells = <2>;
  796. };
  797. pmic {
  798. compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
  799. regulators {
  800. smps12 {
  801. regulator-name = "vdd-ddr";
  802. regulator-min-microvolt = <1200000>;
  803. regulator-max-microvolt = <1500000>;
  804. regulator-always-on;
  805. regulator-boot-on;
  806. };
  807. vdd_1v8: smps3 {
  808. regulator-name = "vdd-1v8";
  809. regulator-min-microvolt = <1800000>;
  810. regulator-max-microvolt = <1800000>;
  811. regulator-boot-on;
  812. };
  813. smps457 {
  814. regulator-name = "vdd-soc";
  815. regulator-min-microvolt = <900000>;
  816. regulator-max-microvolt = <1400000>;
  817. regulator-always-on;
  818. regulator-boot-on;
  819. };
  820. smps8 {
  821. regulator-name = "avdd-pll-1v05";
  822. regulator-min-microvolt = <1050000>;
  823. regulator-max-microvolt = <1050000>;
  824. regulator-always-on;
  825. regulator-boot-on;
  826. };
  827. smps9 {
  828. regulator-name = "vdd-2v85-emmc";
  829. regulator-min-microvolt = <2800000>;
  830. regulator-max-microvolt = <2800000>;
  831. regulator-always-on;
  832. };
  833. smps10_out1 {
  834. regulator-name = "vdd-fan";
  835. regulator-min-microvolt = <5000000>;
  836. regulator-max-microvolt = <5000000>;
  837. regulator-always-on;
  838. regulator-boot-on;
  839. };
  840. smps10_out2 {
  841. regulator-name = "vdd-5v0-sys";
  842. regulator-min-microvolt = <5000000>;
  843. regulator-max-microvolt = <5000000>;
  844. regulator-always-on;
  845. regulator-boot-on;
  846. };
  847. ldo2 {
  848. regulator-name = "vdd-2v8-display";
  849. regulator-min-microvolt = <2800000>;
  850. regulator-max-microvolt = <2800000>;
  851. regulator-always-on;
  852. regulator-boot-on;
  853. };
  854. vdd_1v2_ap: ldo3 {
  855. regulator-name = "avdd-1v2";
  856. regulator-min-microvolt = <1200000>;
  857. regulator-max-microvolt = <1200000>;
  858. regulator-always-on;
  859. regulator-boot-on;
  860. };
  861. ldo4 {
  862. regulator-name = "vpp-fuse";
  863. regulator-min-microvolt = <1800000>;
  864. regulator-max-microvolt = <1800000>;
  865. };
  866. ldo5 {
  867. regulator-name = "avdd-hdmi-pll";
  868. regulator-min-microvolt = <1200000>;
  869. regulator-max-microvolt = <1200000>;
  870. };
  871. ldo6 {
  872. regulator-name = "vdd-sensor-2v8";
  873. regulator-min-microvolt = <2850000>;
  874. regulator-max-microvolt = <2850000>;
  875. };
  876. ldo8 {
  877. regulator-name = "vdd-rtc";
  878. regulator-min-microvolt = <1100000>;
  879. regulator-max-microvolt = <1100000>;
  880. regulator-always-on;
  881. regulator-boot-on;
  882. ti,enable-ldo8-tracking;
  883. };
  884. vddio_sdmmc3: ldo9 {
  885. regulator-name = "vddio-sdmmc3";
  886. regulator-min-microvolt = <1800000>;
  887. regulator-max-microvolt = <3300000>;
  888. };
  889. ldousb {
  890. regulator-name = "avdd-usb-hdmi";
  891. regulator-min-microvolt = <3300000>;
  892. regulator-max-microvolt = <3300000>;
  893. regulator-always-on;
  894. regulator-boot-on;
  895. };
  896. vdd_3v3_sys: regen1 {
  897. regulator-name = "rail-3v3";
  898. regulator-max-microvolt = <3300000>;
  899. regulator-always-on;
  900. regulator-boot-on;
  901. };
  902. regen2 {
  903. regulator-name = "rail-5v0";
  904. regulator-max-microvolt = <5000000>;
  905. regulator-always-on;
  906. regulator-boot-on;
  907. };
  908. };
  909. };
  910. rtc {
  911. compatible = "ti,palmas-rtc";
  912. interrupt-parent = <&palmas>;
  913. interrupts = <8 0>;
  914. };
  915. };
  916. };
  917. pmc@7000e400 {
  918. nvidia,invert-interrupt;
  919. };
  920. /* SD card */
  921. mmc@78000400 {
  922. status = "okay";
  923. bus-width = <4>;
  924. vqmmc-supply = <&vddio_sdmmc3>;
  925. cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  926. power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
  927. };
  928. /* eMMC */
  929. mmc@78000600 {
  930. status = "okay";
  931. bus-width = <8>;
  932. non-removable;
  933. };
  934. /* External USB port (must be powered) */
  935. usb@7d000000 {
  936. status = "okay";
  937. };
  938. usb-phy@7d000000 {
  939. status = "okay";
  940. nvidia,xcvr-setup = <7>;
  941. nvidia,xcvr-lsfslew = <2>;
  942. nvidia,xcvr-lsrslew = <2>;
  943. interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  944. /* Should be changed to "otg" once we have vbus_supply */
  945. /* As of now, USB devices need to be powered externally */
  946. dr_mode = "host";
  947. };
  948. /* SHIELD controller */
  949. usb@7d008000 {
  950. status = "okay";
  951. };
  952. usb-phy@7d008000 {
  953. status = "okay";
  954. nvidia,xcvr-setup = <7>;
  955. nvidia,xcvr-lsfslew = <2>;
  956. nvidia,xcvr-lsrslew = <2>;
  957. };
  958. backlight: backlight {
  959. compatible = "pwm-backlight";
  960. pwms = <&pwm 1 40000>;
  961. brightness-levels = <0 4 8 16 32 64 128 255>;
  962. default-brightness-level = <6>;
  963. power-supply = <&lcd_bl_en>;
  964. enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
  965. };
  966. clk32k_in: clock-32k {
  967. compatible = "fixed-clock";
  968. clock-frequency = <32768>;
  969. #clock-cells = <0>;
  970. };
  971. gpio-keys {
  972. compatible = "gpio-keys";
  973. key-back {
  974. label = "Back";
  975. gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
  976. linux,code = <KEY_BACK>;
  977. };
  978. key-home {
  979. label = "Home";
  980. gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
  981. linux,code = <KEY_HOME>;
  982. };
  983. key-power {
  984. label = "Power";
  985. gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
  986. linux,code = <KEY_POWER>;
  987. wakeup-source;
  988. };
  989. };
  990. lcd_bl_en: regulator-lcden {
  991. compatible = "regulator-fixed";
  992. regulator-name = "lcd_bl_en";
  993. regulator-min-microvolt = <5000000>;
  994. regulator-max-microvolt = <5000000>;
  995. regulator-boot-on;
  996. };
  997. vdd_lcd: regulator-lcd {
  998. compatible = "regulator-fixed";
  999. regulator-name = "vdd_lcd_1v8";
  1000. regulator-min-microvolt = <1800000>;
  1001. regulator-max-microvolt = <1800000>;
  1002. vin-supply = <&vdd_1v8>;
  1003. enable-active-high;
  1004. gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
  1005. regulator-boot-on;
  1006. };
  1007. regulator-1v8ts {
  1008. compatible = "regulator-fixed";
  1009. regulator-name = "vdd_1v8_ts";
  1010. regulator-min-microvolt = <1800000>;
  1011. regulator-max-microvolt = <1800000>;
  1012. gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>;
  1013. regulator-boot-on;
  1014. };
  1015. regulator-3v3ts {
  1016. compatible = "regulator-fixed";
  1017. regulator-name = "vdd_3v3_ts";
  1018. regulator-min-microvolt = <3300000>;
  1019. regulator-max-microvolt = <3300000>;
  1020. enable-active-high;
  1021. gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
  1022. regulator-boot-on;
  1023. };
  1024. regulator-1v8com {
  1025. compatible = "regulator-fixed";
  1026. regulator-name = "vdd_1v8_com";
  1027. regulator-min-microvolt = <1800000>;
  1028. regulator-max-microvolt = <1800000>;
  1029. vin-supply = <&vdd_1v8>;
  1030. enable-active-high;
  1031. gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
  1032. regulator-boot-on;
  1033. };
  1034. regulator-3v3com {
  1035. compatible = "regulator-fixed";
  1036. regulator-name = "vdd_3v3_com";
  1037. regulator-min-microvolt = <3300000>;
  1038. regulator-max-microvolt = <3300000>;
  1039. vin-supply = <&vdd_3v3_sys>;
  1040. enable-active-high;
  1041. gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
  1042. regulator-always-on;
  1043. regulator-boot-on;
  1044. };
  1045. };