sunplus-sp7021.dtsi 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for Sunplus SP7021
  4. *
  5. * Copyright (C) 2021 Sunplus Technology Co.
  6. */
  7. #include <dt-bindings/clock/sunplus,sp7021-clkc.h>
  8. #include <dt-bindings/interrupt-controller/irq.h>
  9. #include <dt-bindings/reset/sunplus,sp7021-reset.h>
  10. #include <dt-bindings/pinctrl/sppctl-sp7021.h>
  11. #include <dt-bindings/gpio/gpio.h>
  12. #define XTAL 27000000
  13. / {
  14. compatible = "sunplus,sp7021";
  15. model = "Sunplus SP7021";
  16. clocks {
  17. extclk: osc0 {
  18. compatible = "fixed-clock";
  19. #clock-cells = <0>;
  20. clock-frequency = <XTAL>;
  21. clock-output-names = "extclk";
  22. };
  23. };
  24. soc@9c000000 {
  25. compatible = "simple-bus";
  26. #address-cells = <1>;
  27. #size-cells = <1>;
  28. ranges = <0 0x9c000000 0x400000>;
  29. interrupt-parent = <&intc>;
  30. clkc: clock-controller@4 {
  31. compatible = "sunplus,sp7021-clkc";
  32. reg = <0x4 0x28>,
  33. <0x200 0x44>,
  34. <0x268 0x04>;
  35. clocks = <&extclk>;
  36. #clock-cells = <1>;
  37. };
  38. intc: interrupt-controller@780 {
  39. compatible = "sunplus,sp7021-intc";
  40. reg = <0x780 0x80>, <0xa80 0x80>;
  41. interrupt-controller;
  42. #interrupt-cells = <2>;
  43. };
  44. otp: otp@af00 {
  45. compatible = "sunplus,sp7021-ocotp";
  46. reg = <0xaf00 0x34>, <0xaf80 0x58>;
  47. reg-names = "hb_gpio", "otprx";
  48. clocks = <&clkc CLK_OTPRX>;
  49. resets = <&rstc RST_OTPRX>;
  50. #address-cells = <1>;
  51. #size-cells = <1>;
  52. therm_calib: thermal-calibration@14 {
  53. reg = <0x14 0x3>;
  54. };
  55. disc_vol: disconnect-voltage@18 {
  56. reg = <0x18 0x2>;
  57. };
  58. mac_addr0: mac-address0@34 {
  59. reg = <0x34 0x6>;
  60. };
  61. mac_addr1: mac-address1@3a {
  62. reg = <0x3a 0x6>;
  63. };
  64. };
  65. pctl: pinctrl@100 {
  66. compatible = "sunplus,sp7021-pctl";
  67. reg = <0x100 0x100>,
  68. <0x300 0x100>,
  69. <0x32e4 0x1C>,
  70. <0x80 0x20>;
  71. reg-names = "moon2", "gpioxt", "first", "moon1";
  72. gpio-controller;
  73. #gpio-cells = <2>;
  74. clocks = <&clkc CLK_GPIO>;
  75. resets = <&rstc RST_GPIO>;
  76. emac_pins: pinmux-emac-pins {
  77. sunplus,pins = <
  78. SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0)
  79. SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0)
  80. SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0)
  81. SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0)
  82. SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0)
  83. SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0)
  84. SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0)
  85. SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0)
  86. SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0)
  87. SPPCTL_IOPAD(45,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXER,0)
  88. SPPCTL_IOPAD(59,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXEN,0)
  89. SPPCTL_IOPAD(57,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD0,0)
  90. SPPCTL_IOPAD(58,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD1,0)
  91. SPPCTL_IOPAD(54,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_CRSDV,0)
  92. SPPCTL_IOPAD(55,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD0,0)
  93. SPPCTL_IOPAD(56,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD1,0)
  94. SPPCTL_IOPAD(53,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXER,0)
  95. >;
  96. sunplus,zerofunc = <
  97. MUXF_L2SW_LED_FLASH0
  98. MUXF_L2SW_LED_FLASH1
  99. MUXF_L2SW_LED_ON0
  100. MUXF_L2SW_LED_ON1
  101. MUXF_DAISY_MODE
  102. >;
  103. };
  104. emmc_pins: pinmux-emmc-pins {
  105. function = "CARD0_EMMC";
  106. groups = "CARD0_EMMC";
  107. };
  108. leds_pins: pinmux-leds-pins {
  109. sunplus,pins = < SPPCTL_IOPAD(0,SPPCTL_PCTL_G_GPIO,0,SPPCTL_PCTL_L_OUT) >;
  110. };
  111. sdcard_pins: pinmux-sdcard-pins {
  112. function = "SD_CARD";
  113. groups = "SD_CARD";
  114. sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >;
  115. };
  116. spi0_pins: pinmux-spi0-pins {
  117. sunplus,pins = <
  118. SPPCTL_IOPAD(26,SPPCTL_PCTL_G_GPIO,0,0)
  119. SPPCTL_IOPAD(28,SPPCTL_PCTL_G_GPIO,0,0)
  120. SPPCTL_IOPAD(23,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_DO,0)
  121. SPPCTL_IOPAD(25,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_DI,0)
  122. SPPCTL_IOPAD(27,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_CLK,0)
  123. >;
  124. };
  125. uart0_pins: pinmux-uart0-pins {
  126. function = "UA0";
  127. groups = "UA0";
  128. };
  129. uart1_pins: pinmux-uart1-pins {
  130. sunplus,pins = <
  131. SPPCTL_IOPAD(14,SPPCTL_PCTL_G_PMUX,MUXF_UA4_TX,0)
  132. SPPCTL_IOPAD(16,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RX,0)
  133. >;
  134. };
  135. uart2_pins: pinmux-uart2-pins {
  136. sunplus,pins = <
  137. SPPCTL_IOPAD(16,SPPCTL_PCTL_G_PMUX,MUXF_UA2_TX,0)
  138. SPPCTL_IOPAD(17,SPPCTL_PCTL_G_PMUX,MUXF_UA2_RX,0)
  139. SPPCTL_IOPAD(18,SPPCTL_PCTL_G_PMUX,MUXF_UA2_RTS,0)
  140. SPPCTL_IOPAD(19,SPPCTL_PCTL_G_PMUX,MUXF_UA2_CTS,0)
  141. >;
  142. };
  143. uart4_pins: pinmux-uart4-pins {
  144. sunplus,pins = <
  145. SPPCTL_IOPAD(22,SPPCTL_PCTL_G_PMUX,MUXF_UA4_TX,0)
  146. SPPCTL_IOPAD(20,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RX,0)
  147. SPPCTL_IOPAD(23,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RTS,0)
  148. SPPCTL_IOPAD(21,SPPCTL_PCTL_G_PMUX,MUXF_UA4_CTS,0)
  149. >;
  150. };
  151. };
  152. rstc: reset@54 {
  153. compatible = "sunplus,sp7021-reset";
  154. reg = <0x54 0x28>;
  155. #reset-cells = <1>;
  156. };
  157. rtc: rtc@3a00 {
  158. compatible = "sunplus,sp7021-rtc";
  159. reg = <0x3a00 0x80>;
  160. reg-names = "rtc";
  161. clocks = <&clkc CLK_RTC>;
  162. resets = <&rstc RST_RTC>;
  163. interrupts = <163 IRQ_TYPE_EDGE_RISING>;
  164. };
  165. spi_controller0: spi@2d80 {
  166. compatible = "sunplus,sp7021-spi";
  167. reg = <0x2d80 0x80>, <0x2e00 0x80>;
  168. reg-names = "master", "slave";
  169. interrupts = <144 IRQ_TYPE_LEVEL_HIGH>,
  170. <146 IRQ_TYPE_LEVEL_HIGH>,
  171. <145 IRQ_TYPE_LEVEL_HIGH>;
  172. interrupt-names = "dma_w", "master_risc", "slave_risc";
  173. clocks = <&clkc CLK_SPI_COMBO_0>;
  174. resets = <&rstc RST_SPI_COMBO_0>;
  175. pinctrl-names = "default";
  176. pinctrl-0 = <&spi0_pins>;
  177. cs-gpios = <&pctl 26 GPIO_ACTIVE_LOW>,
  178. <&pctl 28 GPIO_ACTIVE_LOW>;
  179. };
  180. spi_controller1: spi@f480 {
  181. compatible = "sunplus,sp7021-spi";
  182. reg = <0xf480 0x80>, <0xf500 0x80>;
  183. reg-names = "master", "slave";
  184. interrupts = <67 IRQ_TYPE_LEVEL_HIGH>,
  185. <69 IRQ_TYPE_LEVEL_HIGH>,
  186. <68 IRQ_TYPE_LEVEL_HIGH>;
  187. interrupt-names = "dma_w", "master_risc", "slave_risc";
  188. clocks = <&clkc CLK_SPI_COMBO_1>;
  189. resets = <&rstc RST_SPI_COMBO_1>;
  190. spi-max-frequency = <25000000>;
  191. status = "disabled";
  192. };
  193. spi_controller2: spi@f600 {
  194. compatible = "sunplus,sp7021-spi";
  195. reg = <0xf600 0x80>, <0xf680 0x80>;
  196. reg-names = "master", "slave";
  197. interrupts = <70 IRQ_TYPE_LEVEL_HIGH>,
  198. <72 IRQ_TYPE_LEVEL_HIGH>,
  199. <71 IRQ_TYPE_LEVEL_HIGH>;
  200. interrupt-names = "dma_w", "master_risc", "slave_risc";
  201. clocks = <&clkc CLK_SPI_COMBO_2>;
  202. resets = <&rstc RST_SPI_COMBO_2>;
  203. spi-max-frequency = <25000000>;
  204. status = "disabled";
  205. };
  206. spi_controller3: spi@f780 {
  207. compatible = "sunplus,sp7021-spi";
  208. reg = <0xf780 0x80>, <0xf800 0x80>;
  209. reg-names = "master", "slave";
  210. interrupts = <73 IRQ_TYPE_LEVEL_HIGH>,
  211. <75 IRQ_TYPE_LEVEL_HIGH>,
  212. <74 IRQ_TYPE_LEVEL_HIGH>;
  213. interrupt-names = "dma_w", "master_risc", "slave_risc";
  214. clocks = <&clkc CLK_SPI_COMBO_3>;
  215. resets = <&rstc RST_SPI_COMBO_3>;
  216. spi-max-frequency = <25000000>;
  217. status = "disabled";
  218. };
  219. uart0: serial@900 {
  220. compatible = "sunplus,sp7021-uart";
  221. reg = <0x900 0x80>;
  222. interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
  223. clocks = <&clkc CLK_UA0>;
  224. resets = <&rstc RST_UA0>;
  225. pinctrl-names = "default";
  226. pinctrl-0 = <&uart0_pins>;
  227. };
  228. uart1: serial@980 {
  229. compatible = "sunplus,sp7021-uart";
  230. reg = <0x980 0x80>;
  231. interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
  232. clocks = <&clkc CLK_UA1>;
  233. resets = <&rstc RST_UA1>;
  234. pinctrl-names = "default";
  235. pinctrl-0 = <&uart1_pins>;
  236. status = "disabled";
  237. };
  238. uart2: serial@800 {
  239. compatible = "sunplus,sp7021-uart";
  240. reg = <0x800 0x80>;
  241. interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
  242. clocks = <&clkc CLK_UA2>;
  243. resets = <&rstc RST_UA2>;
  244. pinctrl-names = "default";
  245. pinctrl-0 = <&uart2_pins>;
  246. status = "disabled";
  247. };
  248. uart3: serial@880 {
  249. compatible = "sunplus,sp7021-uart";
  250. reg = <0x880 0x80>;
  251. interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
  252. clocks = <&clkc CLK_UA3>;
  253. resets = <&rstc RST_UA3>;
  254. status = "disabled";
  255. };
  256. uart4: serial@8780 {
  257. compatible = "sunplus,sp7021-uart";
  258. reg = <0x8780 0x80>;
  259. interrupts = <134 IRQ_TYPE_LEVEL_HIGH>;
  260. clocks = <&clkc CLK_UA4>;
  261. resets = <&rstc RST_UA4>;
  262. pinctrl-names = "default";
  263. pinctrl-0 = <&uart4_pins>;
  264. status = "disabled";
  265. };
  266. };
  267. leds {
  268. compatible = "gpio-leds";
  269. pinctrl-names = "default";
  270. pinctrl-0 = <&leds_pins>;
  271. system-led {
  272. label = "system-led";
  273. gpios = <&pctl 0 GPIO_ACTIVE_HIGH>;
  274. default-state = "off";
  275. linux,default-trigger = "heartbeat";
  276. };
  277. };
  278. };