stm32mp157a-dk1-scmi.dts 1.5 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879
  1. // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2. /*
  3. * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
  4. * Author: Alexandre Torgue <[email protected]> for STMicroelectronics.
  5. */
  6. /dts-v1/;
  7. #include "stm32mp157a-dk1.dts"
  8. #include "stm32mp15-scmi.dtsi"
  9. / {
  10. model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board";
  11. compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157";
  12. reserved-memory {
  13. optee@de000000 {
  14. reg = <0xde000000 0x2000000>;
  15. no-map;
  16. };
  17. };
  18. };
  19. &cpu0 {
  20. clocks = <&scmi_clk CK_SCMI_MPU>;
  21. };
  22. &cpu1 {
  23. clocks = <&scmi_clk CK_SCMI_MPU>;
  24. };
  25. &dsi {
  26. clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
  27. };
  28. &gpioz {
  29. clocks = <&scmi_clk CK_SCMI_GPIOZ>;
  30. };
  31. &hash1 {
  32. clocks = <&scmi_clk CK_SCMI_HASH1>;
  33. resets = <&scmi_reset RST_SCMI_HASH1>;
  34. };
  35. &i2c4 {
  36. clocks = <&scmi_clk CK_SCMI_I2C4>;
  37. resets = <&scmi_reset RST_SCMI_I2C4>;
  38. };
  39. &iwdg2 {
  40. clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
  41. };
  42. &mdma1 {
  43. resets = <&scmi_reset RST_SCMI_MDMA>;
  44. };
  45. &mlahb {
  46. resets = <&scmi_reset RST_SCMI_MCU>;
  47. };
  48. &rcc {
  49. compatible = "st,stm32mp1-rcc-secure", "syscon";
  50. clock-names = "hse", "hsi", "csi", "lse", "lsi";
  51. clocks = <&scmi_clk CK_SCMI_HSE>,
  52. <&scmi_clk CK_SCMI_HSI>,
  53. <&scmi_clk CK_SCMI_CSI>,
  54. <&scmi_clk CK_SCMI_LSE>,
  55. <&scmi_clk CK_SCMI_LSI>;
  56. };
  57. &rng1 {
  58. clocks = <&scmi_clk CK_SCMI_RNG1>;
  59. resets = <&scmi_reset RST_SCMI_RNG1>;
  60. };
  61. &rtc {
  62. clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
  63. };