ste-dbx5x0-pinctrl.dtsi 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2013 Linaro Ltd.
  4. */
  5. #include "ste-nomadik-pinctrl.dtsi"
  6. &pinctrl {
  7. /* Settings for all UART default and sleep states */
  8. uart0 {
  9. u0_a_1_default: u0_a_1_default {
  10. default_mux {
  11. function = "u0";
  12. groups = "u0_a_1";
  13. };
  14. default_cfg1 {
  15. pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
  16. ste,config = <&in_pu>;
  17. };
  18. default_cfg2 {
  19. pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
  20. ste,config = <&out_hi>;
  21. };
  22. };
  23. u0_a_1_sleep: u0_a_1_sleep {
  24. sleep_cfg1 {
  25. pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
  26. ste,config = <&slpm_in_wkup_pdis>;
  27. };
  28. sleep_cfg2 {
  29. pins = "GPIO1_AJ3"; /* RTS */
  30. ste,config = <&slpm_out_hi_wkup_pdis>;
  31. };
  32. sleep_cfg3 {
  33. pins = "GPIO3_AH3"; /* TXD */
  34. ste,config = <&slpm_out_wkup_pdis>;
  35. };
  36. };
  37. };
  38. uart1 {
  39. u1rxtx_a_1_default: u1rxtx_a_1_default {
  40. default_mux {
  41. function = "u1";
  42. groups = "u1rxtx_a_1";
  43. };
  44. default_cfg1 {
  45. pins = "GPIO4_AH6"; /* RXD */
  46. ste,config = <&in_pu>;
  47. };
  48. default_cfg2 {
  49. pins = "GPIO5_AG6"; /* TXD */
  50. ste,config = <&out_hi>;
  51. };
  52. };
  53. u1rxtx_a_1_sleep: u1rxtx_a_1_sleep {
  54. sleep_cfg1 {
  55. pins = "GPIO4_AH6"; /* RXD */
  56. ste,config = <&slpm_in_wkup_pdis>;
  57. };
  58. sleep_cfg2 {
  59. pins = "GPIO5_AG6"; /* TXD */
  60. ste,config = <&slpm_out_wkup_pdis>;
  61. };
  62. };
  63. u1ctsrts_a_1_default: u1ctsrts_a_1_default {
  64. default_mux {
  65. function = "u1";
  66. groups = "u1ctsrts_a_1";
  67. };
  68. default_cfg1 {
  69. pins = "GPIO6_AF6"; /* CTS */
  70. ste,config = <&in_pu>;
  71. };
  72. default_cfg2 {
  73. pins = "GPIO7_AG5"; /* RTS */
  74. ste,config = <&out_hi>;
  75. };
  76. };
  77. u1ctsrts_a_1_sleep: u1ctsrts_a_1_sleep {
  78. sleep_cfg1 {
  79. pins = "GPIO6_AF6"; /* CTS */
  80. ste,config = <&slpm_in_wkup_pdis>;
  81. };
  82. sleep_cfg2 {
  83. pins = "GPIO7_AG5"; /* RTS */
  84. ste,config = <&slpm_out_hi_wkup_pdis>;
  85. };
  86. };
  87. };
  88. uart2 {
  89. u2rxtx_c_1_default: u2rxtx_c_1_default {
  90. default_mux {
  91. function = "u2";
  92. groups = "u2rxtx_c_1";
  93. };
  94. default_cfg1 {
  95. pins = "GPIO29_W2"; /* RXD */
  96. ste,config = <&in_pu>;
  97. };
  98. default_cfg2 {
  99. pins = "GPIO30_W3"; /* TXD */
  100. ste,config = <&out_hi>;
  101. };
  102. };
  103. u2rxtx_c_1_sleep: u2rxtx_c_1_sleep {
  104. sleep_cfg1 {
  105. pins = "GPIO29_W2"; /* RXD */
  106. ste,config = <&in_wkup_pdis>;
  107. };
  108. sleep_cfg2 {
  109. pins = "GPIO30_W3"; /* TXD */
  110. ste,config = <&out_wkup_pdis>;
  111. };
  112. };
  113. };
  114. /* Settings for all I2C default and sleep states */
  115. i2c0 {
  116. i2c0_a_1_default: i2c0_a_1_default {
  117. default_mux {
  118. function = "i2c0";
  119. groups = "i2c0_a_1";
  120. };
  121. default_cfg1 {
  122. pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
  123. ste,config = <&in_nopull>;
  124. };
  125. };
  126. i2c0_a_1_sleep: i2c0_a_1_sleep {
  127. sleep_cfg1 {
  128. pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
  129. ste,config = <&slpm_in_wkup_pdis>;
  130. };
  131. };
  132. };
  133. i2c1 {
  134. i2c1_b_2_default: i2c1_b_2_default {
  135. default_mux {
  136. function = "i2c1";
  137. groups = "i2c1_b_2";
  138. };
  139. default_cfg1 {
  140. pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
  141. ste,config = <&in_nopull>;
  142. };
  143. };
  144. i2c1_b_2_sleep: i2c1_b_2_sleep {
  145. sleep_cfg1 {
  146. pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
  147. ste,config = <&slpm_in_wkup_pdis>;
  148. };
  149. };
  150. };
  151. i2c2 {
  152. i2c2_b_1_default: i2c2_b_1_default {
  153. default_mux {
  154. function = "i2c2";
  155. groups = "i2c2_b_1";
  156. };
  157. default_cfg1 {
  158. pins = "GPIO8_AD5", "GPIO9_AE4"; /* SDA/SCL */
  159. ste,config = <&in_nopull>;
  160. };
  161. };
  162. i2c2_b_1_sleep: i2c2_b_1_sleep {
  163. sleep_cfg1 {
  164. pins = "GPIO8_AD5", "GPIO9_AE4"; /* SDA/SCL */
  165. ste,config = <&slpm_in_wkup_pdis>;
  166. };
  167. };
  168. i2c2_b_2_default: i2c2_b_2_default {
  169. default_mux {
  170. function = "i2c2";
  171. groups = "i2c2_b_2";
  172. };
  173. default_cfg1 {
  174. pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
  175. ste,config = <&in_nopull>;
  176. };
  177. };
  178. i2c2_b_2_sleep: i2c2_b_2_sleep {
  179. sleep_cfg1 {
  180. pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
  181. ste,config = <&slpm_in_wkup_pdis>;
  182. };
  183. };
  184. };
  185. i2c3 {
  186. i2c3_c_2_default: i2c3_c_2_default {
  187. default_mux {
  188. function = "i2c3";
  189. groups = "i2c3_c_2";
  190. };
  191. default_cfg1 {
  192. pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
  193. ste,config = <&in_nopull>;
  194. };
  195. };
  196. i2c3_c_2_sleep: i2c3_c_2_sleep {
  197. sleep_cfg1 {
  198. pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
  199. ste,config = <&slpm_in_wkup_pdis>;
  200. };
  201. };
  202. };
  203. /*
  204. * Activating I2C4 will conflict with UART1 about the same pins so do not
  205. * enable I2C4 and UART1 at the same time.
  206. */
  207. i2c4 {
  208. i2c4_b_1_default: i2c4_b_1_default {
  209. default_mux {
  210. function = "i2c4";
  211. groups = "i2c4_b_1";
  212. };
  213. default_cfg1 {
  214. pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
  215. ste,config = <&in_nopull>;
  216. };
  217. };
  218. i2c4_b_1_sleep: i2c4_b_1_sleep {
  219. sleep_cfg1 {
  220. pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
  221. ste,config = <&slpm_in_wkup_pdis>;
  222. };
  223. };
  224. };
  225. /* Settings for all MMC/SD/SDIO default and sleep states */
  226. sdi0 {
  227. /* This is the external SD card slot, 4 bits wide */
  228. mc0_a_1_default: mc0_a_1_default {
  229. default_mux {
  230. function = "mc0";
  231. groups = "mc0_a_1";
  232. };
  233. default_cfg1 {
  234. pins =
  235. "GPIO18_AC2", /* CMDDIR */
  236. "GPIO19_AC1", /* DAT0DIR */
  237. "GPIO20_AB4"; /* DAT2DIR */
  238. ste,config = <&out_hi>;
  239. };
  240. default_cfg2 {
  241. pins = "GPIO22_AA3"; /* FBCLK */
  242. ste,config = <&in_nopull>;
  243. };
  244. default_cfg3 {
  245. pins = "GPIO23_AA4"; /* CLK */
  246. ste,config = <&out_lo>;
  247. };
  248. default_cfg4 {
  249. pins =
  250. "GPIO24_AB2", /* CMD */
  251. "GPIO25_Y4", /* DAT0 */
  252. "GPIO26_Y2", /* DAT1 */
  253. "GPIO27_AA2", /* DAT2 */
  254. "GPIO28_AA1"; /* DAT3 */
  255. ste,config = <&in_pu>;
  256. };
  257. };
  258. mc0_a_1_sleep: mc0_a_1_sleep {
  259. sleep_cfg1 {
  260. pins =
  261. "GPIO18_AC2", /* CMDDIR */
  262. "GPIO19_AC1", /* DAT0DIR */
  263. "GPIO20_AB4"; /* DAT2DIR */
  264. ste,config = <&slpm_out_hi_wkup_pdis>;
  265. };
  266. sleep_cfg2 {
  267. pins =
  268. "GPIO22_AA3", /* FBCLK */
  269. "GPIO24_AB2", /* CMD */
  270. "GPIO25_Y4", /* DAT0 */
  271. "GPIO26_Y2", /* DAT1 */
  272. "GPIO27_AA2", /* DAT2 */
  273. "GPIO28_AA1"; /* DAT3 */
  274. ste,config = <&slpm_in_wkup_pdis>;
  275. };
  276. sleep_cfg3 {
  277. pins = "GPIO23_AA4"; /* CLK */
  278. ste,config = <&slpm_out_lo_wkup_pdis>;
  279. };
  280. };
  281. mc0_a_2_default: mc0_a_2_default {
  282. default_mux {
  283. function = "mc0";
  284. groups = "mc0_a_2";
  285. };
  286. default_cfg1 {
  287. pins = "GPIO22_AA3"; /* FBCLK */
  288. ste,config = <&in_nopull>;
  289. };
  290. default_cfg2 {
  291. pins = "GPIO23_AA4"; /* CLK */
  292. ste,config = <&out_lo>;
  293. };
  294. default_cfg3 {
  295. pins =
  296. "GPIO24_AB2", /* CMD */
  297. "GPIO25_Y4", /* DAT0 */
  298. "GPIO26_Y2", /* DAT1 */
  299. "GPIO27_AA2", /* DAT2 */
  300. "GPIO28_AA1"; /* DAT3 */
  301. ste,config = <&in_pu>;
  302. };
  303. };
  304. mc0_a_2_sleep: mc0_a_2_sleep {
  305. sleep_cfg1 {
  306. pins =
  307. "GPIO22_AA3", /* FBCLK */
  308. "GPIO24_AB2", /* CMD */
  309. "GPIO25_Y4", /* DAT0 */
  310. "GPIO26_Y2", /* DAT1 */
  311. "GPIO27_AA2", /* DAT2 */
  312. "GPIO28_AA1"; /* DAT3 */
  313. ste,config = <&slpm_in_wkup_pdis>;
  314. };
  315. sleep_cfg2 {
  316. pins = "GPIO23_AA4"; /* CLK */
  317. ste,config = <&slpm_out_lo_wkup_pdis>;
  318. };
  319. };
  320. };
  321. sdi1 {
  322. /* This is the WLAN SDIO 4 bits wide */
  323. mc1_a_1_default: mc1_a_1_default {
  324. default_mux {
  325. function = "mc1";
  326. groups = "mc1_a_1";
  327. };
  328. default_cfg1 {
  329. pins = "GPIO208_AH16"; /* CLK */
  330. ste,config = <&out_lo>;
  331. };
  332. default_cfg2 {
  333. pins = "GPIO209_AG15"; /* FBCLK */
  334. ste,config = <&in_nopull>;
  335. };
  336. default_cfg3 {
  337. pins =
  338. "GPIO210_AJ15", /* CMD */
  339. "GPIO211_AG14", /* DAT0 */
  340. "GPIO212_AF13", /* DAT1 */
  341. "GPIO213_AG13", /* DAT2 */
  342. "GPIO214_AH15"; /* DAT3 */
  343. ste,config = <&in_pu>;
  344. };
  345. };
  346. mc1_a_1_sleep: mc1_a_1_sleep {
  347. sleep_cfg1 {
  348. pins = "GPIO208_AH16"; /* CLK */
  349. ste,config = <&slpm_out_lo_wkup_pdis>;
  350. };
  351. sleep_cfg2 {
  352. pins =
  353. "GPIO209_AG15", /* FBCLK */
  354. "GPIO210_AJ15", /* CMD */
  355. "GPIO211_AG14", /* DAT0 */
  356. "GPIO212_AF13", /* DAT1 */
  357. "GPIO213_AG13", /* DAT2 */
  358. "GPIO214_AH15"; /* DAT3 */
  359. ste,config = <&slpm_in_wkup_pdis>;
  360. };
  361. };
  362. mc1_a_2_default: mc1_a_2_default {
  363. default_mux {
  364. function = "mc1";
  365. groups = "mc1_a_2";
  366. };
  367. default_cfg1 {
  368. pins = "GPIO208_AH16"; /* CLK */
  369. ste,config = <&out_lo>;
  370. };
  371. default_cfg2 {
  372. pins =
  373. "GPIO210_AJ15", /* CMD */
  374. "GPIO211_AG14", /* DAT0 */
  375. "GPIO212_AF13", /* DAT1 */
  376. "GPIO213_AG13", /* DAT2 */
  377. "GPIO214_AH15"; /* DAT3 */
  378. ste,config = <&in_pu>;
  379. };
  380. };
  381. mc1_a_2_sleep: mc1_a_2_sleep {
  382. sleep_cfg1 {
  383. pins = "GPIO208_AH16"; /* CLK */
  384. ste,config = <&slpm_out_lo_wkup_pdis>;
  385. };
  386. sleep_cfg2 {
  387. pins =
  388. "GPIO210_AJ15", /* CMD */
  389. "GPIO211_AG14", /* DAT0 */
  390. "GPIO212_AF13", /* DAT1 */
  391. "GPIO213_AG13", /* DAT2 */
  392. "GPIO214_AH15"; /* DAT3 */
  393. ste,config = <&slpm_in_wkup_pdis>;
  394. };
  395. };
  396. };
  397. sdi2 {
  398. /* This is the eMMC 8 bits wide, usually PoP eMMC */
  399. mc2_a_1_default: mc2_a_1_default {
  400. default_mux {
  401. function = "mc2";
  402. groups = "mc2_a_1";
  403. };
  404. default_cfg1 {
  405. pins = "GPIO128_A5"; /* CLK */
  406. ste,config = <&out_lo>;
  407. };
  408. default_cfg2 {
  409. pins = "GPIO130_C8"; /* FBCLK */
  410. ste,config = <&in_nopull>;
  411. };
  412. default_cfg3 {
  413. pins =
  414. "GPIO129_B4", /* CMD */
  415. "GPIO131_A12", /* DAT0 */
  416. "GPIO132_C10", /* DAT1 */
  417. "GPIO133_B10", /* DAT2 */
  418. "GPIO134_B9", /* DAT3 */
  419. "GPIO135_A9", /* DAT4 */
  420. "GPIO136_C7", /* DAT5 */
  421. "GPIO137_A7", /* DAT6 */
  422. "GPIO138_C5"; /* DAT7 */
  423. ste,config = <&in_pu>;
  424. };
  425. };
  426. mc2_a_1_sleep: mc2_a_1_sleep {
  427. sleep_cfg1 {
  428. pins = "GPIO128_A5"; /* CLK */
  429. ste,config = <&out_lo_wkup_pdis>;
  430. };
  431. sleep_cfg2 {
  432. pins =
  433. "GPIO130_C8", /* FBCLK */
  434. "GPIO129_B4"; /* CMD */
  435. ste,config = <&in_wkup_pdis_en>;
  436. };
  437. sleep_cfg3 {
  438. pins =
  439. "GPIO131_A12", /* DAT0 */
  440. "GPIO132_C10", /* DAT1 */
  441. "GPIO133_B10", /* DAT2 */
  442. "GPIO134_B9", /* DAT3 */
  443. "GPIO135_A9", /* DAT4 */
  444. "GPIO136_C7", /* DAT5 */
  445. "GPIO137_A7", /* DAT6 */
  446. "GPIO138_C5"; /* DAT7 */
  447. ste,config = <&in_wkup_pdis>;
  448. };
  449. };
  450. };
  451. sdi4 {
  452. /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
  453. mc4_a_1_default: mc4_a_1_default {
  454. default_mux {
  455. function = "mc4";
  456. groups = "mc4_a_1";
  457. };
  458. default_cfg1 {
  459. pins = "GPIO203_AE23"; /* CLK */
  460. ste,config = <&out_lo>;
  461. };
  462. default_cfg2 {
  463. pins = "GPIO202_AF25"; /* FBCLK */
  464. ste,config = <&in_nopull>;
  465. };
  466. default_cfg3 {
  467. pins =
  468. "GPIO201_AF24", /* CMD */
  469. "GPIO200_AH26", /* DAT0 */
  470. "GPIO199_AH23", /* DAT1 */
  471. "GPIO198_AG25", /* DAT2 */
  472. "GPIO197_AH24", /* DAT3 */
  473. "GPIO207_AJ23", /* DAT4 */
  474. "GPIO206_AG24", /* DAT5 */
  475. "GPIO205_AG23", /* DAT6 */
  476. "GPIO204_AF23"; /* DAT7 */
  477. ste,config = <&in_pu>;
  478. };
  479. };
  480. mc4_a_1_sleep: mc4_a_1_sleep {
  481. sleep_cfg1 {
  482. pins = "GPIO203_AE23"; /* CLK */
  483. ste,config = <&out_lo_wkup_pdis>;
  484. };
  485. sleep_cfg2 {
  486. pins =
  487. "GPIO202_AF25", /* FBCLK */
  488. "GPIO201_AF24", /* CMD */
  489. "GPIO200_AH26", /* DAT0 */
  490. "GPIO199_AH23", /* DAT1 */
  491. "GPIO198_AG25", /* DAT2 */
  492. "GPIO197_AH24", /* DAT3 */
  493. "GPIO207_AJ23", /* DAT4 */
  494. "GPIO206_AG24", /* DAT5 */
  495. "GPIO205_AG23", /* DAT6 */
  496. "GPIO204_AF23"; /* DAT7 */
  497. ste,config = <&slpm_in_wkup_pdis>;
  498. };
  499. };
  500. };
  501. /*
  502. * Multi-rate serial ports (MSPs) - MSP3 output is internal and
  503. * cannot be muxed onto any pins.
  504. */
  505. msp0 {
  506. msp0txrxtfstck_a_1_default: msp0txrxtfstck_a_1_default {
  507. default_msp0_mux {
  508. function = "msp0";
  509. groups = "msp0txrx_a_1", "msp0tfstck_a_1";
  510. };
  511. default_msp0_cfg {
  512. pins =
  513. "GPIO12_AC4", /* TXD */
  514. "GPIO15_AC3", /* RXD */
  515. "GPIO13_AF3", /* TFS */
  516. "GPIO14_AE3"; /* TCK */
  517. ste,config = <&in_nopull>;
  518. };
  519. };
  520. };
  521. msp1 {
  522. msp1txrx_a_1_default: msp1txrx_a_1_default {
  523. default_mux {
  524. function = "msp1";
  525. groups = "msp1txrx_a_1", "msp1_a_1";
  526. };
  527. default_cfg1 {
  528. pins = "GPIO33_AF2";
  529. ste,config = <&out_lo>;
  530. };
  531. default_cfg2 {
  532. pins =
  533. "GPIO34_AE1",
  534. "GPIO35_AE2",
  535. "GPIO36_AG2";
  536. ste,config = <&in_nopull>;
  537. };
  538. };
  539. };
  540. msp2 {
  541. msp2_a_1_default: msp2_a_1_default {
  542. /* MSP2 usually used for HDMI audio */
  543. default_mux {
  544. function = "msp2";
  545. groups = "msp2_a_1";
  546. };
  547. default_cfg1 {
  548. pins =
  549. "GPIO193_AH27", /* TXD */
  550. "GPIO194_AF27", /* TCK */
  551. "GPIO195_AG28"; /* TFS */
  552. ste,config = <&in_pd>;
  553. };
  554. default_cfg2 {
  555. pins = "GPIO196_AG26"; /* RXD */
  556. ste,config = <&out_lo>;
  557. };
  558. };
  559. };
  560. musb {
  561. usb_a_1_default: usb_a_1_default {
  562. default_mux {
  563. function = "usb";
  564. groups = "usb_a_1";
  565. };
  566. default_cfg1 {
  567. pins =
  568. "GPIO256_AF28", /* NXT */
  569. "GPIO258_AD29", /* XCLK */
  570. "GPIO259_AC29", /* DIR */
  571. "GPIO260_AD28", /* DAT7 */
  572. "GPIO261_AD26", /* DAT6 */
  573. "GPIO262_AE26", /* DAT5 */
  574. "GPIO263_AG29", /* DAT4 */
  575. "GPIO264_AE27", /* DAT3 */
  576. "GPIO265_AD27", /* DAT2 */
  577. "GPIO266_AC28", /* DAT1 */
  578. "GPIO267_AC27"; /* DAT0 */
  579. ste,config = <&in_nopull>;
  580. };
  581. default_cfg2 {
  582. pins = "GPIO257_AE29"; /* STP */
  583. ste,config = <&out_hi>;
  584. };
  585. };
  586. usb_a_1_sleep: usb_a_1_sleep {
  587. sleep_cfg1 {
  588. pins =
  589. "GPIO256_AF28", /* NXT */
  590. "GPIO258_AD29", /* XCLK */
  591. "GPIO259_AC29"; /* DIR */
  592. ste,config = <&slpm_wkup_pdis_en>;
  593. };
  594. sleep_cfg2 {
  595. pins = "GPIO257_AE29"; /* STP */
  596. ste,config = <&slpm_out_hi_wkup_pdis>;
  597. };
  598. sleep_cfg3 {
  599. pins =
  600. "GPIO260_AD28", /* DAT7 */
  601. "GPIO261_AD26", /* DAT6 */
  602. "GPIO262_AE26", /* DAT5 */
  603. "GPIO263_AG29", /* DAT4 */
  604. "GPIO264_AE27", /* DAT3 */
  605. "GPIO265_AD27", /* DAT2 */
  606. "GPIO266_AC28", /* DAT1 */
  607. "GPIO267_AC27"; /* DAT0 */
  608. ste,config = <&slpm_in_wkup_pdis_en>;
  609. };
  610. };
  611. };
  612. };