spear320.dtsi 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * DTS file for SPEAr320 SoC
  4. *
  5. * Copyright 2012 Viresh Kumar <[email protected]>
  6. */
  7. /include/ "spear3xx.dtsi"
  8. / {
  9. ahb {
  10. #address-cells = <1>;
  11. #size-cells = <1>;
  12. compatible = "simple-bus";
  13. ranges = <0x40000000 0x40000000 0x80000000
  14. 0xd0000000 0xd0000000 0x30000000>;
  15. pinmux: pinmux@b3000000 {
  16. compatible = "st,spear320-pinmux";
  17. reg = <0xb3000000 0x1000>;
  18. #gpio-range-cells = <3>;
  19. };
  20. clcd@90000000 {
  21. compatible = "arm,pl110", "arm,primecell";
  22. reg = <0x90000000 0x1000>;
  23. interrupts = <8>;
  24. interrupt-parent = <&shirq>;
  25. status = "disabled";
  26. };
  27. fsmc: flash@4c000000 {
  28. compatible = "st,spear600-fsmc-nand";
  29. #address-cells = <1>;
  30. #size-cells = <1>;
  31. reg = <0x4c000000 0x1000 /* FSMC Register */
  32. 0x50000000 0x0010 /* NAND Base DATA */
  33. 0x50020000 0x0010 /* NAND Base ADDR */
  34. 0x50010000 0x0010>; /* NAND Base CMD */
  35. reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
  36. status = "disabled";
  37. };
  38. sdhci@70000000 {
  39. compatible = "st,sdhci-spear";
  40. reg = <0x70000000 0x100>;
  41. interrupts = <10>;
  42. interrupt-parent = <&shirq>;
  43. status = "disabled";
  44. };
  45. shirq: interrupt-controller@0xb3000000 {
  46. compatible = "st,spear320-shirq";
  47. reg = <0xb3000000 0x1000>;
  48. interrupts = <30 28 29 1>;
  49. #interrupt-cells = <1>;
  50. interrupt-controller;
  51. };
  52. spi1: spi@a5000000 {
  53. compatible = "arm,pl022", "arm,primecell";
  54. reg = <0xa5000000 0x1000>;
  55. interrupts = <15>;
  56. interrupt-parent = <&shirq>;
  57. #address-cells = <1>;
  58. #size-cells = <0>;
  59. status = "disabled";
  60. };
  61. spi2: spi@a6000000 {
  62. compatible = "arm,pl022", "arm,primecell";
  63. reg = <0xa6000000 0x1000>;
  64. interrupts = <16>;
  65. interrupt-parent = <&shirq>;
  66. #address-cells = <1>;
  67. #size-cells = <0>;
  68. status = "disabled";
  69. };
  70. pwm: pwm@a8000000 {
  71. compatible = "st,spear-pwm";
  72. reg = <0xa8000000 0x1000>;
  73. #pwm-cells = <2>;
  74. status = "disabled";
  75. };
  76. apb {
  77. #address-cells = <1>;
  78. #size-cells = <1>;
  79. compatible = "simple-bus";
  80. ranges = <0xa0000000 0xa0000000 0x20000000
  81. 0xd0000000 0xd0000000 0x30000000>;
  82. i2c1: i2c@a7000000 {
  83. #address-cells = <1>;
  84. #size-cells = <0>;
  85. compatible = "snps,designware-i2c";
  86. reg = <0xa7000000 0x1000>;
  87. interrupts = <21>;
  88. interrupt-parent = <&shirq>;
  89. status = "disabled";
  90. };
  91. serial@a3000000 {
  92. compatible = "arm,pl011", "arm,primecell";
  93. reg = <0xa3000000 0x1000>;
  94. interrupts = <13>;
  95. interrupt-parent = <&shirq>;
  96. status = "disabled";
  97. };
  98. serial@a4000000 {
  99. compatible = "arm,pl011", "arm,primecell";
  100. reg = <0xa4000000 0x1000>;
  101. interrupts = <14>;
  102. interrupt-parent = <&shirq>;
  103. status = "disabled";
  104. };
  105. gpiopinctrl: gpio@b3000000 {
  106. compatible = "st,spear-plgpio";
  107. reg = <0xb3000000 0x1000>;
  108. regmap = <&pinmux>;
  109. #interrupt-cells = <1>;
  110. interrupt-controller;
  111. gpio-controller;
  112. #gpio-cells = <2>;
  113. gpio-ranges = <&pinmux 0 0 102>;
  114. status = "disabled";
  115. st-plgpio,ngpio = <102>;
  116. st-plgpio,enb-reg = <0x24>;
  117. st-plgpio,wdata-reg = <0x34>;
  118. st-plgpio,dir-reg = <0x44>;
  119. st-plgpio,ie-reg = <0x64>;
  120. st-plgpio,rdata-reg = <0x54>;
  121. st-plgpio,mis-reg = <0x84>;
  122. st-plgpio,eit-reg = <0x94>;
  123. };
  124. };
  125. };
  126. };