spear13xx.dtsi 7.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * DTS file for all SPEAr13xx SoCs
  4. *
  5. * Copyright 2012 Viresh Kumar <[email protected]>
  6. */
  7. / {
  8. #address-cells = <1>;
  9. #size-cells = <1>;
  10. interrupt-parent = <&gic>;
  11. cpus {
  12. #address-cells = <1>;
  13. #size-cells = <0>;
  14. cpu@0 {
  15. compatible = "arm,cortex-a9";
  16. device_type = "cpu";
  17. reg = <0>;
  18. next-level-cache = <&L2>;
  19. };
  20. cpu@1 {
  21. compatible = "arm,cortex-a9";
  22. device_type = "cpu";
  23. reg = <1>;
  24. next-level-cache = <&L2>;
  25. };
  26. };
  27. gic: interrupt-controller@ec801000 {
  28. compatible = "arm,cortex-a9-gic";
  29. interrupt-controller;
  30. #interrupt-cells = <3>;
  31. reg = < 0xec801000 0x1000 >,
  32. < 0xec800100 0x0100 >;
  33. };
  34. pmu {
  35. compatible = "arm,cortex-a9-pmu";
  36. interrupts = <0 6 0x04
  37. 0 7 0x04>;
  38. };
  39. L2: cache-controller {
  40. compatible = "arm,pl310-cache";
  41. reg = <0xed000000 0x1000>;
  42. cache-unified;
  43. cache-level = <2>;
  44. };
  45. memory {
  46. name = "memory";
  47. device_type = "memory";
  48. reg = <0 0x40000000>;
  49. };
  50. chosen {
  51. bootargs = "console=ttyAMA0,115200";
  52. };
  53. cpufreq {
  54. compatible = "st,cpufreq-spear";
  55. cpufreq_tbl = < 166000
  56. 200000
  57. 250000
  58. 300000
  59. 400000
  60. 500000
  61. 600000 >;
  62. status = "disabled";
  63. };
  64. ahb {
  65. #address-cells = <1>;
  66. #size-cells = <1>;
  67. compatible = "simple-bus";
  68. ranges = <0x50000000 0x50000000 0x10000000
  69. 0x80000000 0x80000000 0x20000000
  70. 0xb0000000 0xb0000000 0x22000000
  71. 0xd8000000 0xd8000000 0x01000000
  72. 0xe0000000 0xe0000000 0x10000000>;
  73. sdhci@b3000000 {
  74. compatible = "st,sdhci-spear";
  75. reg = <0xb3000000 0x100>;
  76. interrupts = <0 28 0x4>;
  77. status = "disabled";
  78. };
  79. cf@b2800000 {
  80. compatible = "arasan,cf-spear1340";
  81. reg = <0xb2800000 0x1000>;
  82. interrupts = <0 29 0x4>;
  83. status = "disabled";
  84. dmas = <&dwdma0 0 0 0>;
  85. dma-names = "data";
  86. };
  87. dwdma0: dma@ea800000 {
  88. compatible = "snps,dma-spear1340";
  89. reg = <0xea800000 0x1000>;
  90. interrupts = <0 19 0x4>;
  91. status = "disabled";
  92. dma-channels = <8>;
  93. #dma-cells = <3>;
  94. dma-requests = <32>;
  95. chan_allocation_order = <1>;
  96. chan_priority = <1>;
  97. block_size = <0xfff>;
  98. dma-masters = <2>;
  99. data-width = <8 8>;
  100. multi-block = <1 1 1 1 1 1 1 1>;
  101. };
  102. dma@eb000000 {
  103. compatible = "snps,dma-spear1340";
  104. reg = <0xeb000000 0x1000>;
  105. interrupts = <0 59 0x4>;
  106. status = "disabled";
  107. dma-requests = <32>;
  108. dma-channels = <8>;
  109. dma-masters = <2>;
  110. #dma-cells = <3>;
  111. chan_allocation_order = <1>;
  112. chan_priority = <1>;
  113. block_size = <0xfff>;
  114. data-width = <8 8>;
  115. multi-block = <1 1 1 1 1 1 1 1>;
  116. };
  117. fsmc: flash@b0000000 {
  118. compatible = "st,spear600-fsmc-nand";
  119. #address-cells = <1>;
  120. #size-cells = <1>;
  121. reg = <0xb0000000 0x1000 /* FSMC Register*/
  122. 0xb0800000 0x0010 /* NAND Base DATA */
  123. 0xb0820000 0x0010 /* NAND Base ADDR */
  124. 0xb0810000 0x0010>; /* NAND Base CMD */
  125. reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
  126. interrupts = <0 20 0x4
  127. 0 21 0x4
  128. 0 22 0x4
  129. 0 23 0x4>;
  130. st,mode = <2>;
  131. status = "disabled";
  132. };
  133. gmac0: eth@e2000000 {
  134. compatible = "st,spear600-gmac";
  135. reg = <0xe2000000 0x8000>;
  136. interrupts = <0 33 0x4
  137. 0 34 0x4>;
  138. interrupt-names = "macirq", "eth_wake_irq";
  139. status = "disabled";
  140. };
  141. pcm {
  142. compatible = "st,pcm-audio";
  143. #address-cells = <0>;
  144. #size-cells = <0>;
  145. status = "disabled";
  146. };
  147. smi: flash@ea000000 {
  148. compatible = "st,spear600-smi";
  149. #address-cells = <1>;
  150. #size-cells = <1>;
  151. reg = <0xea000000 0x1000>;
  152. interrupts = <0 30 0x4>;
  153. status = "disabled";
  154. };
  155. ehci@e4800000 {
  156. compatible = "st,spear600-ehci", "usb-ehci";
  157. reg = <0xe4800000 0x1000>;
  158. interrupts = <0 64 0x4>;
  159. usbh0_id = <0>;
  160. status = "disabled";
  161. };
  162. ehci@e5800000 {
  163. compatible = "st,spear600-ehci", "usb-ehci";
  164. reg = <0xe5800000 0x1000>;
  165. interrupts = <0 66 0x4>;
  166. usbh1_id = <1>;
  167. status = "disabled";
  168. };
  169. ohci@e4000000 {
  170. compatible = "st,spear600-ohci", "usb-ohci";
  171. reg = <0xe4000000 0x1000>;
  172. interrupts = <0 65 0x4>;
  173. usbh0_id = <0>;
  174. status = "disabled";
  175. };
  176. ohci@e5000000 {
  177. compatible = "st,spear600-ohci", "usb-ohci";
  178. reg = <0xe5000000 0x1000>;
  179. interrupts = <0 67 0x4>;
  180. usbh1_id = <1>;
  181. status = "disabled";
  182. };
  183. apb {
  184. #address-cells = <1>;
  185. #size-cells = <1>;
  186. compatible = "simple-bus";
  187. ranges = <0x50000000 0x50000000 0x10000000
  188. 0xb0000000 0xb0000000 0x10000000
  189. 0xd0000000 0xd0000000 0x02000000
  190. 0xd8000000 0xd8000000 0x01000000
  191. 0xe0000000 0xe0000000 0x10000000>;
  192. misc: syscon@e0700000 {
  193. compatible = "st,spear1340-misc", "syscon";
  194. reg = <0xe0700000 0x1000>;
  195. };
  196. gpio0: gpio@e0600000 {
  197. compatible = "arm,pl061", "arm,primecell";
  198. reg = <0xe0600000 0x1000>;
  199. interrupts = <0 24 0x4>;
  200. gpio-controller;
  201. #gpio-cells = <2>;
  202. interrupt-controller;
  203. #interrupt-cells = <2>;
  204. status = "disabled";
  205. };
  206. gpio1: gpio@e0680000 {
  207. compatible = "arm,pl061", "arm,primecell";
  208. reg = <0xe0680000 0x1000>;
  209. interrupts = <0 25 0x4>;
  210. gpio-controller;
  211. #gpio-cells = <2>;
  212. interrupt-controller;
  213. #interrupt-cells = <2>;
  214. status = "disabled";
  215. };
  216. kbd@e0300000 {
  217. compatible = "st,spear300-kbd";
  218. reg = <0xe0300000 0x1000>;
  219. interrupts = <0 52 0x4>;
  220. status = "disabled";
  221. };
  222. i2c0: i2c@e0280000 {
  223. #address-cells = <1>;
  224. #size-cells = <0>;
  225. compatible = "snps,designware-i2c";
  226. reg = <0xe0280000 0x1000>;
  227. interrupts = <0 41 0x4>;
  228. status = "disabled";
  229. };
  230. i2s@e0180000 {
  231. compatible = "st,designware-i2s";
  232. reg = <0xe0180000 0x1000>;
  233. interrupt-names = "play_irq", "record_irq";
  234. interrupts = <0 10 0x4
  235. 0 11 0x4 >;
  236. status = "disabled";
  237. };
  238. i2s@e0200000 {
  239. compatible = "st,designware-i2s";
  240. reg = <0xe0200000 0x1000>;
  241. interrupt-names = "play_irq", "record_irq";
  242. interrupts = <0 26 0x4
  243. 0 53 0x4>;
  244. status = "disabled";
  245. };
  246. spi0: spi@e0100000 {
  247. compatible = "arm,pl022", "arm,primecell";
  248. reg = <0xe0100000 0x1000>;
  249. #address-cells = <1>;
  250. #size-cells = <0>;
  251. interrupts = <0 31 0x4>;
  252. status = "disabled";
  253. dmas = <&dwdma0 5 0 0>,
  254. <&dwdma0 4 0 0>;
  255. dma-names = "rx", "tx";
  256. };
  257. rtc@e0580000 {
  258. compatible = "st,spear600-rtc";
  259. reg = <0xe0580000 0x1000>;
  260. interrupts = <0 36 0x4>;
  261. status = "disabled";
  262. };
  263. serial@e0000000 {
  264. compatible = "arm,pl011", "arm,primecell";
  265. reg = <0xe0000000 0x1000>;
  266. interrupts = <0 35 0x4>;
  267. status = "disabled";
  268. };
  269. adc@e0080000 {
  270. compatible = "st,spear600-adc";
  271. reg = <0xe0080000 0x1000>;
  272. interrupts = <0 12 0x4>;
  273. status = "disabled";
  274. };
  275. timer@e0380000 {
  276. compatible = "st,spear-timer";
  277. reg = <0xe0380000 0x400>;
  278. interrupts = <0 37 0x4>;
  279. };
  280. timer@ec800600 {
  281. compatible = "arm,cortex-a9-twd-timer";
  282. reg = <0xec800600 0x20>;
  283. interrupts = <1 13 0x4>;
  284. status = "disabled";
  285. };
  286. wdt@ec800620 {
  287. compatible = "arm,cortex-a9-twd-wdt";
  288. reg = <0xec800620 0x20>;
  289. status = "disabled";
  290. };
  291. thermal@e07008c4 {
  292. compatible = "st,thermal-spear1340";
  293. reg = <0xe07008c4 0x4>;
  294. thermal_flags = <0x7000>;
  295. };
  296. };
  297. };
  298. };