spear1340.dtsi 3.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * DTS file for all SPEAr1340 SoCs
  4. *
  5. * Copyright 2012 Viresh Kumar <[email protected]>
  6. */
  7. /include/ "spear13xx.dtsi"
  8. / {
  9. compatible = "st,spear1340";
  10. ahb {
  11. spics: spics@e0700000{
  12. compatible = "st,spear-spics-gpio";
  13. reg = <0xe0700000 0x1000>;
  14. st-spics,peripcfg-reg = <0x42c>;
  15. st-spics,sw-enable-bit = <21>;
  16. st-spics,cs-value-bit = <20>;
  17. st-spics,cs-enable-mask = <3>;
  18. st-spics,cs-enable-shift = <18>;
  19. gpio-controller;
  20. #gpio-cells = <2>;
  21. status = "disabled";
  22. };
  23. miphy0: miphy@eb800000 {
  24. compatible = "st,spear1340-miphy";
  25. reg = <0xeb800000 0x4000>;
  26. misc = <&misc>;
  27. #phy-cells = <1>;
  28. status = "disabled";
  29. };
  30. ahci0: ahci@b1000000 {
  31. compatible = "snps,spear-ahci";
  32. reg = <0xb1000000 0x10000>;
  33. interrupts = <0 72 0x4>;
  34. phys = <&miphy0 0>;
  35. phy-names = "sata-phy";
  36. status = "disabled";
  37. };
  38. pcie0: pcie@b1000000 {
  39. compatible = "st,spear1340-pcie", "snps,dw-pcie";
  40. reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
  41. reg-names = "dbi", "config";
  42. interrupts = <0 68 0x4>;
  43. num-lanes = <1>;
  44. phys = <&miphy0 1>;
  45. phy-names = "pcie-phy";
  46. #address-cells = <3>;
  47. #size-cells = <2>;
  48. device_type = "pci";
  49. ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
  50. 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
  51. bus-range = <0x00 0xff>;
  52. status = "disabled";
  53. };
  54. i2s-play@b2400000 {
  55. compatible = "snps,designware-i2s";
  56. reg = <0xb2400000 0x10000>;
  57. interrupt-names = "play_irq";
  58. interrupts = <0 98 0x4
  59. 0 99 0x4>;
  60. play;
  61. channel = <8>;
  62. status = "disabled";
  63. };
  64. i2s-rec@b2000000 {
  65. compatible = "snps,designware-i2s";
  66. reg = <0xb2000000 0x10000>;
  67. interrupt-names = "record_irq";
  68. interrupts = <0 100 0x4
  69. 0 101 0x4>;
  70. record;
  71. channel = <8>;
  72. status = "disabled";
  73. };
  74. pinmux: pinmux@e0700000 {
  75. compatible = "st,spear1340-pinmux";
  76. reg = <0xe0700000 0x1000>;
  77. #gpio-range-cells = <3>;
  78. };
  79. pwm: pwm@e0180000 {
  80. compatible = "st,spear13xx-pwm";
  81. reg = <0xe0180000 0x1000>;
  82. #pwm-cells = <2>;
  83. status = "disabled";
  84. };
  85. spdif-in@d0100000 {
  86. compatible = "st,spdif-in";
  87. reg = < 0xd0100000 0x20000
  88. 0xd0110000 0x10000 >;
  89. interrupts = <0 84 0x4>;
  90. status = "disabled";
  91. };
  92. spdif-out@d0000000 {
  93. compatible = "st,spdif-out";
  94. reg = <0xd0000000 0x20000>;
  95. interrupts = <0 85 0x4>;
  96. status = "disabled";
  97. };
  98. spi1: spi@5d400000 {
  99. compatible = "arm,pl022", "arm,primecell";
  100. reg = <0x5d400000 0x1000>;
  101. #address-cells = <1>;
  102. #size-cells = <0>;
  103. interrupts = <0 99 0x4>;
  104. status = "disabled";
  105. };
  106. apb {
  107. i2c1: i2c@b4000000 {
  108. #address-cells = <1>;
  109. #size-cells = <0>;
  110. compatible = "snps,designware-i2c";
  111. reg = <0xb4000000 0x1000>;
  112. interrupts = <0 104 0x4>;
  113. write-16bit;
  114. status = "disabled";
  115. };
  116. serial@b4100000 {
  117. compatible = "arm,pl011", "arm,primecell";
  118. reg = <0xb4100000 0x1000>;
  119. interrupts = <0 105 0x4>;
  120. status = "disabled";
  121. dmas = <&dwdma0 13 0 1>,
  122. <&dwdma0 12 1 0>;
  123. dma-names = "rx", "tx";
  124. };
  125. thermal@e07008c4 {
  126. st,thermal-flags = <0x2a00>;
  127. };
  128. gpiopinctrl: gpio@e2800000 {
  129. compatible = "st,spear-plgpio";
  130. reg = <0xe2800000 0x1000>;
  131. interrupts = <0 107 0x4>;
  132. #interrupt-cells = <1>;
  133. interrupt-controller;
  134. gpio-controller;
  135. #gpio-cells = <2>;
  136. gpio-ranges = <&pinmux 0 0 252>;
  137. status = "disabled";
  138. st-plgpio,ngpio = <250>;
  139. st-plgpio,wdata-reg = <0x40>;
  140. st-plgpio,dir-reg = <0x00>;
  141. st-plgpio,ie-reg = <0x80>;
  142. st-plgpio,rdata-reg = <0x20>;
  143. st-plgpio,mis-reg = <0xa0>;
  144. st-plgpio,eit-reg = <0x60>;
  145. };
  146. };
  147. };
  148. };