spear1310.dtsi 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * DTS file for all SPEAr1310 SoCs
  4. *
  5. * Copyright 2012 Viresh Kumar <[email protected]>
  6. */
  7. /include/ "spear13xx.dtsi"
  8. / {
  9. compatible = "st,spear1310";
  10. ahb {
  11. spics: spics@e0700000{
  12. compatible = "st,spear-spics-gpio";
  13. reg = <0xe0700000 0x1000>;
  14. st-spics,peripcfg-reg = <0x3b0>;
  15. st-spics,sw-enable-bit = <12>;
  16. st-spics,cs-value-bit = <11>;
  17. st-spics,cs-enable-mask = <3>;
  18. st-spics,cs-enable-shift = <8>;
  19. gpio-controller;
  20. #gpio-cells = <2>;
  21. };
  22. miphy0: miphy@eb800000 {
  23. compatible = "st,spear1310-miphy";
  24. reg = <0xeb800000 0x4000>;
  25. misc = <&misc>;
  26. phy-id = <0>;
  27. #phy-cells = <1>;
  28. status = "disabled";
  29. };
  30. miphy1: miphy@eb804000 {
  31. compatible = "st,spear1310-miphy";
  32. reg = <0xeb804000 0x4000>;
  33. misc = <&misc>;
  34. phy-id = <1>;
  35. #phy-cells = <1>;
  36. status = "disabled";
  37. };
  38. miphy2: miphy@eb808000 {
  39. compatible = "st,spear1310-miphy";
  40. reg = <0xeb808000 0x4000>;
  41. misc = <&misc>;
  42. phy-id = <2>;
  43. #phy-cells = <1>;
  44. status = "disabled";
  45. };
  46. ahci0: ahci@b1000000 {
  47. compatible = "snps,spear-ahci";
  48. reg = <0xb1000000 0x10000>;
  49. interrupts = <0 68 0x4>;
  50. phys = <&miphy0 0>;
  51. phy-names = "sata-phy";
  52. status = "disabled";
  53. };
  54. ahci1: ahci@b1800000 {
  55. compatible = "snps,spear-ahci";
  56. reg = <0xb1800000 0x10000>;
  57. interrupts = <0 69 0x4>;
  58. phys = <&miphy1 0>;
  59. phy-names = "sata-phy";
  60. status = "disabled";
  61. };
  62. ahci2: ahci@b4000000 {
  63. compatible = "snps,spear-ahci";
  64. reg = <0xb4000000 0x10000>;
  65. interrupts = <0 70 0x4>;
  66. phys = <&miphy2 0>;
  67. phy-names = "sata-phy";
  68. status = "disabled";
  69. };
  70. pcie0: pcie@b1000000 {
  71. compatible = "st,spear1340-pcie", "snps,dw-pcie";
  72. reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
  73. reg-names = "dbi", "config";
  74. interrupts = <0 68 0x4>;
  75. num-lanes = <1>;
  76. phys = <&miphy0 1>;
  77. phy-names = "pcie-phy";
  78. #address-cells = <3>;
  79. #size-cells = <2>;
  80. device_type = "pci";
  81. ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
  82. 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
  83. bus-range = <0x00 0xff>;
  84. status = "disabled";
  85. };
  86. pcie1: pcie@b1800000 {
  87. compatible = "st,spear1340-pcie", "snps,dw-pcie";
  88. reg = <0xb1800000 0x4000>, <0x90000000 0x20000>;
  89. reg-names = "dbi", "config";
  90. interrupts = <0 69 0x4>;
  91. num-lanes = <1>;
  92. phys = <&miphy1 1>;
  93. phy-names = "pcie-phy";
  94. #address-cells = <3>;
  95. #size-cells = <2>;
  96. device_type = "pci";
  97. ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
  98. 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
  99. bus-range = <0x00 0xff>;
  100. status = "disabled";
  101. };
  102. pcie2: pcie@b4000000 {
  103. compatible = "st,spear1340-pcie", "snps,dw-pcie";
  104. reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>;
  105. reg-names = "dbi", "config";
  106. interrupts = <0 70 0x4>;
  107. num-lanes = <1>;
  108. phys = <&miphy2 1>;
  109. phy-names = "pcie-phy";
  110. #address-cells = <3>;
  111. #size-cells = <2>;
  112. device_type = "pci";
  113. ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
  114. 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
  115. bus-range = <0x00 0xff>;
  116. status = "disabled";
  117. };
  118. gmac1: eth@5c400000 {
  119. compatible = "st,spear600-gmac";
  120. reg = <0x5c400000 0x8000>;
  121. interrupts = <0 95 0x4>;
  122. interrupt-names = "macirq";
  123. phy-mode = "mii";
  124. status = "disabled";
  125. };
  126. gmac2: eth@5c500000 {
  127. compatible = "st,spear600-gmac";
  128. reg = <0x5c500000 0x8000>;
  129. interrupts = <0 96 0x4>;
  130. interrupt-names = "macirq";
  131. phy-mode = "mii";
  132. status = "disabled";
  133. };
  134. gmac3: eth@5c600000 {
  135. compatible = "st,spear600-gmac";
  136. reg = <0x5c600000 0x8000>;
  137. interrupts = <0 97 0x4>;
  138. interrupt-names = "macirq";
  139. phy-mode = "rmii";
  140. status = "disabled";
  141. };
  142. gmac4: eth@5c700000 {
  143. compatible = "st,spear600-gmac";
  144. reg = <0x5c700000 0x8000>;
  145. interrupts = <0 98 0x4>;
  146. interrupt-names = "macirq";
  147. phy-mode = "rgmii";
  148. status = "disabled";
  149. };
  150. pinmux: pinmux@e0700000 {
  151. compatible = "st,spear1310-pinmux";
  152. reg = <0xe0700000 0x1000>;
  153. #gpio-range-cells = <3>;
  154. };
  155. apb {
  156. i2c1: i2c@5cd00000 {
  157. #address-cells = <1>;
  158. #size-cells = <0>;
  159. compatible = "snps,designware-i2c";
  160. reg = <0x5cd00000 0x1000>;
  161. interrupts = <0 87 0x4>;
  162. status = "disabled";
  163. };
  164. i2c2: i2c@5ce00000 {
  165. #address-cells = <1>;
  166. #size-cells = <0>;
  167. compatible = "snps,designware-i2c";
  168. reg = <0x5ce00000 0x1000>;
  169. interrupts = <0 88 0x4>;
  170. status = "disabled";
  171. };
  172. i2c3: i2c@5cf00000 {
  173. #address-cells = <1>;
  174. #size-cells = <0>;
  175. compatible = "snps,designware-i2c";
  176. reg = <0x5cf00000 0x1000>;
  177. interrupts = <0 89 0x4>;
  178. status = "disabled";
  179. };
  180. i2c4: i2c@5d000000 {
  181. #address-cells = <1>;
  182. #size-cells = <0>;
  183. compatible = "snps,designware-i2c";
  184. reg = <0x5d000000 0x1000>;
  185. interrupts = <0 90 0x4>;
  186. status = "disabled";
  187. };
  188. i2c5: i2c@5d100000 {
  189. #address-cells = <1>;
  190. #size-cells = <0>;
  191. compatible = "snps,designware-i2c";
  192. reg = <0x5d100000 0x1000>;
  193. interrupts = <0 91 0x4>;
  194. status = "disabled";
  195. };
  196. i2c6: i2c@5d200000 {
  197. #address-cells = <1>;
  198. #size-cells = <0>;
  199. compatible = "snps,designware-i2c";
  200. reg = <0x5d200000 0x1000>;
  201. interrupts = <0 92 0x4>;
  202. status = "disabled";
  203. };
  204. i2c7: i2c@5d300000 {
  205. #address-cells = <1>;
  206. #size-cells = <0>;
  207. compatible = "snps,designware-i2c";
  208. reg = <0x5d300000 0x1000>;
  209. interrupts = <0 93 0x4>;
  210. status = "disabled";
  211. };
  212. spi1: spi@5d400000 {
  213. compatible = "arm,pl022", "arm,primecell";
  214. reg = <0x5d400000 0x1000>;
  215. interrupts = <0 99 0x4>;
  216. #address-cells = <1>;
  217. #size-cells = <0>;
  218. status = "disabled";
  219. };
  220. serial@5c800000 {
  221. compatible = "arm,pl011", "arm,primecell";
  222. reg = <0x5c800000 0x1000>;
  223. interrupts = <0 82 0x4>;
  224. status = "disabled";
  225. };
  226. serial@5c900000 {
  227. compatible = "arm,pl011", "arm,primecell";
  228. reg = <0x5c900000 0x1000>;
  229. interrupts = <0 83 0x4>;
  230. status = "disabled";
  231. };
  232. serial@5ca00000 {
  233. compatible = "arm,pl011", "arm,primecell";
  234. reg = <0x5ca00000 0x1000>;
  235. interrupts = <0 84 0x4>;
  236. status = "disabled";
  237. };
  238. serial@5cb00000 {
  239. compatible = "arm,pl011", "arm,primecell";
  240. reg = <0x5cb00000 0x1000>;
  241. interrupts = <0 85 0x4>;
  242. status = "disabled";
  243. };
  244. serial@5cc00000 {
  245. compatible = "arm,pl011", "arm,primecell";
  246. reg = <0x5cc00000 0x1000>;
  247. interrupts = <0 86 0x4>;
  248. status = "disabled";
  249. };
  250. thermal@e07008c4 {
  251. st,thermal-flags = <0x7000>;
  252. };
  253. gpiopinctrl: gpio@d8400000 {
  254. compatible = "st,spear-plgpio";
  255. reg = <0xd8400000 0x1000>;
  256. interrupts = <0 100 0x4>;
  257. #interrupt-cells = <1>;
  258. interrupt-controller;
  259. gpio-controller;
  260. #gpio-cells = <2>;
  261. gpio-ranges = <&pinmux 0 0 246>;
  262. status = "disabled";
  263. st-plgpio,ngpio = <246>;
  264. st-plgpio,enb-reg = <0xd0>;
  265. st-plgpio,wdata-reg = <0x90>;
  266. st-plgpio,dir-reg = <0xb0>;
  267. st-plgpio,ie-reg = <0x30>;
  268. st-plgpio,rdata-reg = <0x70>;
  269. st-plgpio,mis-reg = <0x10>;
  270. st-plgpio,eit-reg = <0x50>;
  271. };
  272. };
  273. };
  274. };