socfpga_vt.dts 1.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Altera Corporation <www.altera.com>
  4. */
  5. /dts-v1/;
  6. #include "socfpga.dtsi"
  7. / {
  8. model = "Altera SOCFPGA VT";
  9. compatible = "altr,socfpga-vt", "altr,socfpga";
  10. chosen {
  11. bootargs = "console=ttyS0,57600";
  12. };
  13. memory@0 {
  14. name = "memory";
  15. device_type = "memory";
  16. reg = <0x0 0x40000000>; /* 1 GB */
  17. };
  18. soc {
  19. clkmgr@ffd04000 {
  20. clocks {
  21. osc1 {
  22. clock-frequency = <10000000>;
  23. };
  24. };
  25. };
  26. dwmmc0@ff704000 {
  27. broken-cd;
  28. bus-width = <4>;
  29. cap-mmc-highspeed;
  30. cap-sd-highspeed;
  31. };
  32. ethernet@ff700000 {
  33. phy-mode = "gmii";
  34. status = "okay";
  35. };
  36. timer0@ffc08000 {
  37. clock-frequency = <7000000>;
  38. };
  39. timer1@ffc09000 {
  40. clock-frequency = <7000000>;
  41. };
  42. timer2@ffd00000 {
  43. clock-frequency = <7000000>;
  44. };
  45. timer3@ffd01000 {
  46. clock-frequency = <7000000>;
  47. };
  48. serial0@ffc02000 {
  49. clock-frequency = <7372800>;
  50. };
  51. serial1@ffc03000 {
  52. clock-frequency = <7372800>;
  53. };
  54. sysmgr@ffd08000 {
  55. cpu1-start-addr = <0xffd08010>;
  56. };
  57. };
  58. };
  59. &gmac0 {
  60. status = "okay";
  61. phy-mode = "gmii";
  62. };