socfpga_arria5.dtsi 548 B

123456789101112131415161718192021222324252627282930313233343536
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2013 Altera Corporation <www.altera.com>
  4. */
  5. /dts-v1/;
  6. /* First 4KB has trampoline code for secondary cores. */
  7. /memreserve/ 0x00000000 0x0001000;
  8. #include "socfpga.dtsi"
  9. / {
  10. soc {
  11. clkmgr@ffd04000 {
  12. clocks {
  13. osc1 {
  14. clock-frequency = <25000000>;
  15. };
  16. };
  17. };
  18. mmc0: dwmmc0@ff704000 {
  19. broken-cd;
  20. bus-width = <4>;
  21. cap-mmc-highspeed;
  22. cap-sd-highspeed;
  23. };
  24. sysmgr@ffd08000 {
  25. cpu1-start-addr = <0xffd080c4>;
  26. };
  27. };
  28. };
  29. &watchdog0 {
  30. status = "okay";
  31. };