rk3288-veyron-sdmmc.dtsi 2.0 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Google Veyron (and derivatives) fragment for sdmmc cards
  4. *
  5. * Copyright 2015 Google, Inc
  6. */
  7. &io_domains {
  8. sdcard-supply = <&vccio_sd>;
  9. };
  10. &pinctrl {
  11. sdmmc {
  12. /*
  13. * We run sdmmc at max speed; bump up drive strength.
  14. * We also have external pulls, so disable the internal ones.
  15. */
  16. sdmmc_bus4: sdmmc-bus4 {
  17. rockchip,pins = <6 RK_PC0 1 &pcfg_pull_none_drv_8ma>,
  18. <6 RK_PC1 1 &pcfg_pull_none_drv_8ma>,
  19. <6 RK_PC2 1 &pcfg_pull_none_drv_8ma>,
  20. <6 RK_PC3 1 &pcfg_pull_none_drv_8ma>;
  21. };
  22. sdmmc_clk: sdmmc-clk {
  23. rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>;
  24. };
  25. sdmmc_cmd: sdmmc-cmd {
  26. rockchip,pins = <6 RK_PC5 1 &pcfg_pull_none_drv_8ma>;
  27. };
  28. /*
  29. * Builtin CD line is hooked to ground to prevent JTAG at boot
  30. * (and also to get the voltage rail correct).
  31. * Configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't
  32. * think there's a card inserted
  33. */
  34. sdmmc_cd_disabled: sdmmc-cd-disabled {
  35. rockchip,pins = <6 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
  36. };
  37. /* This is where we actually hook up CD */
  38. sdmmc_cd_pin: sdmmc-cd-pin {
  39. rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
  40. };
  41. };
  42. };
  43. &rk808 {
  44. vcc9-supply = <&vcc_5v>;
  45. regulators {
  46. vccio_sd: LDO_REG4 {
  47. regulator-name = "vccio_sd";
  48. regulator-min-microvolt = <1800000>;
  49. regulator-max-microvolt = <3300000>;
  50. regulator-state-mem {
  51. regulator-off-in-suspend;
  52. };
  53. };
  54. vcc33_sd: LDO_REG5 {
  55. regulator-name = "vcc33_sd";
  56. regulator-min-microvolt = <3300000>;
  57. regulator-max-microvolt = <3300000>;
  58. regulator-state-mem {
  59. regulator-off-in-suspend;
  60. };
  61. };
  62. };
  63. };
  64. &sdmmc {
  65. status = "okay";
  66. bus-width = <4>;
  67. cap-mmc-highspeed;
  68. cap-sd-highspeed;
  69. card-detect-delay = <200>;
  70. cd-gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>;
  71. rockchip,default-sample-phase = <90>;
  72. sd-uhs-sdr12;
  73. sd-uhs-sdr25;
  74. sd-uhs-sdr50;
  75. sd-uhs-sdr104;
  76. vmmc-supply = <&vcc33_sd>;
  77. vqmmc-supply = <&vccio_sd>;
  78. };