rk3288-veyron-minnie.dts 6.9 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Google Veyron Minnie Rev 0+ board device tree source
  4. *
  5. * Copyright 2015 Google, Inc
  6. */
  7. /dts-v1/;
  8. #include "rk3288-veyron-chromebook.dtsi"
  9. #include "rk3288-veyron-broadcom-bluetooth.dtsi"
  10. / {
  11. model = "Google Minnie";
  12. compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
  13. "google,veyron-minnie-rev2", "google,veyron-minnie-rev1",
  14. "google,veyron-minnie-rev0", "google,veyron-minnie",
  15. "google,veyron", "rockchip,rk3288";
  16. volume_buttons: volume-buttons {
  17. compatible = "gpio-keys";
  18. pinctrl-names = "default";
  19. pinctrl-0 = <&volum_down_l &volum_up_l>;
  20. key-volum-down {
  21. label = "Volum_down";
  22. gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>;
  23. linux,code = <KEY_VOLUMEDOWN>;
  24. debounce-interval = <100>;
  25. };
  26. key-volum-up {
  27. label = "Volum_up";
  28. gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>;
  29. linux,code = <KEY_VOLUMEUP>;
  30. debounce-interval = <100>;
  31. };
  32. };
  33. };
  34. &backlight {
  35. /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */
  36. brightness-levels = <3 255>;
  37. num-interpolated-steps = <252>;
  38. };
  39. &i2c_tunnel {
  40. battery: bq27500@55 {
  41. compatible = "ti,bq27500";
  42. reg = <0x55>;
  43. };
  44. };
  45. &i2c3 {
  46. status = "okay";
  47. clock-frequency = <400000>;
  48. i2c-scl-falling-time-ns = <50>;
  49. i2c-scl-rising-time-ns = <300>;
  50. touchscreen@10 {
  51. compatible = "elan,ekth3500";
  52. reg = <0x10>;
  53. interrupt-parent = <&gpio2>;
  54. interrupts = <RK_PB6 IRQ_TYPE_EDGE_FALLING>;
  55. pinctrl-names = "default";
  56. pinctrl-0 = <&touch_int &touch_rst>;
  57. reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
  58. vcc33-supply = <&vcc33_touch>;
  59. vccio-supply = <&vcc33_touch>;
  60. };
  61. };
  62. &panel {
  63. compatible = "auo,b101ean01";
  64. /delete-node/ panel-timing;
  65. panel-timing {
  66. clock-frequency = <66666667>;
  67. hactive = <1280>;
  68. hfront-porch = <18>;
  69. hback-porch = <21>;
  70. hsync-len = <32>;
  71. vactive = <800>;
  72. vfront-porch = <4>;
  73. vback-porch = <8>;
  74. vsync-len = <18>;
  75. };
  76. };
  77. &rk808 {
  78. pinctrl-names = "default";
  79. pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
  80. regulators {
  81. vcc33_touch: LDO_REG2 {
  82. regulator-min-microvolt = <3300000>;
  83. regulator-max-microvolt = <3300000>;
  84. regulator-name = "vcc33_touch";
  85. regulator-state-mem {
  86. regulator-off-in-suspend;
  87. };
  88. };
  89. vcc5v_touch: SWITCH_REG2 {
  90. regulator-name = "vcc5v_touch";
  91. regulator-state-mem {
  92. regulator-off-in-suspend;
  93. };
  94. };
  95. };
  96. };
  97. &sdmmc {
  98. disable-wp;
  99. pinctrl-names = "default";
  100. pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
  101. &sdmmc_bus4>;
  102. };
  103. &vcc_5v {
  104. enable-active-high;
  105. gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
  106. pinctrl-names = "default";
  107. pinctrl-0 = <&drv_5v>;
  108. };
  109. &vcc50_hdmi {
  110. enable-active-high;
  111. gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
  112. pinctrl-names = "default";
  113. pinctrl-0 = <&vcc50_hdmi_en>;
  114. };
  115. &gpio0 {
  116. gpio-line-names = "PMIC_SLEEP_AP",
  117. "DDRIO_PWROFF",
  118. "DDRIO_RETEN",
  119. "TS3A227E_INT_L",
  120. "PMIC_INT_L",
  121. "PWR_KEY_L",
  122. "AP_LID_INT_L",
  123. "EC_IN_RW",
  124. "AC_PRESENT_AP",
  125. /*
  126. * RECOVERY_SW_L is Chrome OS ABI. Schematics call
  127. * it REC_MODE_L.
  128. */
  129. "RECOVERY_SW_L",
  130. "OTP_OUT",
  131. "HOST1_PWR_EN",
  132. "USBOTG_PWREN_H",
  133. "AP_WARM_RESET_H",
  134. "nFALUT2",
  135. "I2C0_SDA_PMIC",
  136. "I2C0_SCL_PMIC",
  137. "SUSPEND_L",
  138. "USB_INT";
  139. };
  140. &gpio2 {
  141. gpio-line-names = "CONFIG0",
  142. "CONFIG1",
  143. "CONFIG2",
  144. "",
  145. "",
  146. "",
  147. "",
  148. "CONFIG3",
  149. "PROCHOT#",
  150. "EMMC_RST_L",
  151. "",
  152. "",
  153. "BL_PWR_EN",
  154. "AVDD_1V8_DISP_EN",
  155. "TOUCH_INT",
  156. "TOUCH_RST",
  157. "I2C3_SCL_TP",
  158. "I2C3_SDA_TP";
  159. };
  160. &gpio3 {
  161. gpio-line-names = "FLASH0_D0",
  162. "FLASH0_D1",
  163. "FLASH0_D2",
  164. "FLASH0_D3",
  165. "FLASH0_D4",
  166. "FLASH0_D5",
  167. "FLASH0_D6",
  168. "FLASH0_D7",
  169. "",
  170. "",
  171. "",
  172. "",
  173. "",
  174. "",
  175. "",
  176. "",
  177. "FLASH0_CS2/EMMC_CMD",
  178. "",
  179. "FLASH0_DQS/EMMC_CLKO";
  180. };
  181. &gpio4 {
  182. gpio-line-names = "",
  183. "",
  184. "",
  185. "",
  186. "",
  187. "",
  188. "",
  189. "",
  190. "",
  191. "",
  192. "",
  193. "",
  194. "",
  195. "",
  196. "",
  197. "",
  198. "UART0_RXD",
  199. "UART0_TXD",
  200. "UART0_CTS",
  201. "UART0_RTS",
  202. "SDIO0_D0",
  203. "SDIO0_D1",
  204. "SDIO0_D2",
  205. "SDIO0_D3",
  206. "SDIO0_CMD",
  207. "SDIO0_CLK",
  208. "dev_wake",
  209. "",
  210. "WIFI_ENABLE_H",
  211. "BT_ENABLE_L",
  212. "WIFI_HOST_WAKE",
  213. "BT_HOST_WAKE";
  214. };
  215. &gpio5 {
  216. gpio-line-names = "",
  217. "",
  218. "",
  219. "",
  220. "",
  221. "",
  222. "",
  223. "",
  224. "",
  225. "",
  226. "Volum_Up#",
  227. "Volum_Down#",
  228. "SPI0_CLK",
  229. "SPI0_CS0",
  230. "SPI0_TXD",
  231. "SPI0_RXD",
  232. "",
  233. "",
  234. "",
  235. "VCC50_HDMI_EN";
  236. };
  237. &gpio6 {
  238. gpio-line-names = "I2S0_SCLK",
  239. "I2S0_LRCK_RX",
  240. "I2S0_LRCK_TX",
  241. "I2S0_SDI",
  242. "I2S0_SDO0",
  243. "HP_DET_H",
  244. "",
  245. "INT_CODEC",
  246. "I2S0_CLK",
  247. "I2C2_SDA",
  248. "I2C2_SCL",
  249. "MICDET",
  250. "",
  251. "",
  252. "",
  253. "",
  254. "SDMMC_D0",
  255. "SDMMC_D1",
  256. "SDMMC_D2",
  257. "SDMMC_D3",
  258. "SDMMC_CLK",
  259. "SDMMC_CMD";
  260. };
  261. &gpio7 {
  262. gpio-line-names = "LCDC_BL",
  263. "PWM_LOG",
  264. "BL_EN",
  265. "TRACKPAD_INT",
  266. "TPM_INT_H",
  267. "SDMMC_DET_L",
  268. /*
  269. * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
  270. * it FW_WP_AP.
  271. */
  272. "AP_FLASH_WP_L",
  273. "EC_INT",
  274. "CPU_NMI",
  275. "DVS_OK",
  276. "SDMMC_WP",
  277. "EDP_HPD",
  278. "DVS1",
  279. "nFALUT1",
  280. "LCD_EN",
  281. "DVS2",
  282. "VCC5V_GOOD_H",
  283. "I2C4_SDA_TP",
  284. "I2C4_SCL_TP",
  285. "I2C5_SDA_HDMI",
  286. "I2C5_SCL_HDMI",
  287. "5V_DRV",
  288. "UART2_RXD",
  289. "UART2_TXD";
  290. };
  291. &gpio8 {
  292. gpio-line-names = "RAM_ID0",
  293. "RAM_ID1",
  294. "RAM_ID2",
  295. "RAM_ID3",
  296. "I2C1_SDA_TPM",
  297. "I2C1_SCL_TPM",
  298. "SPI2_CLK",
  299. "SPI2_CS0",
  300. "SPI2_RXD",
  301. "SPI2_TXD";
  302. };
  303. &pinctrl {
  304. pinctrl-names = "default", "sleep";
  305. pinctrl-0 = <
  306. /* Common for sleep and wake, but no owners */
  307. &ddr0_retention
  308. &ddrio_pwroff
  309. &global_pwroff
  310. /* Wake only */
  311. &suspend_l_wake
  312. >;
  313. pinctrl-1 = <
  314. /* Common for sleep and wake, but no owners */
  315. &ddr0_retention
  316. &ddrio_pwroff
  317. &global_pwroff
  318. /* Sleep only */
  319. &suspend_l_sleep
  320. >;
  321. buck-5v {
  322. drv_5v: drv-5v {
  323. rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
  324. };
  325. };
  326. buttons {
  327. volum_down_l: volum-down-l {
  328. rockchip,pins = <5 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
  329. };
  330. volum_up_l: volum-up-l {
  331. rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
  332. };
  333. };
  334. hdmi {
  335. vcc50_hdmi_en: vcc50-hdmi-en {
  336. rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
  337. };
  338. };
  339. pmic {
  340. dvs_1: dvs-1 {
  341. rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
  342. };
  343. dvs_2: dvs-2 {
  344. rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
  345. };
  346. };
  347. prochot {
  348. gpio_prochot: gpio-prochot {
  349. rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
  350. };
  351. };
  352. touchscreen {
  353. touch_int: touch-int {
  354. rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
  355. };
  356. touch_rst: touch-rst {
  357. rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
  358. };
  359. };
  360. };