rk3288-veyron-edp.dtsi 2.7 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Google Veyron (and derivatives) fragment for the edp displays
  4. *
  5. * Copyright 2019 Google LLC
  6. */
  7. / {
  8. backlight_regulator: backlight-regulator {
  9. compatible = "regulator-fixed";
  10. enable-active-high;
  11. gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
  12. pinctrl-names = "default";
  13. pinctrl-0 = <&bl_pwr_en>;
  14. regulator-name = "backlight_regulator";
  15. vin-supply = <&vcc33_sys>;
  16. startup-delay-us = <15000>;
  17. };
  18. panel_regulator: panel-regulator {
  19. compatible = "regulator-fixed";
  20. enable-active-high;
  21. gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
  22. pinctrl-names = "default";
  23. pinctrl-0 = <&lcd_enable_h>;
  24. regulator-name = "panel_regulator";
  25. vin-supply = <&vcc33_sys>;
  26. };
  27. vcc18_lcd: vcc18-lcd {
  28. compatible = "regulator-fixed";
  29. enable-active-high;
  30. gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
  31. pinctrl-names = "default";
  32. pinctrl-0 = <&avdd_1v8_disp_en>;
  33. regulator-name = "vcc18_lcd";
  34. regulator-always-on;
  35. regulator-boot-on;
  36. vin-supply = <&vcc18_wl>;
  37. };
  38. backlight: backlight {
  39. compatible = "pwm-backlight";
  40. brightness-levels = <0 255>;
  41. num-interpolated-steps = <255>;
  42. default-brightness-level = <128>;
  43. enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
  44. pinctrl-names = "default";
  45. pinctrl-0 = <&bl_en>;
  46. pwms = <&pwm0 0 1000000 0>;
  47. post-pwm-on-delay-ms = <10>;
  48. pwm-off-delay-ms = <10>;
  49. power-supply = <&backlight_regulator>;
  50. };
  51. panel: panel {
  52. compatible = "innolux,n116bge";
  53. status = "okay";
  54. power-supply = <&panel_regulator>;
  55. backlight = <&backlight>;
  56. panel-timing {
  57. clock-frequency = <74250000>;
  58. hactive = <1366>;
  59. hfront-porch = <136>;
  60. hback-porch = <60>;
  61. hsync-len = <30>;
  62. hsync-active = <0>;
  63. vactive = <768>;
  64. vfront-porch = <8>;
  65. vback-porch = <12>;
  66. vsync-len = <12>;
  67. vsync-active = <0>;
  68. };
  69. ports {
  70. panel_in: port {
  71. panel_in_edp: endpoint {
  72. remote-endpoint = <&edp_out_panel>;
  73. };
  74. };
  75. };
  76. };
  77. };
  78. &edp {
  79. status = "okay";
  80. pinctrl-names = "default";
  81. pinctrl-0 = <&edp_hpd>;
  82. ports {
  83. edp_out: port@1 {
  84. reg = <1>;
  85. #address-cells = <1>;
  86. #size-cells = <0>;
  87. edp_out_panel: endpoint@0 {
  88. reg = <0>;
  89. remote-endpoint = <&panel_in_edp>;
  90. };
  91. };
  92. };
  93. };
  94. &edp_phy {
  95. status = "okay";
  96. };
  97. &pwm0 {
  98. status = "okay";
  99. };
  100. &vopl {
  101. status = "okay";
  102. };
  103. &vopl_mmu {
  104. status = "okay";
  105. };
  106. &pinctrl {
  107. backlight {
  108. bl_pwr_en: bl_pwr_en {
  109. rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
  110. };
  111. bl_en: bl-en {
  112. rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
  113. };
  114. };
  115. lcd {
  116. lcd_enable_h: lcd-en {
  117. rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
  118. };
  119. avdd_1v8_disp_en: avdd-1v8-disp-en {
  120. rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
  121. };
  122. };
  123. };