r8a7779-marzen.dts 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for the R-Car H1 (R8A77790) Marzen board
  4. *
  5. * Copyright (C) 2013 Renesas Solutions Corp.
  6. * Copyright (C) 2013 Simon Horman
  7. */
  8. /dts-v1/;
  9. #include "r8a7779.dtsi"
  10. #include <dt-bindings/gpio/gpio.h>
  11. #include <dt-bindings/interrupt-controller/irq.h>
  12. / {
  13. model = "marzen";
  14. compatible = "renesas,marzen", "renesas,r8a7779";
  15. aliases {
  16. serial0 = &scif2;
  17. serial1 = &scif4;
  18. };
  19. chosen {
  20. bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
  21. stdout-path = "serial0:115200n8";
  22. };
  23. memory@60000000 {
  24. device_type = "memory";
  25. reg = <0x60000000 0x40000000>;
  26. };
  27. fixedregulator3v3: regulator-3v3 {
  28. compatible = "regulator-fixed";
  29. regulator-name = "fixed-3.3V";
  30. regulator-min-microvolt = <3300000>;
  31. regulator-max-microvolt = <3300000>;
  32. regulator-boot-on;
  33. regulator-always-on;
  34. };
  35. vccq_sdhi0: regulator-vccq-sdhi0 {
  36. compatible = "regulator-gpio";
  37. regulator-name = "SDHI0 VccQ";
  38. regulator-min-microvolt = <1800000>;
  39. regulator-max-microvolt = <3300000>;
  40. gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
  41. gpios-states = <1>;
  42. states = <3300000 1>, <1800000 0>;
  43. };
  44. ethernet@18000000 {
  45. compatible = "smsc,lan89218", "smsc,lan9115";
  46. reg = <0x18000000 0x100>;
  47. pinctrl-0 = <&ethernet_pins>;
  48. pinctrl-names = "default";
  49. phy-mode = "mii";
  50. interrupt-parent = <&irqpin0>;
  51. interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
  52. smsc,irq-push-pull;
  53. reg-io-width = <4>;
  54. vddvario-supply = <&fixedregulator3v3>;
  55. vdd33a-supply = <&fixedregulator3v3>;
  56. };
  57. leds {
  58. compatible = "gpio-leds";
  59. led2 {
  60. gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
  61. };
  62. led3 {
  63. gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
  64. };
  65. led4 {
  66. gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
  67. };
  68. };
  69. vga-encoder {
  70. compatible = "adi,adv7123";
  71. ports {
  72. #address-cells = <1>;
  73. #size-cells = <0>;
  74. port@0 {
  75. reg = <0>;
  76. vga_enc_in: endpoint {
  77. remote-endpoint = <&du_out_rgb0>;
  78. };
  79. };
  80. port@1 {
  81. reg = <1>;
  82. vga_enc_out: endpoint {
  83. remote-endpoint = <&vga_in>;
  84. };
  85. };
  86. };
  87. };
  88. vga {
  89. compatible = "vga-connector";
  90. port {
  91. vga_in: endpoint {
  92. remote-endpoint = <&vga_enc_out>;
  93. };
  94. };
  95. };
  96. lvds-encoder {
  97. compatible = "thine,thc63lvdm83d";
  98. ports {
  99. #address-cells = <1>;
  100. #size-cells = <0>;
  101. port@0 {
  102. reg = <0>;
  103. lvds_enc_in: endpoint {
  104. remote-endpoint = <&du_out_rgb1>;
  105. };
  106. };
  107. port@1 {
  108. reg = <1>;
  109. lvds_connector: endpoint {
  110. };
  111. };
  112. };
  113. };
  114. x3_clk: x3-clock {
  115. compatible = "fixed-clock";
  116. #clock-cells = <0>;
  117. clock-frequency = <65000000>;
  118. };
  119. };
  120. &du {
  121. pinctrl-0 = <&du_pins>;
  122. pinctrl-names = "default";
  123. status = "okay";
  124. clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>;
  125. clock-names = "du.0", "dclkin.0";
  126. ports {
  127. port@0 {
  128. endpoint {
  129. remote-endpoint = <&vga_enc_in>;
  130. };
  131. };
  132. port@1 {
  133. endpoint {
  134. remote-endpoint = <&lvds_enc_in>;
  135. };
  136. };
  137. };
  138. };
  139. &irqpin0 {
  140. status = "okay";
  141. };
  142. &extal_clk {
  143. clock-frequency = <31250000>;
  144. };
  145. &tmu0 {
  146. status = "okay";
  147. };
  148. &pfc {
  149. pinctrl-0 = <&scif_clk_pins>;
  150. pinctrl-names = "default";
  151. du_pins: du {
  152. du0 {
  153. groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0", "du0_clk_in";
  154. function = "du0";
  155. };
  156. du1 {
  157. groups = "du1_rgb666", "du1_sync_1", "du1_clk_out";
  158. function = "du1";
  159. };
  160. };
  161. scif_clk_pins: scif_clk {
  162. groups = "scif_clk_b";
  163. function = "scif_clk";
  164. };
  165. ethernet_pins: ethernet {
  166. intc {
  167. groups = "intc_irq1_b";
  168. function = "intc";
  169. };
  170. lbsc {
  171. groups = "lbsc_ex_cs0";
  172. function = "lbsc";
  173. };
  174. };
  175. scif2_pins: scif2 {
  176. groups = "scif2_data_c";
  177. function = "scif2";
  178. };
  179. scif4_pins: scif4 {
  180. groups = "scif4_data";
  181. function = "scif4";
  182. };
  183. sdhi0_pins: sd0 {
  184. groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
  185. function = "sdhi0";
  186. };
  187. hspi0_pins: hspi0 {
  188. groups = "hspi0";
  189. function = "hspi0";
  190. };
  191. };
  192. &sata {
  193. status = "okay";
  194. };
  195. &scif2 {
  196. pinctrl-0 = <&scif2_pins>;
  197. pinctrl-names = "default";
  198. status = "okay";
  199. };
  200. &scif4 {
  201. pinctrl-0 = <&scif4_pins>;
  202. pinctrl-names = "default";
  203. status = "okay";
  204. };
  205. &scif_clk {
  206. clock-frequency = <14745600>;
  207. };
  208. &sdhi0 {
  209. pinctrl-0 = <&sdhi0_pins>;
  210. pinctrl-names = "default";
  211. vmmc-supply = <&fixedregulator3v3>;
  212. vqmmc-supply = <&vccq_sdhi0>;
  213. bus-width = <4>;
  214. status = "okay";
  215. };
  216. &hspi0 {
  217. pinctrl-0 = <&hspi0_pins>;
  218. pinctrl-names = "default";
  219. status = "okay";
  220. };