r8a77470.dtsi 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for the r8a77470 SoC
  4. *
  5. * Copyright (C) 2018 Renesas Electronics Corp.
  6. */
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. #include <dt-bindings/interrupt-controller/arm-gic.h>
  9. #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
  10. #include <dt-bindings/power/r8a77470-sysc.h>
  11. / {
  12. compatible = "renesas,r8a77470";
  13. #address-cells = <2>;
  14. #size-cells = <2>;
  15. aliases {
  16. i2c0 = &i2c0;
  17. i2c1 = &i2c1;
  18. i2c2 = &i2c2;
  19. i2c3 = &i2c3;
  20. i2c4 = &i2c4;
  21. };
  22. cpus {
  23. #address-cells = <1>;
  24. #size-cells = <0>;
  25. cpu0: cpu@0 {
  26. device_type = "cpu";
  27. compatible = "arm,cortex-a7";
  28. reg = <0>;
  29. clock-frequency = <1000000000>;
  30. clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
  31. power-domains = <&sysc R8A77470_PD_CA7_CPU0>;
  32. enable-method = "renesas,apmu";
  33. next-level-cache = <&L2_CA7>;
  34. };
  35. cpu1: cpu@1 {
  36. device_type = "cpu";
  37. compatible = "arm,cortex-a7";
  38. reg = <1>;
  39. clock-frequency = <1000000000>;
  40. clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
  41. power-domains = <&sysc R8A77470_PD_CA7_CPU1>;
  42. enable-method = "renesas,apmu";
  43. next-level-cache = <&L2_CA7>;
  44. };
  45. L2_CA7: cache-controller-0 {
  46. compatible = "cache";
  47. cache-unified;
  48. cache-level = <2>;
  49. power-domains = <&sysc R8A77470_PD_CA7_SCU>;
  50. };
  51. };
  52. /* External root clock */
  53. extal_clk: extal {
  54. compatible = "fixed-clock";
  55. #clock-cells = <0>;
  56. /* This value must be overridden by the board. */
  57. clock-frequency = <0>;
  58. };
  59. pmu {
  60. compatible = "arm,cortex-a7-pmu";
  61. interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
  62. <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  63. interrupt-affinity = <&cpu0>, <&cpu1>;
  64. };
  65. /* External SCIF clock */
  66. scif_clk: scif {
  67. compatible = "fixed-clock";
  68. #clock-cells = <0>;
  69. /* This value must be overridden by the board. */
  70. clock-frequency = <0>;
  71. };
  72. soc {
  73. compatible = "simple-bus";
  74. interrupt-parent = <&gic>;
  75. #address-cells = <2>;
  76. #size-cells = <2>;
  77. ranges;
  78. rwdt: watchdog@e6020000 {
  79. compatible = "renesas,r8a77470-wdt",
  80. "renesas,rcar-gen2-wdt";
  81. reg = <0 0xe6020000 0 0x0c>;
  82. interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
  83. clocks = <&cpg CPG_MOD 402>;
  84. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  85. resets = <&cpg 402>;
  86. status = "disabled";
  87. };
  88. gpio0: gpio@e6050000 {
  89. compatible = "renesas,gpio-r8a77470",
  90. "renesas,rcar-gen2-gpio";
  91. reg = <0 0xe6050000 0 0x50>;
  92. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  93. #gpio-cells = <2>;
  94. gpio-controller;
  95. gpio-ranges = <&pfc 0 0 23>;
  96. #interrupt-cells = <2>;
  97. interrupt-controller;
  98. clocks = <&cpg CPG_MOD 912>;
  99. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  100. resets = <&cpg 912>;
  101. };
  102. gpio1: gpio@e6051000 {
  103. compatible = "renesas,gpio-r8a77470",
  104. "renesas,rcar-gen2-gpio";
  105. reg = <0 0xe6051000 0 0x50>;
  106. interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  107. #gpio-cells = <2>;
  108. gpio-controller;
  109. gpio-ranges = <&pfc 0 32 23>;
  110. #interrupt-cells = <2>;
  111. interrupt-controller;
  112. clocks = <&cpg CPG_MOD 911>;
  113. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  114. resets = <&cpg 911>;
  115. };
  116. gpio2: gpio@e6052000 {
  117. compatible = "renesas,gpio-r8a77470",
  118. "renesas,rcar-gen2-gpio";
  119. reg = <0 0xe6052000 0 0x50>;
  120. interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  121. #gpio-cells = <2>;
  122. gpio-controller;
  123. gpio-ranges = <&pfc 0 64 32>;
  124. #interrupt-cells = <2>;
  125. interrupt-controller;
  126. clocks = <&cpg CPG_MOD 910>;
  127. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  128. resets = <&cpg 910>;
  129. };
  130. gpio3: gpio@e6053000 {
  131. compatible = "renesas,gpio-r8a77470",
  132. "renesas,rcar-gen2-gpio";
  133. reg = <0 0xe6053000 0 0x50>;
  134. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  135. #gpio-cells = <2>;
  136. gpio-controller;
  137. gpio-ranges = <&pfc 0 96 30>;
  138. gpio-reserved-ranges = <17 10>;
  139. #interrupt-cells = <2>;
  140. interrupt-controller;
  141. clocks = <&cpg CPG_MOD 909>;
  142. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  143. resets = <&cpg 909>;
  144. };
  145. gpio4: gpio@e6054000 {
  146. compatible = "renesas,gpio-r8a77470",
  147. "renesas,rcar-gen2-gpio";
  148. reg = <0 0xe6054000 0 0x50>;
  149. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  150. #gpio-cells = <2>;
  151. gpio-controller;
  152. gpio-ranges = <&pfc 0 128 26>;
  153. #interrupt-cells = <2>;
  154. interrupt-controller;
  155. clocks = <&cpg CPG_MOD 908>;
  156. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  157. resets = <&cpg 908>;
  158. };
  159. gpio5: gpio@e6055000 {
  160. compatible = "renesas,gpio-r8a77470",
  161. "renesas,rcar-gen2-gpio";
  162. reg = <0 0xe6055000 0 0x50>;
  163. interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  164. #gpio-cells = <2>;
  165. gpio-controller;
  166. gpio-ranges = <&pfc 0 160 32>;
  167. #interrupt-cells = <2>;
  168. interrupt-controller;
  169. clocks = <&cpg CPG_MOD 907>;
  170. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  171. resets = <&cpg 907>;
  172. };
  173. pfc: pinctrl@e6060000 {
  174. compatible = "renesas,pfc-r8a77470";
  175. reg = <0 0xe6060000 0 0x118>;
  176. };
  177. cpg: clock-controller@e6150000 {
  178. compatible = "renesas,r8a77470-cpg-mssr";
  179. reg = <0 0xe6150000 0 0x1000>;
  180. clocks = <&extal_clk>, <&usb_extal_clk>;
  181. clock-names = "extal", "usb_extal";
  182. #clock-cells = <2>;
  183. #power-domain-cells = <0>;
  184. #reset-cells = <1>;
  185. };
  186. apmu@e6151000 {
  187. compatible = "renesas,r8a77470-apmu", "renesas,apmu";
  188. reg = <0 0xe6151000 0 0x188>;
  189. cpus = <&cpu0>, <&cpu1>;
  190. };
  191. rst: reset-controller@e6160000 {
  192. compatible = "renesas,r8a77470-rst";
  193. reg = <0 0xe6160000 0 0x100>;
  194. };
  195. sysc: system-controller@e6180000 {
  196. compatible = "renesas,r8a77470-sysc";
  197. reg = <0 0xe6180000 0 0x200>;
  198. #power-domain-cells = <1>;
  199. };
  200. irqc: interrupt-controller@e61c0000 {
  201. compatible = "renesas,irqc-r8a77470", "renesas,irqc";
  202. #interrupt-cells = <2>;
  203. interrupt-controller;
  204. reg = <0 0xe61c0000 0 0x200>;
  205. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  206. <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  207. <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  208. <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  209. <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
  210. <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
  211. <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
  212. <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
  213. <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
  214. <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  215. clocks = <&cpg CPG_MOD 407>;
  216. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  217. resets = <&cpg 407>;
  218. };
  219. icram0: sram@e63a0000 {
  220. compatible = "mmio-sram";
  221. reg = <0 0xe63a0000 0 0x12000>;
  222. #address-cells = <1>;
  223. #size-cells = <1>;
  224. ranges = <0 0 0xe63a0000 0x12000>;
  225. };
  226. icram1: sram@e63c0000 {
  227. compatible = "mmio-sram";
  228. reg = <0 0xe63c0000 0 0x1000>;
  229. #address-cells = <1>;
  230. #size-cells = <1>;
  231. ranges = <0 0 0xe63c0000 0x1000>;
  232. smp-sram@0 {
  233. compatible = "renesas,smp-sram";
  234. reg = <0 0x100>;
  235. };
  236. };
  237. icram2: sram@e6300000 {
  238. compatible = "mmio-sram";
  239. reg = <0 0xe6300000 0 0x20000>;
  240. #address-cells = <1>;
  241. #size-cells = <1>;
  242. ranges = <0 0 0xe6300000 0x20000>;
  243. };
  244. i2c0: i2c@e6508000 {
  245. #address-cells = <1>;
  246. #size-cells = <0>;
  247. compatible = "renesas,i2c-r8a77470",
  248. "renesas,rcar-gen2-i2c";
  249. reg = <0 0xe6508000 0 0x40>;
  250. interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
  251. clocks = <&cpg CPG_MOD 931>;
  252. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  253. resets = <&cpg 931>;
  254. i2c-scl-internal-delay-ns = <6>;
  255. status = "disabled";
  256. };
  257. i2c1: i2c@e6518000 {
  258. #address-cells = <1>;
  259. #size-cells = <0>;
  260. compatible = "renesas,i2c-r8a77470",
  261. "renesas,rcar-gen2-i2c";
  262. reg = <0 0xe6518000 0 0x40>;
  263. interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
  264. clocks = <&cpg CPG_MOD 930>;
  265. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  266. resets = <&cpg 930>;
  267. i2c-scl-internal-delay-ns = <6>;
  268. status = "disabled";
  269. };
  270. i2c2: i2c@e6530000 {
  271. #address-cells = <1>;
  272. #size-cells = <0>;
  273. compatible = "renesas,i2c-r8a77470",
  274. "renesas,rcar-gen2-i2c";
  275. reg = <0 0xe6530000 0 0x40>;
  276. interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
  277. clocks = <&cpg CPG_MOD 929>;
  278. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  279. resets = <&cpg 929>;
  280. i2c-scl-internal-delay-ns = <6>;
  281. status = "disabled";
  282. };
  283. i2c3: i2c@e6540000 {
  284. #address-cells = <1>;
  285. #size-cells = <0>;
  286. compatible = "renesas,i2c-r8a77470",
  287. "renesas,rcar-gen2-i2c";
  288. reg = <0 0xe6540000 0 0x40>;
  289. interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
  290. clocks = <&cpg CPG_MOD 928>;
  291. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  292. resets = <&cpg 928>;
  293. i2c-scl-internal-delay-ns = <6>;
  294. status = "disabled";
  295. };
  296. i2c4: i2c@e6520000 {
  297. #address-cells = <1>;
  298. #size-cells = <0>;
  299. compatible = "renesas,i2c-r8a77470",
  300. "renesas,rcar-gen2-i2c";
  301. reg = <0 0xe6520000 0 0x40>;
  302. interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  303. clocks = <&cpg CPG_MOD 927>;
  304. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  305. resets = <&cpg 927>;
  306. i2c-scl-internal-delay-ns = <6>;
  307. status = "disabled";
  308. };
  309. hsusb0: hsusb@e6590000 {
  310. compatible = "renesas,usbhs-r8a77470",
  311. "renesas,rcar-gen2-usbhs";
  312. reg = <0 0xe6590000 0 0x100>;
  313. interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
  314. clocks = <&cpg CPG_MOD 704>;
  315. dmas = <&usb_dmac00 0>, <&usb_dmac00 1>,
  316. <&usb_dmac10 0>, <&usb_dmac10 1>;
  317. dma-names = "ch0", "ch1", "ch2", "ch3";
  318. renesas,buswait = <4>;
  319. phys = <&usb0 1>;
  320. phy-names = "usb";
  321. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  322. resets = <&cpg 704>;
  323. status = "disabled";
  324. };
  325. usbphy0: usb-phy-controller@e6590100 {
  326. compatible = "renesas,usb-phy-r8a77470",
  327. "renesas,rcar-gen2-usb-phy";
  328. reg = <0 0xe6590100 0 0x100>;
  329. #address-cells = <1>;
  330. #size-cells = <0>;
  331. clocks = <&cpg CPG_MOD 704>;
  332. clock-names = "usbhs";
  333. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  334. resets = <&cpg 704>;
  335. status = "disabled";
  336. usb0: usb-phy@0 {
  337. reg = <0>;
  338. #phy-cells = <1>;
  339. };
  340. };
  341. hsusb1: hsusb@e6598000 {
  342. compatible = "renesas,usbhs-r8a77470",
  343. "renesas,rcar-gen2-usbhs";
  344. reg = <0 0xe6598000 0 0x100>;
  345. interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
  346. clocks = <&cpg CPG_MOD 706>;
  347. dmas = <&usb_dmac01 0>, <&usb_dmac01 1>,
  348. <&usb_dmac11 0>, <&usb_dmac11 1>;
  349. dma-names = "ch0", "ch1", "ch2", "ch3";
  350. renesas,buswait = <4>;
  351. /* We need to turn on usbphy0 to make usbphy1 to work */
  352. phys = <&usb1 1>;
  353. phy-names = "usb";
  354. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  355. resets = <&cpg 706>;
  356. status = "disabled";
  357. };
  358. usbphy1: usb-phy-controller@e6598100 {
  359. compatible = "renesas,usb-phy-r8a77470",
  360. "renesas,rcar-gen2-usb-phy";
  361. reg = <0 0xe6598100 0 0x100>;
  362. #address-cells = <1>;
  363. #size-cells = <0>;
  364. clocks = <&cpg CPG_MOD 706>;
  365. clock-names = "usbhs";
  366. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  367. resets = <&cpg 706>;
  368. status = "disabled";
  369. usb1: usb-phy@0 {
  370. reg = <0>;
  371. #phy-cells = <1>;
  372. };
  373. };
  374. usb_dmac00: dma-controller@e65a0000 {
  375. compatible = "renesas,r8a77470-usb-dmac",
  376. "renesas,usb-dmac";
  377. reg = <0 0xe65a0000 0 0x100>;
  378. interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
  379. <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
  380. interrupt-names = "ch0", "ch1";
  381. clocks = <&cpg CPG_MOD 330>;
  382. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  383. resets = <&cpg 330>;
  384. #dma-cells = <1>;
  385. dma-channels = <2>;
  386. };
  387. usb_dmac10: dma-controller@e65b0000 {
  388. compatible = "renesas,r8a77470-usb-dmac",
  389. "renesas,usb-dmac";
  390. reg = <0 0xe65b0000 0 0x100>;
  391. interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
  392. <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  393. interrupt-names = "ch0", "ch1";
  394. clocks = <&cpg CPG_MOD 331>;
  395. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  396. resets = <&cpg 331>;
  397. #dma-cells = <1>;
  398. dma-channels = <2>;
  399. };
  400. usb_dmac01: dma-controller@e65a8000 {
  401. compatible = "renesas,r8a77470-usb-dmac",
  402. "renesas,usb-dmac";
  403. reg = <0 0xe65a8000 0 0x100>;
  404. interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
  405. <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>;
  406. interrupt-names = "ch0", "ch1";
  407. clocks = <&cpg CPG_MOD 326>;
  408. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  409. resets = <&cpg 326>;
  410. #dma-cells = <1>;
  411. dma-channels = <2>;
  412. };
  413. usb_dmac11: dma-controller@e65b8000 {
  414. compatible = "renesas,r8a77470-usb-dmac",
  415. "renesas,usb-dmac";
  416. reg = <0 0xe65b8000 0 0x100>;
  417. interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
  418. <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
  419. interrupt-names = "ch0", "ch1";
  420. clocks = <&cpg CPG_MOD 327>;
  421. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  422. resets = <&cpg 327>;
  423. #dma-cells = <1>;
  424. dma-channels = <2>;
  425. };
  426. dmac0: dma-controller@e6700000 {
  427. compatible = "renesas,dmac-r8a77470",
  428. "renesas,rcar-dmac";
  429. reg = <0 0xe6700000 0 0x20000>;
  430. interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
  431. <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
  432. <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
  433. <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
  434. <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
  435. <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
  436. <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
  437. <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
  438. <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
  439. <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
  440. <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
  441. <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
  442. <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
  443. <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
  444. <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
  445. <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
  446. interrupt-names = "error",
  447. "ch0", "ch1", "ch2", "ch3",
  448. "ch4", "ch5", "ch6", "ch7",
  449. "ch8", "ch9", "ch10", "ch11",
  450. "ch12", "ch13", "ch14";
  451. clocks = <&cpg CPG_MOD 219>;
  452. clock-names = "fck";
  453. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  454. resets = <&cpg 219>;
  455. #dma-cells = <1>;
  456. dma-channels = <15>;
  457. };
  458. dmac1: dma-controller@e6720000 {
  459. compatible = "renesas,dmac-r8a77470",
  460. "renesas,rcar-dmac";
  461. reg = <0 0xe6720000 0 0x20000>;
  462. interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
  463. <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
  464. <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
  465. <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
  466. <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
  467. <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
  468. <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
  469. <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
  470. <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
  471. <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
  472. <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
  473. <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
  474. <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
  475. <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
  476. <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
  477. <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
  478. interrupt-names = "error",
  479. "ch0", "ch1", "ch2", "ch3",
  480. "ch4", "ch5", "ch6", "ch7",
  481. "ch8", "ch9", "ch10", "ch11",
  482. "ch12", "ch13", "ch14";
  483. clocks = <&cpg CPG_MOD 218>;
  484. clock-names = "fck";
  485. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  486. resets = <&cpg 218>;
  487. #dma-cells = <1>;
  488. dma-channels = <15>;
  489. };
  490. avb: ethernet@e6800000 {
  491. compatible = "renesas,etheravb-r8a77470",
  492. "renesas,etheravb-rcar-gen2";
  493. reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
  494. interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
  495. clocks = <&cpg CPG_MOD 812>;
  496. clock-names = "fck";
  497. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  498. resets = <&cpg 812>;
  499. #address-cells = <1>;
  500. #size-cells = <0>;
  501. status = "disabled";
  502. };
  503. qspi0: spi@e6b10000 {
  504. compatible = "renesas,qspi-r8a77470", "renesas,qspi";
  505. reg = <0 0xe6b10000 0 0x2c>;
  506. interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
  507. clocks = <&cpg CPG_MOD 918>;
  508. dmas = <&dmac0 0x17>, <&dmac0 0x18>,
  509. <&dmac1 0x17>, <&dmac1 0x18>;
  510. dma-names = "tx", "rx", "tx", "rx";
  511. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  512. num-cs = <1>;
  513. #address-cells = <1>;
  514. #size-cells = <0>;
  515. resets = <&cpg 918>;
  516. status = "disabled";
  517. };
  518. qspi1: spi@ee200000 {
  519. compatible = "renesas,qspi-r8a77470", "renesas,qspi";
  520. reg = <0 0xee200000 0 0x2c>;
  521. interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
  522. clocks = <&cpg CPG_MOD 917>;
  523. dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
  524. <&dmac1 0xd1>, <&dmac1 0xd2>;
  525. dma-names = "tx", "rx", "tx", "rx";
  526. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  527. num-cs = <1>;
  528. #address-cells = <1>;
  529. #size-cells = <0>;
  530. resets = <&cpg 917>;
  531. status = "disabled";
  532. };
  533. scif0: serial@e6e60000 {
  534. compatible = "renesas,scif-r8a77470",
  535. "renesas,rcar-gen2-scif", "renesas,scif";
  536. reg = <0 0xe6e60000 0 0x40>;
  537. interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
  538. clocks = <&cpg CPG_MOD 721>,
  539. <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
  540. clock-names = "fck", "brg_int", "scif_clk";
  541. dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
  542. <&dmac1 0x29>, <&dmac1 0x2a>;
  543. dma-names = "tx", "rx", "tx", "rx";
  544. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  545. resets = <&cpg 721>;
  546. status = "disabled";
  547. };
  548. scif1: serial@e6e68000 {
  549. compatible = "renesas,scif-r8a77470",
  550. "renesas,rcar-gen2-scif", "renesas,scif";
  551. reg = <0 0xe6e68000 0 0x40>;
  552. interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
  553. clocks = <&cpg CPG_MOD 720>,
  554. <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
  555. clock-names = "fck", "brg_int", "scif_clk";
  556. dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
  557. <&dmac1 0x2d>, <&dmac1 0x2e>;
  558. dma-names = "tx", "rx", "tx", "rx";
  559. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  560. resets = <&cpg 720>;
  561. status = "disabled";
  562. };
  563. scif2: serial@e6e58000 {
  564. compatible = "renesas,scif-r8a77470",
  565. "renesas,rcar-gen2-scif", "renesas,scif";
  566. reg = <0 0xe6e58000 0 0x40>;
  567. interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
  568. clocks = <&cpg CPG_MOD 719>,
  569. <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
  570. clock-names = "fck", "brg_int", "scif_clk";
  571. dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
  572. <&dmac1 0x2b>, <&dmac1 0x2c>;
  573. dma-names = "tx", "rx", "tx", "rx";
  574. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  575. resets = <&cpg 719>;
  576. status = "disabled";
  577. };
  578. scif3: serial@e6ea8000 {
  579. compatible = "renesas,scif-r8a77470",
  580. "renesas,rcar-gen2-scif", "renesas,scif";
  581. reg = <0 0xe6ea8000 0 0x40>;
  582. interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  583. clocks = <&cpg CPG_MOD 718>,
  584. <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
  585. clock-names = "fck", "brg_int", "scif_clk";
  586. dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
  587. <&dmac1 0x2f>, <&dmac1 0x30>;
  588. dma-names = "tx", "rx", "tx", "rx";
  589. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  590. resets = <&cpg 718>;
  591. status = "disabled";
  592. };
  593. scif4: serial@e6ee0000 {
  594. compatible = "renesas,scif-r8a77470",
  595. "renesas,rcar-gen2-scif", "renesas,scif";
  596. reg = <0 0xe6ee0000 0 0x40>;
  597. interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
  598. clocks = <&cpg CPG_MOD 715>,
  599. <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
  600. clock-names = "fck", "brg_int", "scif_clk";
  601. dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
  602. <&dmac1 0xfb>, <&dmac1 0xfc>;
  603. dma-names = "tx", "rx", "tx", "rx";
  604. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  605. resets = <&cpg 715>;
  606. status = "disabled";
  607. };
  608. scif5: serial@e6ee8000 {
  609. compatible = "renesas,scif-r8a77470",
  610. "renesas,rcar-gen2-scif", "renesas,scif";
  611. reg = <0 0xe6ee8000 0 0x40>;
  612. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  613. clocks = <&cpg CPG_MOD 714>,
  614. <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
  615. clock-names = "fck", "brg_int", "scif_clk";
  616. dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
  617. <&dmac1 0xfd>, <&dmac1 0xfe>;
  618. dma-names = "tx", "rx", "tx", "rx";
  619. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  620. resets = <&cpg 714>;
  621. status = "disabled";
  622. };
  623. hscif0: serial@e62c0000 {
  624. compatible = "renesas,hscif-r8a77470",
  625. "renesas,rcar-gen2-hscif", "renesas,hscif";
  626. reg = <0 0xe62c0000 0 0x60>;
  627. interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  628. clocks = <&cpg CPG_MOD 717>,
  629. <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
  630. clock-names = "fck", "brg_int", "scif_clk";
  631. dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
  632. <&dmac1 0x39>, <&dmac1 0x3a>;
  633. dma-names = "tx", "rx", "tx", "rx";
  634. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  635. resets = <&cpg 717>;
  636. status = "disabled";
  637. };
  638. hscif1: serial@e62c8000 {
  639. compatible = "renesas,hscif-r8a77470",
  640. "renesas,rcar-gen2-hscif", "renesas,hscif";
  641. reg = <0 0xe62c8000 0 0x60>;
  642. interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
  643. clocks = <&cpg CPG_MOD 716>,
  644. <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
  645. clock-names = "fck", "brg_int", "scif_clk";
  646. dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
  647. <&dmac1 0x4d>, <&dmac1 0x4e>;
  648. dma-names = "tx", "rx", "tx", "rx";
  649. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  650. resets = <&cpg 716>;
  651. status = "disabled";
  652. };
  653. hscif2: serial@e62d0000 {
  654. compatible = "renesas,hscif-r8a77470",
  655. "renesas,rcar-gen2-hscif", "renesas,hscif";
  656. reg = <0 0xe62d0000 0 0x60>;
  657. interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
  658. clocks = <&cpg CPG_MOD 713>,
  659. <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
  660. clock-names = "fck", "brg_int", "scif_clk";
  661. dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
  662. <&dmac1 0x3b>, <&dmac1 0x3c>;
  663. dma-names = "tx", "rx", "tx", "rx";
  664. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  665. resets = <&cpg 713>;
  666. status = "disabled";
  667. };
  668. pwm0: pwm@e6e30000 {
  669. compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
  670. reg = <0 0xe6e30000 0 0x8>;
  671. clocks = <&cpg CPG_MOD 523>;
  672. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  673. resets = <&cpg 523>;
  674. #pwm-cells = <2>;
  675. status = "disabled";
  676. };
  677. pwm1: pwm@e6e31000 {
  678. compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
  679. reg = <0 0xe6e31000 0 0x8>;
  680. clocks = <&cpg CPG_MOD 523>;
  681. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  682. resets = <&cpg 523>;
  683. #pwm-cells = <2>;
  684. status = "disabled";
  685. };
  686. pwm2: pwm@e6e32000 {
  687. compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
  688. reg = <0 0xe6e32000 0 0x8>;
  689. clocks = <&cpg CPG_MOD 523>;
  690. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  691. resets = <&cpg 523>;
  692. #pwm-cells = <2>;
  693. status = "disabled";
  694. };
  695. pwm3: pwm@e6e33000 {
  696. compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
  697. reg = <0 0xe6e33000 0 0x8>;
  698. clocks = <&cpg CPG_MOD 523>;
  699. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  700. resets = <&cpg 523>;
  701. #pwm-cells = <2>;
  702. status = "disabled";
  703. };
  704. pwm4: pwm@e6e34000 {
  705. compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
  706. reg = <0 0xe6e34000 0 0x8>;
  707. clocks = <&cpg CPG_MOD 523>;
  708. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  709. resets = <&cpg 523>;
  710. #pwm-cells = <2>;
  711. status = "disabled";
  712. };
  713. pwm5: pwm@e6e35000 {
  714. compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
  715. reg = <0 0xe6e35000 0 0x8>;
  716. clocks = <&cpg CPG_MOD 523>;
  717. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  718. resets = <&cpg 523>;
  719. #pwm-cells = <2>;
  720. status = "disabled";
  721. };
  722. pwm6: pwm@e6e36000 {
  723. compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar";
  724. reg = <0 0xe6e36000 0 0x8>;
  725. clocks = <&cpg CPG_MOD 523>;
  726. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  727. resets = <&cpg 523>;
  728. #pwm-cells = <2>;
  729. status = "disabled";
  730. };
  731. vin0: video@e6ef0000 {
  732. compatible = "renesas,vin-r8a77470",
  733. "renesas,rcar-gen2-vin";
  734. reg = <0 0xe6ef0000 0 0x1000>;
  735. interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
  736. clocks = <&cpg CPG_MOD 811>;
  737. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  738. resets = <&cpg 811>;
  739. status = "disabled";
  740. };
  741. vin1: video@e6ef1000 {
  742. compatible = "renesas,vin-r8a77470",
  743. "renesas,rcar-gen2-vin";
  744. reg = <0 0xe6ef1000 0 0x1000>;
  745. interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
  746. clocks = <&cpg CPG_MOD 810>;
  747. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  748. resets = <&cpg 810>;
  749. status = "disabled";
  750. };
  751. ohci0: usb@ee080000 {
  752. compatible = "generic-ohci";
  753. reg = <0 0xee080000 0 0x100>;
  754. interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
  755. clocks = <&cpg CPG_MOD 703>;
  756. phys = <&usb0 0>, <&usb2_phy0>;
  757. phy-names = "usb";
  758. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  759. resets = <&cpg 703>;
  760. status = "disabled";
  761. };
  762. ehci0: usb@ee080100 {
  763. compatible = "generic-ehci";
  764. reg = <0 0xee080100 0 0x100>;
  765. interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
  766. clocks = <&cpg CPG_MOD 703>;
  767. phys = <&usb0 0>, <&usb2_phy0>;
  768. phy-names = "usb";
  769. companion = <&ohci0>;
  770. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  771. resets = <&cpg 703>;
  772. status = "disabled";
  773. };
  774. usb2_phy0: usb-phy@ee080200 {
  775. compatible = "renesas,usb2-phy-r8a77470";
  776. reg = <0 0xee080200 0 0x700>;
  777. clocks = <&cpg CPG_MOD 703>;
  778. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  779. resets = <&cpg 703>;
  780. #phy-cells = <0>;
  781. status = "disabled";
  782. };
  783. ohci1: usb@ee0c0000 {
  784. compatible = "generic-ohci";
  785. reg = <0 0xee0c0000 0 0x100>;
  786. interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
  787. clocks = <&cpg CPG_MOD 705>;
  788. phys = <&usb0 1>, <&usb2_phy1>, <&usb1 0>;
  789. phy-names = "usb";
  790. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  791. resets = <&cpg 705>;
  792. status = "disabled";
  793. };
  794. ehci1: usb@ee0c0100 {
  795. compatible = "generic-ehci";
  796. reg = <0 0xee0c0100 0 0x100>;
  797. interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
  798. clocks = <&cpg CPG_MOD 705>;
  799. phys = <&usb0 1>, <&usb2_phy1>, <&usb1 0>;
  800. phy-names = "usb";
  801. companion = <&ohci1>;
  802. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  803. resets = <&cpg 705>;
  804. status = "disabled";
  805. };
  806. usb2_phy1: usb-phy@ee0c0200 {
  807. compatible = "renesas,usb2-phy-r8a77470";
  808. reg = <0 0xee0c0200 0 0x700>;
  809. clocks = <&cpg CPG_MOD 705>;
  810. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  811. resets = <&cpg 705>;
  812. #phy-cells = <0>;
  813. status = "disabled";
  814. };
  815. sdhi0: mmc@ee100000 {
  816. compatible = "renesas,sdhi-r8a77470",
  817. "renesas,rcar-gen2-sdhi";
  818. reg = <0 0xee100000 0 0x328>;
  819. interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
  820. clocks = <&cpg CPG_MOD 314>;
  821. dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
  822. <&dmac1 0xcd>, <&dmac1 0xce>;
  823. dma-names = "tx", "rx", "tx", "rx";
  824. max-frequency = <156000000>;
  825. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  826. resets = <&cpg 314>;
  827. status = "disabled";
  828. };
  829. sdhi1: mmc@ee300000 {
  830. compatible = "renesas,sdhi-mmc-r8a77470";
  831. reg = <0 0xee300000 0 0x2000>;
  832. interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
  833. clocks = <&cpg CPG_MOD 313>;
  834. max-frequency = <156000000>;
  835. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  836. resets = <&cpg 313>;
  837. status = "disabled";
  838. };
  839. sdhi2: mmc@ee160000 {
  840. compatible = "renesas,sdhi-r8a77470",
  841. "renesas,rcar-gen2-sdhi";
  842. reg = <0 0xee160000 0 0x328>;
  843. interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
  844. clocks = <&cpg CPG_MOD 312>;
  845. dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
  846. <&dmac1 0xd3>, <&dmac1 0xd4>;
  847. dma-names = "tx", "rx", "tx", "rx";
  848. max-frequency = <78000000>;
  849. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  850. resets = <&cpg 312>;
  851. status = "disabled";
  852. };
  853. gic: interrupt-controller@f1001000 {
  854. compatible = "arm,gic-400";
  855. #interrupt-cells = <3>;
  856. #address-cells = <0>;
  857. interrupt-controller;
  858. reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
  859. <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
  860. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  861. clocks = <&cpg CPG_MOD 408>;
  862. clock-names = "clk";
  863. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  864. resets = <&cpg 408>;
  865. };
  866. du: display@feb00000 {
  867. compatible = "renesas,du-r8a77470";
  868. reg = <0 0xfeb00000 0 0x40000>;
  869. interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
  870. <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
  871. clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
  872. clock-names = "du.0", "du.1";
  873. resets = <&cpg 724>;
  874. reset-names = "du.0";
  875. status = "disabled";
  876. ports {
  877. #address-cells = <1>;
  878. #size-cells = <0>;
  879. port@0 {
  880. reg = <0>;
  881. du_out_rgb0: endpoint {
  882. };
  883. };
  884. port@1 {
  885. reg = <1>;
  886. du_out_rgb1: endpoint {
  887. };
  888. };
  889. port@2 {
  890. reg = <2>;
  891. du_out_lvds0: endpoint {
  892. };
  893. };
  894. };
  895. };
  896. prr: chipid@ff000044 {
  897. compatible = "renesas,prr";
  898. reg = <0 0xff000044 0 4>;
  899. };
  900. cmt0: timer@ffca0000 {
  901. compatible = "renesas,r8a77470-cmt0",
  902. "renesas,rcar-gen2-cmt0";
  903. reg = <0 0xffca0000 0 0x1004>;
  904. interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
  905. <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
  906. clocks = <&cpg CPG_MOD 124>;
  907. clock-names = "fck";
  908. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  909. resets = <&cpg 124>;
  910. status = "disabled";
  911. };
  912. cmt1: timer@e6130000 {
  913. compatible = "renesas,r8a77470-cmt1",
  914. "renesas,rcar-gen2-cmt1";
  915. reg = <0 0xe6130000 0 0x1004>;
  916. interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
  917. <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
  918. <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
  919. <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
  920. <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
  921. <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
  922. <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
  923. <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
  924. clocks = <&cpg CPG_MOD 329>;
  925. clock-names = "fck";
  926. power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  927. resets = <&cpg 329>;
  928. status = "disabled";
  929. };
  930. };
  931. timer {
  932. compatible = "arm,armv7-timer";
  933. interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  934. <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  935. <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  936. <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  937. };
  938. /* External USB clock - can be overridden by the board */
  939. usb_extal_clk: usb_extal {
  940. compatible = "fixed-clock";
  941. #clock-cells = <0>;
  942. clock-frequency = <48000000>;
  943. };
  944. };