pxa3xx.dtsi 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* The pxa3xx skeleton simply augments the 2xx version */
  3. #include "pxa2xx.dtsi"
  4. #define MFP_PIN_PXA300(gpio) \
  5. ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
  6. (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
  7. (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
  8. (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
  9. 0)
  10. #define MFP_PIN_PXA300_2(gpio) \
  11. ((gpio <= 1) ? (0x674 + 4 * gpio) : \
  12. (gpio <= 6) ? (0x2dc + 4 * gpio) : \
  13. 0)
  14. #define MFP_PIN_PXA310(gpio) \
  15. ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
  16. (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
  17. (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \
  18. (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \
  19. (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
  20. (gpio <= 262) ? 0 : \
  21. (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \
  22. 0)
  23. #define MFP_PIN_PXA310_2(gpio) \
  24. ((gpio <= 1) ? (0x674 + 4 * gpio) : \
  25. (gpio <= 6) ? (0x2dc + 4 * gpio) : \
  26. (gpio <= 10) ? (0x52c + 4 * gpio) : \
  27. 0)
  28. #define MFP_PIN_PXA320(gpio) \
  29. ((gpio <= 4) ? (0x0124 + 4 * gpio) : \
  30. (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \
  31. (gpio <= 10) ? (0x0458 + 4 * (gpio - 10)) : \
  32. (gpio <= 26) ? (0x02a0 + 4 * (gpio - 11)) : \
  33. (gpio <= 48) ? (0x0400 + 4 * (gpio - 27)) : \
  34. (gpio <= 62) ? (0x045c + 4 * (gpio - 49)) : \
  35. (gpio <= 73) ? (0x04b4 + 4 * (gpio - 63)) : \
  36. (gpio <= 98) ? (0x04f0 + 4 * (gpio - 74)) : \
  37. (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
  38. 0)
  39. #define MFP_PIN_PXA320_2(gpio) \
  40. ((gpio <= 3) ? (0x674 + 4 * gpio) : \
  41. (gpio <= 5) ? (0x284 + 4 * gpio) : \
  42. 0)
  43. /*
  44. * MFP Alternate functions for pins having a gpio.
  45. * Example of use: pinctrl-single,pins = < MFP_PIN_PXA310(21) MFP_AF1 >
  46. */
  47. #define MFP_AF0 (0 << 0)
  48. #define MFP_AF1 (1 << 0)
  49. #define MFP_AF2 (2 << 0)
  50. #define MFP_AF3 (3 << 0)
  51. #define MFP_AF4 (4 << 0)
  52. #define MFP_AF5 (5 << 0)
  53. #define MFP_AF6 (6 << 0)
  54. /*
  55. * MFP drive strength functions for pins.
  56. * Example of use: pinctrl-single,drive-strength = MFP_DS03X;
  57. */
  58. #define MFP_DSMSK (0x7 << 10)
  59. #define MFP_DS01X < (0x0 << 10) MFP_DSMSK >
  60. #define MFP_DS02X < (0x1 << 10) MFP_DSMSK >
  61. #define MFP_DS03X < (0x2 << 10) MFP_DSMSK >
  62. #define MFP_DS04X < (0x3 << 10) MFP_DSMSK >
  63. #define MFP_DS06X < (0x4 << 10) MFP_DSMSK >
  64. #define MFP_DS08X < (0x5 << 10) MFP_DSMSK >
  65. #define MFP_DS10X < (0x6 << 10) MFP_DSMSK >
  66. #define MFP_DS13X < (0x7 << 10) MFP_DSMSK >
  67. /*
  68. * MFP bias pull mode for pins.
  69. * Example of use: pinctrl-single,bias-pullup = MPF_PULL_UP;
  70. */
  71. #define MPF_PULL_MSK (0x7 << 13)
  72. #define MPF_PULL_DOWN < (0x5 << 13) (0x5 << 13) 0 MPF_PULL_MSK >
  73. #define MPF_PULL_UP < (0x6 << 13) (0x6 << 13) 0 MPF_PULL_MSK >
  74. /*
  75. * MFP low power mode for pins.
  76. * Example of use:
  77. * pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW|MFP_LPM_EDGE_FALL);
  78. *
  79. * Table that determines the low power modes outputs, with actual settings
  80. * used in parentheses for don't-care values. Except for the float output,
  81. * the configured driven and pulled levels match, so if there is a need for
  82. * non-LPM pulled output, the same configuration could probably be used.
  83. *
  84. * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel
  85. * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15)
  86. *
  87. * Input 0 X(0) X(0) X(0) 0
  88. * Drive 0 0 0 0 X(1) 0
  89. * Drive 1 0 1 X(1) 0 0
  90. * Pull hi (1) 1 X(1) 1 0 0
  91. * Pull lo (0) 1 X(0) 0 1 0
  92. * Z (float) 1 X(0) 0 0 0
  93. */
  94. #define MFP_LPM(x) < (x) MFP_LPM_MSK >
  95. #define MFP_LPM_MSK 0xe1f0
  96. #define MFP_LPM_INPUT 0x0000
  97. #define MFP_LPM_DRIVE_LOW 0x2000
  98. #define MFP_LPM_DRIVE_HIGH 0x4100
  99. #define MFP_LPM_PULL_LOW 0x2080
  100. #define MFP_LPM_PULL_HIGH 0x4180
  101. #define MFP_LPM_FLOAT 0x0080
  102. #define MFP_LPM_EDGE_NONE 0x0000
  103. #define MFP_LPM_EDGE_RISE 0x0010
  104. #define MFP_LPM_EDGE_FALL 0x0020
  105. #define MFP_LPM_EDGE_BOTH 0x0030
  106. / {
  107. model = "Marvell PXA3xx familiy SoC";
  108. compatible = "marvell,pxa3xx";
  109. pxabus {
  110. pdma: dma-controller@40000000 {
  111. compatible = "marvell,pdma-1.0";
  112. reg = <0x40000000 0x10000>;
  113. interrupts = <25>;
  114. #dma-cells = <2>;
  115. /* For backwards compatibility: */
  116. #dma-channels = <32>;
  117. dma-channels = <32>;
  118. #dma-requests = <100>;
  119. dma-requests = <100>;
  120. status = "okay";
  121. };
  122. pwri2c: i2c@40f500c0 {
  123. compatible = "mrvl,pwri2c";
  124. reg = <0x40f500c0 0x30>;
  125. interrupts = <6>;
  126. clocks = <&clks CLK_PWRI2C>;
  127. #address-cells = <0x1>;
  128. #size-cells = <0>;
  129. status = "disabled";
  130. };
  131. nand_controller: nand-controller@43100000 {
  132. compatible = "marvell,pxa3xx-nand-controller";
  133. reg = <0x43100000 90>;
  134. interrupts = <45>;
  135. clocks = <&clks CLK_NAND>;
  136. clock-names = "core";
  137. dmas = <&pdma 97 3>;
  138. dma-names = "data";
  139. #address-cells = <1>;
  140. #size-cells = <0>;
  141. status = "disabled";
  142. };
  143. pxairq: interrupt-controller@40d00000 {
  144. marvell,intc-priority;
  145. marvell,intc-nr-irqs = <56>;
  146. };
  147. pinctrl: pinctrl@40e10000 {
  148. compatible = "pinconf-single";
  149. reg = <0x40e10000 0xffff>;
  150. #pinctrl-cells = <1>;
  151. pinctrl-single,register-width = <32>;
  152. pinctrl-single,function-mask = <0x7>;
  153. };
  154. gpio: gpio@40e00000 {
  155. compatible = "intel,pxa3xx-gpio";
  156. reg = <0x40e00000 0x10000>;
  157. clocks = <&clks CLK_GPIO>;
  158. gpio-ranges = <&pinctrl 0 0 128>;
  159. interrupt-names = "gpio0", "gpio1", "gpio_mux";
  160. interrupts = <8>, <9>, <10>;
  161. gpio-controller;
  162. #gpio-cells = <0x2>;
  163. interrupt-controller;
  164. #interrupt-cells = <0x2>;
  165. };
  166. mmc0: mmc@41100000 {
  167. compatible = "marvell,pxa-mmc";
  168. reg = <0x41100000 0x1000>;
  169. interrupts = <23>;
  170. clocks = <&clks CLK_MMC1>;
  171. dmas = <&pdma 21 3
  172. &pdma 22 3>;
  173. dma-names = "rx", "tx";
  174. status = "disabled";
  175. };
  176. mmc1: mmc@42000000 {
  177. compatible = "marvell,pxa-mmc";
  178. reg = <0x42000000 0x1000>;
  179. interrupts = <41>;
  180. clocks = <&clks CLK_MMC2>;
  181. dmas = <&pdma 93 3
  182. &pdma 94 3>;
  183. dma-names = "rx", "tx";
  184. status = "disabled";
  185. };
  186. mmc2: mmc@42500000 {
  187. compatible = "marvell,pxa-mmc";
  188. reg = <0x42500000 0x1000>;
  189. interrupts = <55>;
  190. clocks = <&clks CLK_MMC3>;
  191. dmas = <&pdma 46 3
  192. &pdma 47 3>;
  193. dma-names = "rx", "tx";
  194. status = "disabled";
  195. };
  196. usb0: usb@4c000000 {
  197. compatible = "marvell,pxa-ohci";
  198. reg = <0x4c000000 0x10000>;
  199. interrupts = <3>;
  200. clocks = <&clks CLK_USBH>;
  201. status = "disabled";
  202. };
  203. pwm0: pwm@40b00000 {
  204. compatible = "marvell,pxa270-pwm";
  205. reg = <0x40b00000 0x10>;
  206. #pwm-cells = <1>;
  207. clocks = <&clks CLK_PWM0>;
  208. status = "disabled";
  209. };
  210. pwm1: pwm@40b00010 {
  211. compatible = "marvell,pxa270-pwm";
  212. reg = <0x40b00010 0x10>;
  213. #pwm-cells = <1>;
  214. clocks = <&clks CLK_PWM1>;
  215. status = "disabled";
  216. };
  217. pwm2: pwm@40c00000 {
  218. compatible = "marvell,pxa270-pwm";
  219. reg = <0x40c00000 0x10>;
  220. #pwm-cells = <1>;
  221. clocks = <&clks CLK_PWM0>;
  222. status = "disabled";
  223. };
  224. pwm3: pwm@40c00010 {
  225. compatible = "marvell,pxa270-pwm";
  226. reg = <0x40c00010 0x10>;
  227. #pwm-cells = <1>;
  228. clocks = <&clks CLK_PWM1>;
  229. status = "disabled";
  230. };
  231. ssp1: ssp@41000000 {
  232. compatible = "mrvl,pxa3xx-ssp";
  233. reg = <0x41000000 0x40>;
  234. interrupts = <24>;
  235. clocks = <&clks CLK_SSP1>;
  236. status = "disabled";
  237. };
  238. ssp2: ssp@41700000 {
  239. compatible = "mrvl,pxa3xx-ssp";
  240. reg = <0x41700000 0x40>;
  241. interrupts = <16>;
  242. clocks = <&clks CLK_SSP2>;
  243. status = "disabled";
  244. };
  245. ssp3: ssp@41900000 {
  246. compatible = "mrvl,pxa3xx-ssp";
  247. reg = <0x41900000 0x40>;
  248. interrupts = <0>;
  249. clocks = <&clks CLK_SSP3>;
  250. status = "disabled";
  251. };
  252. ssp4: ssp@41a00000 {
  253. compatible = "mrvl,pxa3xx-ssp";
  254. reg = <0x41a00000 0x40>;
  255. interrupts = <13>;
  256. clocks = <&clks CLK_SSP4>;
  257. status = "disabled";
  258. };
  259. timer@40a00000 {
  260. compatible = "marvell,pxa-timer";
  261. reg = <0x40a00000 0x20>;
  262. interrupts = <26>;
  263. clocks = <&clks CLK_OSTIMER>;
  264. status = "okay";
  265. };
  266. gcu: display-controller@54000000 {
  267. compatible = "marvell,pxa300-gcu";
  268. reg = <0x54000000 0x1000>;
  269. interrupts = <39>;
  270. clocks = <&clks CLK_PXA300_GCU>;
  271. status = "disabled";
  272. };
  273. };
  274. clocks {
  275. /*
  276. * The muxing of external clocks/internal dividers for osc* clock
  277. * sources has been hidden under the carpet by now.
  278. */
  279. #address-cells = <1>;
  280. #size-cells = <1>;
  281. ranges;
  282. clks: clocks {
  283. compatible = "marvell,pxa300-clocks";
  284. #clock-cells = <1>;
  285. status = "okay";
  286. };
  287. };
  288. };