omap3-zoom3.dts 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  4. */
  5. /dts-v1/;
  6. #include "omap36xx.dtsi"
  7. #include "omap-zoom-common.dtsi"
  8. / {
  9. model = "TI Zoom3";
  10. compatible = "ti,omap3-zoom3", "ti,omap3630", "ti,omap36xx", "ti,omap3";
  11. cpus {
  12. cpu@0 {
  13. cpu0-supply = <&vcc>;
  14. };
  15. };
  16. memory@80000000 {
  17. device_type = "memory";
  18. reg = <0x80000000 0x20000000>; /* 512 MB */
  19. };
  20. vddvario: regulator-vddvario {
  21. compatible = "regulator-fixed";
  22. regulator-name = "vddvario";
  23. regulator-always-on;
  24. };
  25. vdd33a: regulator-vdd33a {
  26. compatible = "regulator-fixed";
  27. regulator-name = "vdd33a";
  28. regulator-always-on;
  29. };
  30. wl12xx_vmmc: wl12xx_vmmc {
  31. pinctrl-names = "default";
  32. pinctrl-0 = <&wl12xx_gpio>;
  33. compatible = "regulator-fixed";
  34. regulator-name = "vwl1271";
  35. regulator-min-microvolt = <1800000>;
  36. regulator-max-microvolt = <1800000>;
  37. gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */
  38. startup-delay-us = <70000>;
  39. enable-active-high;
  40. };
  41. };
  42. &omap3_pmx_core {
  43. /* REVISIT: twl gpio0 is mmc0_cd */
  44. mmc1_pins: pinmux_mmc1_pins {
  45. pinctrl-single,pins = <
  46. OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
  47. OMAP3_CORE1_IOPAD(0x2146, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
  48. OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
  49. OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
  50. OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
  51. OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
  52. >;
  53. };
  54. mmc2_pins: pinmux_mmc2_pins {
  55. pinctrl-single,pins = <
  56. OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
  57. OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
  58. OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
  59. OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
  60. OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
  61. OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
  62. OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat4.sdmmc2_dat4 */
  63. OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat5.sdmmc2_dat5 */
  64. OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat6.sdmmc2_dat6 */
  65. OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */
  66. >;
  67. };
  68. mmc3_pins: pinmux_mmc3_pins {
  69. pinctrl-single,pins = <
  70. OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 WLAN IRQ */
  71. OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */
  72. >;
  73. };
  74. uart1_pins: pinmux_uart1_pins {
  75. pinctrl-single,pins = <
  76. OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */
  77. OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */
  78. OMAP3_CORE1_IOPAD(0x2182, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
  79. OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */
  80. >;
  81. };
  82. uart2_pins: pinmux_uart2_pins {
  83. pinctrl-single,pins = <
  84. OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */
  85. OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */
  86. OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
  87. OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
  88. >;
  89. };
  90. uart3_pins: pinmux_uart3_pins {
  91. pinctrl-single,pins = <
  92. OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */
  93. OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */
  94. OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
  95. OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
  96. >;
  97. };
  98. /* wl12xx GPIO output for WLAN_EN */
  99. wl12xx_gpio: pinmux_wl12xx_gpio {
  100. pinctrl-single,pins = <
  101. OMAP3_CORE1_IOPAD(0x211a, PIN_OUTPUT| MUX_MODE4) /* cam_d2.gpio_101 */
  102. >;
  103. };
  104. };
  105. &omap3_pmx_core2 {
  106. mmc3_2_pins: pinmux_mmc3_2_pins {
  107. pinctrl-single,pins = <
  108. OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */
  109. OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */
  110. OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
  111. OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */
  112. OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */
  113. >;
  114. };
  115. };
  116. &omap3_pmx_wkup {
  117. wlan_host_wkup: pinmux_wlan_host_wkup_pins {
  118. pinctrl-single,pins = <
  119. OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_clkout1.gpio_10 WLAN_HOST_WKUP */
  120. >;
  121. };
  122. };
  123. &i2c1 {
  124. clock-frequency = <2600000>;
  125. twl: twl@48 {
  126. reg = <0x48>;
  127. interrupts = <7>; /* SYS_NIRQ cascaded to intc */
  128. interrupt-parent = <&intc>;
  129. };
  130. };
  131. #include "twl4030.dtsi"
  132. &i2c2 {
  133. clock-frequency = <400000>;
  134. };
  135. &i2c3 {
  136. clock-frequency = <400000>;
  137. /*
  138. * TVP5146 Video decoder-in for analog input support.
  139. */
  140. tvp5146@5c {
  141. compatible = "ti,tvp5146m2";
  142. reg = <0x5c>;
  143. };
  144. };
  145. &twl_gpio {
  146. ti,use-leds;
  147. };
  148. &mmc1 {
  149. vmmc-supply = <&vmmc1>;
  150. vqmmc-supply = <&vsim>;
  151. bus-width = <4>;
  152. pinctrl-names = "default";
  153. pinctrl-0 = <&mmc1_pins>;
  154. };
  155. /*
  156. &mmc2 {
  157. vmmc-supply = <&vmmc2>;
  158. ti,non-removable;
  159. bus-width = <8>;
  160. pinctrl-names = "default";
  161. pinctrl-0 = <&mmc2_pins>;
  162. };
  163. */
  164. &mmc3 {
  165. vmmc-supply = <&wl12xx_vmmc>;
  166. non-removable;
  167. bus-width = <4>;
  168. cap-power-off-card;
  169. pinctrl-names = "default";
  170. pinctrl-0 = <&mmc3_pins &mmc3_2_pins>;
  171. #address-cells = <1>;
  172. #size-cells = <0>;
  173. wlcore: wlcore@2 {
  174. compatible = "ti,wl1271";
  175. reg = <2>;
  176. interrupt-parent = <&gpio6>;
  177. interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 162 */
  178. ref-clock-frequency = <26000000>;
  179. };
  180. };
  181. &uart1 {
  182. pinctrl-names = "default";
  183. pinctrl-0 = <&uart1_pins>;
  184. };
  185. &uart2 {
  186. pinctrl-names = "default";
  187. pinctrl-0 = <&uart2_pins>;
  188. };
  189. &uart3 {
  190. pinctrl-names = "default";
  191. pinctrl-0 = <&uart3_pins>;
  192. };
  193. &uart4 {
  194. status = "disabled";
  195. };
  196. &usb_otg_hs {
  197. interface-type = <0>;
  198. usb-phy = <&usb2_phy>;
  199. mode = <3>;
  200. power = <50>;
  201. };