omap3-igep.dtsi 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Common device tree for IGEP boards based on AM/DM37x
  4. *
  5. * Copyright (C) 2012 Javier Martinez Canillas <[email protected]>
  6. * Copyright (C) 2012 Enric Balletbo i Serra <[email protected]>
  7. */
  8. /dts-v1/;
  9. #include "omap36xx.dtsi"
  10. / {
  11. memory@80000000 {
  12. device_type = "memory";
  13. reg = <0x80000000 0x20000000>; /* 512 MB */
  14. };
  15. chosen {
  16. stdout-path = &uart3;
  17. };
  18. sound {
  19. compatible = "ti,omap-twl4030";
  20. ti,model = "igep2";
  21. ti,mcbsp = <&mcbsp2>;
  22. };
  23. vdd33: regulator-vdd33 {
  24. compatible = "regulator-fixed";
  25. regulator-name = "vdd33";
  26. regulator-always-on;
  27. };
  28. };
  29. &omap3_pmx_core {
  30. gpmc_pins: pinmux_gpmc_pins {
  31. pinctrl-single,pins = <
  32. /* OneNAND seems to require PIN_INPUT on clock. */
  33. OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
  34. >;
  35. };
  36. uart1_pins: pinmux_uart1_pins {
  37. pinctrl-single,pins = <
  38. OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
  39. OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */
  40. >;
  41. };
  42. uart3_pins: pinmux_uart3_pins {
  43. pinctrl-single,pins = <
  44. OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */
  45. OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */
  46. >;
  47. };
  48. mcbsp2_pins: pinmux_mcbsp2_pins {
  49. pinctrl-single,pins = <
  50. OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
  51. OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */
  52. OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */
  53. OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */
  54. >;
  55. };
  56. mmc1_pins: pinmux_mmc1_pins {
  57. pinctrl-single,pins = <
  58. OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
  59. OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
  60. OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
  61. OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
  62. OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
  63. OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
  64. >;
  65. };
  66. mmc2_pins: pinmux_mmc2_pins {
  67. pinctrl-single,pins = <
  68. OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
  69. OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
  70. OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
  71. OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
  72. OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
  73. OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
  74. >;
  75. };
  76. i2c1_pins: pinmux_i2c1_pins {
  77. pinctrl-single,pins = <
  78. OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
  79. OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
  80. >;
  81. };
  82. i2c3_pins: pinmux_i2c3_pins {
  83. pinctrl-single,pins = <
  84. OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */
  85. OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */
  86. >;
  87. };
  88. };
  89. &gpmc {
  90. pinctrl-names = "default";
  91. pinctrl-0 = <&gpmc_pins>;
  92. nand@0,0 {
  93. compatible = "ti,omap2-nand";
  94. reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
  95. interrupt-parent = <&gpmc>;
  96. interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
  97. <1 IRQ_TYPE_NONE>; /* termcount */
  98. linux,mtd-name = "micron,mt29c4g96maz";
  99. nand-bus-width = <16>;
  100. gpmc,device-width = <2>;
  101. ti,nand-ecc-opt = "bch8";
  102. gpmc,sync-clk-ps = <0>;
  103. gpmc,cs-on-ns = <0>;
  104. gpmc,cs-rd-off-ns = <44>;
  105. gpmc,cs-wr-off-ns = <44>;
  106. gpmc,adv-on-ns = <6>;
  107. gpmc,adv-rd-off-ns = <34>;
  108. gpmc,adv-wr-off-ns = <44>;
  109. gpmc,we-off-ns = <40>;
  110. gpmc,oe-off-ns = <54>;
  111. gpmc,access-ns = <64>;
  112. gpmc,rd-cycle-ns = <82>;
  113. gpmc,wr-cycle-ns = <82>;
  114. gpmc,wr-access-ns = <40>;
  115. gpmc,wr-data-mux-bus-ns = <0>;
  116. #address-cells = <1>;
  117. #size-cells = <1>;
  118. status = "okay";
  119. };
  120. onenand@0,0 {
  121. compatible = "ti,omap2-onenand";
  122. reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
  123. gpmc,sync-read;
  124. gpmc,sync-write;
  125. gpmc,burst-length = <16>;
  126. gpmc,burst-wrap;
  127. gpmc,burst-read;
  128. gpmc,burst-write;
  129. gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
  130. gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */
  131. gpmc,cs-on-ns = <0>;
  132. gpmc,cs-rd-off-ns = <96>;
  133. gpmc,cs-wr-off-ns = <96>;
  134. gpmc,adv-on-ns = <0>;
  135. gpmc,adv-rd-off-ns = <12>;
  136. gpmc,adv-wr-off-ns = <12>;
  137. gpmc,oe-on-ns = <18>;
  138. gpmc,oe-off-ns = <96>;
  139. gpmc,we-on-ns = <0>;
  140. gpmc,we-off-ns = <96>;
  141. gpmc,rd-cycle-ns = <114>;
  142. gpmc,wr-cycle-ns = <114>;
  143. gpmc,access-ns = <90>;
  144. gpmc,page-burst-access-ns = <12>;
  145. gpmc,bus-turnaround-ns = <0>;
  146. gpmc,cycle2cycle-delay-ns = <0>;
  147. gpmc,wait-monitoring-ns = <0>;
  148. gpmc,clk-activation-ns = <6>;
  149. gpmc,wr-data-mux-bus-ns = <30>;
  150. gpmc,wr-access-ns = <90>;
  151. gpmc,sync-clk-ps = <12000>;
  152. #address-cells = <1>;
  153. #size-cells = <1>;
  154. status = "disabled";
  155. };
  156. };
  157. &i2c1 {
  158. pinctrl-names = "default";
  159. pinctrl-0 = <&i2c1_pins>;
  160. clock-frequency = <2600000>;
  161. twl: twl@48 {
  162. reg = <0x48>;
  163. interrupts = <7>; /* SYS_NIRQ cascaded to intc */
  164. interrupt-parent = <&intc>;
  165. twl_audio: audio {
  166. compatible = "ti,twl4030-audio";
  167. codec {
  168. };
  169. };
  170. };
  171. };
  172. #include "twl4030.dtsi"
  173. #include "twl4030_omap3.dtsi"
  174. &i2c3 {
  175. pinctrl-names = "default";
  176. pinctrl-0 = <&i2c3_pins>;
  177. };
  178. &mcbsp2 {
  179. pinctrl-names = "default";
  180. pinctrl-0 = <&mcbsp2_pins>;
  181. status = "okay";
  182. };
  183. &mmc1 {
  184. pinctrl-names = "default";
  185. pinctrl-0 = <&mmc1_pins>;
  186. vmmc-supply = <&vmmc1>;
  187. vmmc_aux-supply = <&vsim>;
  188. bus-width = <4>;
  189. cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
  190. };
  191. &mmc3 {
  192. status = "disabled";
  193. };
  194. &uart1 {
  195. pinctrl-names = "default";
  196. pinctrl-0 = <&uart1_pins>;
  197. };
  198. &uart3 {
  199. pinctrl-names = "default";
  200. pinctrl-0 = <&uart3_pins>;
  201. };
  202. &twl_gpio {
  203. ti,use-leds;
  204. };
  205. &usb_otg_hs {
  206. interface-type = <0>;
  207. usb-phy = <&usb2_phy>;
  208. phys = <&usb2_phy>;
  209. phy-names = "usb2-phy";
  210. mode = <3>;
  211. power = <50>;
  212. };