omap3-gta04a5one.dts 3.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2014-18 H. Nikolaus Schaller <[email protected]>
  4. */
  5. #include "omap3-gta04a5.dts"
  6. / {
  7. model = "Goldelico GTA04A5/Letux 2804 with OneNAND";
  8. };
  9. &omap3_pmx_core {
  10. gpmc_pins: pinmux_gpmc_pins {
  11. pinctrl-single,pins = <
  12. /* address lines */
  13. OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */
  14. OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */
  15. OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */
  16. /* data lines, gpmc_d0..d7 not muxable according to TRM */
  17. OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */
  18. OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */
  19. OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */
  20. OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */
  21. OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */
  22. OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */
  23. OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */
  24. OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */
  25. /*
  26. * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
  27. * according to TRM. OneNAND seems to require PIN_INPUT on clock.
  28. */
  29. OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */
  30. OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
  31. >;
  32. };
  33. };
  34. &gpmc {
  35. /* switch inherited setup to OneNAND */
  36. ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */
  37. pinctrl-names = "default";
  38. pinctrl-0 = <&gpmc_pins>;
  39. /delete-node/ nand@0,0;
  40. onenand@0,0 {
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. compatible = "ti,omap2-onenand";
  44. reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
  45. gpmc,sync-read;
  46. gpmc,sync-write;
  47. gpmc,burst-length = <16>;
  48. gpmc,burst-read;
  49. gpmc,burst-wrap;
  50. gpmc,burst-write;
  51. gpmc,device-width = <2>;
  52. gpmc,mux-add-data = <2>;
  53. gpmc,cs-on-ns = <0>;
  54. gpmc,cs-rd-off-ns = <87>;
  55. gpmc,cs-wr-off-ns = <87>;
  56. gpmc,adv-on-ns = <0>;
  57. gpmc,adv-rd-off-ns = <10>;
  58. gpmc,adv-wr-off-ns = <10>;
  59. gpmc,oe-on-ns = <15>;
  60. gpmc,oe-off-ns = <87>;
  61. gpmc,we-on-ns = <0>;
  62. gpmc,we-off-ns = <87>;
  63. gpmc,rd-cycle-ns = <112>;
  64. gpmc,wr-cycle-ns = <112>;
  65. gpmc,access-ns = <81>;
  66. gpmc,page-burst-access-ns = <15>;
  67. gpmc,bus-turnaround-ns = <0>;
  68. gpmc,cycle2cycle-delay-ns = <0>;
  69. gpmc,wait-monitoring-ns = <0>;
  70. gpmc,clk-activation-ns = <5>;
  71. gpmc,wr-data-mux-bus-ns = <30>;
  72. gpmc,wr-access-ns = <81>;
  73. gpmc,sync-clk-ps = <15000>;
  74. x-loader@0 {
  75. label = "X-Loader";
  76. reg = <0 0x80000>;
  77. };
  78. bootloaders@80000 {
  79. label = "U-Boot";
  80. reg = <0x80000 0x1c0000>;
  81. };
  82. bootloaders_env@240000 {
  83. label = "U-Boot Env";
  84. reg = <0x240000 0x40000>;
  85. };
  86. kernel@280000 {
  87. label = "Kernel";
  88. reg = <0x280000 0x600000>;
  89. };
  90. filesystem@880000 {
  91. label = "File System";
  92. reg = <0x880000 0>; /* 0 = MTDPART_SIZ_FULL */
  93. };
  94. };
  95. };