omap3-cm-t3x.dtsi 8.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Common support for CompuLab CM-T3x CoMs
  4. */
  5. / {
  6. memory@80000000 {
  7. device_type = "memory";
  8. reg = <0x80000000 0x10000000>; /* 256 MB */
  9. };
  10. leds {
  11. compatible = "gpio-leds";
  12. pinctrl-names = "default";
  13. pinctrl-0 = <&green_led_pins>;
  14. ledb {
  15. label = "cm-t3x:green";
  16. gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* gpio186 */
  17. linux,default-trigger = "heartbeat";
  18. };
  19. };
  20. /* HS USB Port 1 Power */
  21. hsusb1_power: hsusb1_power_reg {
  22. compatible = "regulator-fixed";
  23. regulator-name = "hsusb1_vbus";
  24. regulator-min-microvolt = <3300000>;
  25. regulator-max-microvolt = <3300000>;
  26. startup-delay-us = <70000>;
  27. };
  28. /* HS USB Port 2 Power */
  29. hsusb2_power: hsusb2_power_reg {
  30. compatible = "regulator-fixed";
  31. regulator-name = "hsusb2_vbus";
  32. regulator-min-microvolt = <3300000>;
  33. regulator-max-microvolt = <3300000>;
  34. startup-delay-us = <70000>;
  35. };
  36. /* HS USB Host PHY on PORT 1 */
  37. hsusb1_phy: hsusb1_phy {
  38. compatible = "usb-nop-xceiv";
  39. vcc-supply = <&hsusb1_power>;
  40. #phy-cells = <0>;
  41. };
  42. /* HS USB Host PHY on PORT 2 */
  43. hsusb2_phy: hsusb2_phy {
  44. compatible = "usb-nop-xceiv";
  45. vcc-supply = <&hsusb2_power>;
  46. #phy-cells = <0>;
  47. };
  48. ads7846reg: ads7846-reg {
  49. compatible = "regulator-fixed";
  50. regulator-name = "ads7846-reg";
  51. regulator-min-microvolt = <3300000>;
  52. regulator-max-microvolt = <3300000>;
  53. };
  54. tv0: svideo-connector {
  55. compatible = "svideo-connector";
  56. label = "tv";
  57. port {
  58. tv_connector_in: endpoint {
  59. remote-endpoint = <&venc_out>;
  60. };
  61. };
  62. };
  63. };
  64. &omap3_pmx_core {
  65. uart3_pins: pinmux_uart3_pins {
  66. pinctrl-single,pins = <
  67. OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
  68. OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
  69. >;
  70. };
  71. mmc1_pins: pinmux_mmc1_pins {
  72. pinctrl-single,pins = <
  73. OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
  74. OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
  75. OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
  76. OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
  77. OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
  78. OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
  79. >;
  80. };
  81. green_led_pins: pinmux_green_led_pins {
  82. pinctrl-single,pins = <
  83. OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */
  84. >;
  85. };
  86. dss_dpi_pins_common: pinmux_dss_dpi_pins_common {
  87. pinctrl-single,pins = <
  88. OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
  89. OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
  90. OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
  91. OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
  92. OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
  93. OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
  94. OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
  95. OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
  96. OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
  97. OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
  98. OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
  99. OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
  100. OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
  101. OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
  102. OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
  103. OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
  104. OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
  105. OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
  106. OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
  107. OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
  108. OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
  109. OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
  110. >;
  111. };
  112. dss_dpi_pins_cm_t35x: pinmux_dss_dpi_pins_cm_t35x {
  113. pinctrl-single,pins = <
  114. OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
  115. OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
  116. OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
  117. OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
  118. OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
  119. OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
  120. >;
  121. };
  122. ads7846_pins: pinmux_ads7846_pins {
  123. pinctrl-single,pins = <
  124. OMAP3_CORE1_IOPAD(0x20ba, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs6.gpio_57 */
  125. >;
  126. };
  127. mcspi1_pins: pinmux_mcspi1_pins {
  128. pinctrl-single,pins = <
  129. OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk */
  130. OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo */
  131. OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi */
  132. OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0 */
  133. >;
  134. };
  135. i2c1_pins: pinmux_i2c1_pins {
  136. pinctrl-single,pins = <
  137. OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
  138. OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
  139. >;
  140. };
  141. mcbsp2_pins: pinmux_mcbsp2_pins {
  142. pinctrl-single,pins = <
  143. OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */
  144. OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */
  145. OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */
  146. OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */
  147. >;
  148. };
  149. };
  150. &uart3 {
  151. pinctrl-names = "default";
  152. pinctrl-0 = <&uart3_pins>;
  153. };
  154. &mmc1 {
  155. pinctrl-names = "default";
  156. pinctrl-0 = <&mmc1_pins>;
  157. bus-width = <4>;
  158. };
  159. &mmc3 {
  160. status = "disabled";
  161. };
  162. &i2c1 {
  163. pinctrl-names = "default";
  164. pinctrl-0 = <&i2c1_pins>;
  165. clock-frequency = <400000>;
  166. at24@50 {
  167. compatible = "atmel,24c02";
  168. pagesize = <16>;
  169. reg = <0x50>;
  170. };
  171. };
  172. &i2c3 {
  173. clock-frequency = <400000>;
  174. };
  175. &usbhshost {
  176. port1-mode = "ehci-phy";
  177. port2-mode = "ehci-phy";
  178. };
  179. &usbhsehci {
  180. phys = <&hsusb1_phy &hsusb2_phy>;
  181. };
  182. &mcspi1 {
  183. pinctrl-names = "default";
  184. pinctrl-0 = <&mcspi1_pins>;
  185. /* touch controller */
  186. ads7846@0 {
  187. pinctrl-names = "default";
  188. pinctrl-0 = <&ads7846_pins>;
  189. compatible = "ti,ads7846";
  190. vcc-supply = <&ads7846reg>;
  191. reg = <0>; /* CS0 */
  192. spi-max-frequency = <1500000>;
  193. interrupt-parent = <&gpio2>;
  194. interrupts = <25 0>; /* gpio_57 */
  195. pendown-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>;
  196. ti,x-min = /bits/ 16 <0x0>;
  197. ti,x-max = /bits/ 16 <0x0fff>;
  198. ti,y-min = /bits/ 16 <0x0>;
  199. ti,y-max = /bits/ 16 <0x0fff>;
  200. ti,x-plate-ohms = /bits/ 16 <180>;
  201. ti,pressure-max = /bits/ 16 <255>;
  202. ti,debounce-max = /bits/ 16 <30>;
  203. ti,debounce-tol = /bits/ 16 <10>;
  204. ti,debounce-rep = /bits/ 16 <1>;
  205. wakeup-source;
  206. };
  207. };
  208. &venc {
  209. status = "okay";
  210. port {
  211. venc_out: endpoint {
  212. remote-endpoint = <&tv_connector_in>;
  213. ti,channels = <2>;
  214. };
  215. };
  216. };
  217. &mcbsp2 {
  218. status = "okay";
  219. pinctrl-names = "default";
  220. pinctrl-0 = <&mcbsp2_pins>;
  221. };
  222. &gpmc {
  223. ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */
  224. nand@0,0 {
  225. compatible = "ti,omap2-nand";
  226. reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
  227. interrupt-parent = <&gpmc>;
  228. interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
  229. <1 IRQ_TYPE_NONE>; /* termcount */
  230. nand-bus-width = <8>;
  231. gpmc,device-width = <1>;
  232. ti,nand-ecc-opt = "sw";
  233. gpmc,cs-on-ns = <0>;
  234. gpmc,cs-rd-off-ns = <120>;
  235. gpmc,cs-wr-off-ns = <120>;
  236. gpmc,adv-on-ns = <0>;
  237. gpmc,adv-rd-off-ns = <120>;
  238. gpmc,adv-wr-off-ns = <120>;
  239. gpmc,we-on-ns = <6>;
  240. gpmc,we-off-ns = <90>;
  241. gpmc,oe-on-ns = <6>;
  242. gpmc,oe-off-ns = <90>;
  243. gpmc,page-burst-access-ns = <6>;
  244. gpmc,access-ns = <72>;
  245. gpmc,cycle2cycle-delay-ns = <60>;
  246. gpmc,rd-cycle-ns = <120>;
  247. gpmc,wr-cycle-ns = <120>;
  248. gpmc,wr-access-ns = <186>;
  249. gpmc,wr-data-mux-bus-ns = <90>;
  250. #address-cells = <1>;
  251. #size-cells = <1>;
  252. partition@0 {
  253. label = "xloader";
  254. reg = <0 0x80000>;
  255. };
  256. partition@80000 {
  257. label = "uboot";
  258. reg = <0x80000 0x1e0000>;
  259. };
  260. partition@260000 {
  261. label = "uboot environment";
  262. reg = <0x260000 0x40000>;
  263. };
  264. partition@2a0000 {
  265. label = "linux";
  266. reg = <0x2a0000 0x400000>;
  267. };
  268. partition@6a0000 {
  269. label = "rootfs";
  270. reg = <0x6a0000 0x1f880000>;
  271. };
  272. };
  273. };