omap2430.dtsi 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Device Tree Source for OMAP243x SoC
  4. *
  5. * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  6. */
  7. #include "omap2.dtsi"
  8. / {
  9. compatible = "ti,omap2430", "ti,omap2";
  10. ocp {
  11. l4_wkup: l4_wkup@49000000 {
  12. compatible = "ti,omap2-l4-wkup", "simple-bus";
  13. #address-cells = <1>;
  14. #size-cells = <1>;
  15. ranges = <0 0x49000000 0x31000>;
  16. prcm: prcm@6000 {
  17. compatible = "ti,omap2-prcm";
  18. reg = <0x6000 0x1000>;
  19. prcm_clocks: clocks {
  20. #address-cells = <1>;
  21. #size-cells = <0>;
  22. };
  23. prcm_clockdomains: clockdomains {
  24. };
  25. };
  26. scm: scm@2000 {
  27. compatible = "ti,omap2-scm", "simple-bus";
  28. reg = <0x2000 0x1000>;
  29. #address-cells = <1>;
  30. #size-cells = <1>;
  31. #pinctrl-cells = <1>;
  32. ranges = <0 0x2000 0x1000>;
  33. omap2430_pmx: pinmux@30 {
  34. compatible = "ti,omap2430-padconf",
  35. "pinctrl-single";
  36. reg = <0x30 0x0154>;
  37. #address-cells = <1>;
  38. #size-cells = <0>;
  39. #pinctrl-cells = <1>;
  40. pinctrl-single,register-width = <8>;
  41. pinctrl-single,function-mask = <0x3f>;
  42. };
  43. scm_conf: scm_conf@270 {
  44. compatible = "syscon",
  45. "simple-bus";
  46. reg = <0x270 0x240>;
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. ranges = <0 0x270 0x240>;
  50. scm_clocks: clocks {
  51. #address-cells = <1>;
  52. #size-cells = <0>;
  53. };
  54. pbias_regulator: pbias_regulator@230 {
  55. compatible = "ti,pbias-omap2", "ti,pbias-omap";
  56. reg = <0x230 0x4>;
  57. syscon = <&scm_conf>;
  58. pbias_mmc_reg: pbias_mmc_omap2430 {
  59. regulator-name = "pbias_mmc_omap2430";
  60. regulator-min-microvolt = <1800000>;
  61. regulator-max-microvolt = <3000000>;
  62. };
  63. };
  64. };
  65. scm_clockdomains: clockdomains {
  66. };
  67. };
  68. target-module@20000 {
  69. compatible = "ti,sysc-omap2", "ti,sysc";
  70. reg = <0x20000 0x4>,
  71. <0x20004 0x4>;
  72. reg-names = "rev", "sysc";
  73. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  74. <SYSC_IDLE_NO>;
  75. clocks = <&func_32k_ck>;
  76. clock-names = "fck";
  77. #address-cells = <1>;
  78. #size-cells = <1>;
  79. ranges = <0x0 0x20000 0x1000>;
  80. counter32k: counter@0 {
  81. compatible = "ti,omap-counter32k";
  82. reg = <0 0x20>;
  83. };
  84. };
  85. };
  86. gpio1: gpio@4900c000 {
  87. compatible = "ti,omap2-gpio";
  88. reg = <0x4900c000 0x200>;
  89. interrupts = <29>;
  90. ti,hwmods = "gpio1";
  91. ti,gpio-always-on;
  92. #gpio-cells = <2>;
  93. gpio-controller;
  94. #interrupt-cells = <2>;
  95. interrupt-controller;
  96. };
  97. gpio2: gpio@4900e000 {
  98. compatible = "ti,omap2-gpio";
  99. reg = <0x4900e000 0x200>;
  100. interrupts = <30>;
  101. ti,hwmods = "gpio2";
  102. ti,gpio-always-on;
  103. #gpio-cells = <2>;
  104. gpio-controller;
  105. #interrupt-cells = <2>;
  106. interrupt-controller;
  107. };
  108. gpio3: gpio@49010000 {
  109. compatible = "ti,omap2-gpio";
  110. reg = <0x49010000 0x200>;
  111. interrupts = <31>;
  112. ti,hwmods = "gpio3";
  113. ti,gpio-always-on;
  114. #gpio-cells = <2>;
  115. gpio-controller;
  116. #interrupt-cells = <2>;
  117. interrupt-controller;
  118. };
  119. gpio4: gpio@49012000 {
  120. compatible = "ti,omap2-gpio";
  121. reg = <0x49012000 0x200>;
  122. interrupts = <32>;
  123. ti,hwmods = "gpio4";
  124. ti,gpio-always-on;
  125. #gpio-cells = <2>;
  126. gpio-controller;
  127. #interrupt-cells = <2>;
  128. interrupt-controller;
  129. };
  130. gpio5: gpio@480b6000 {
  131. compatible = "ti,omap2-gpio";
  132. reg = <0x480b6000 0x200>;
  133. interrupts = <33>;
  134. ti,hwmods = "gpio5";
  135. #gpio-cells = <2>;
  136. gpio-controller;
  137. #interrupt-cells = <2>;
  138. interrupt-controller;
  139. };
  140. gpmc: gpmc@6e000000 {
  141. compatible = "ti,omap2430-gpmc";
  142. reg = <0x6e000000 0x1000>;
  143. #address-cells = <2>;
  144. #size-cells = <1>;
  145. interrupts = <20>;
  146. gpmc,num-cs = <8>;
  147. gpmc,num-waitpins = <4>;
  148. ti,hwmods = "gpmc";
  149. interrupt-controller;
  150. #interrupt-cells = <2>;
  151. gpio-controller;
  152. #gpio-cells = <2>;
  153. };
  154. mcbsp1: mcbsp@48074000 {
  155. compatible = "ti,omap2430-mcbsp";
  156. reg = <0x48074000 0xff>;
  157. reg-names = "mpu";
  158. interrupts = <64>, /* OCP compliant interrupt */
  159. <59>, /* TX interrupt */
  160. <60>, /* RX interrupt */
  161. <61>; /* RX overflow interrupt */
  162. interrupt-names = "common", "tx", "rx", "rx_overflow";
  163. ti,buffer-size = <128>;
  164. ti,hwmods = "mcbsp1";
  165. dmas = <&sdma 31>,
  166. <&sdma 32>;
  167. dma-names = "tx", "rx";
  168. status = "disabled";
  169. };
  170. mcbsp2: mcbsp@48076000 {
  171. compatible = "ti,omap2430-mcbsp";
  172. reg = <0x48076000 0xff>;
  173. reg-names = "mpu";
  174. interrupts = <16>, /* OCP compliant interrupt */
  175. <62>, /* TX interrupt */
  176. <63>; /* RX interrupt */
  177. interrupt-names = "common", "tx", "rx";
  178. ti,buffer-size = <128>;
  179. ti,hwmods = "mcbsp2";
  180. dmas = <&sdma 33>,
  181. <&sdma 34>;
  182. dma-names = "tx", "rx";
  183. status = "disabled";
  184. };
  185. mcbsp3: mcbsp@4808c000 {
  186. compatible = "ti,omap2430-mcbsp";
  187. reg = <0x4808c000 0xff>;
  188. reg-names = "mpu";
  189. interrupts = <17>, /* OCP compliant interrupt */
  190. <89>, /* TX interrupt */
  191. <90>; /* RX interrupt */
  192. interrupt-names = "common", "tx", "rx";
  193. ti,buffer-size = <128>;
  194. ti,hwmods = "mcbsp3";
  195. dmas = <&sdma 17>,
  196. <&sdma 18>;
  197. dma-names = "tx", "rx";
  198. status = "disabled";
  199. };
  200. mcbsp4: mcbsp@4808e000 {
  201. compatible = "ti,omap2430-mcbsp";
  202. reg = <0x4808e000 0xff>;
  203. reg-names = "mpu";
  204. interrupts = <18>, /* OCP compliant interrupt */
  205. <54>, /* TX interrupt */
  206. <55>; /* RX interrupt */
  207. interrupt-names = "common", "tx", "rx";
  208. ti,buffer-size = <128>;
  209. ti,hwmods = "mcbsp4";
  210. dmas = <&sdma 19>,
  211. <&sdma 20>;
  212. dma-names = "tx", "rx";
  213. status = "disabled";
  214. };
  215. mcbsp5: mcbsp@48096000 {
  216. compatible = "ti,omap2430-mcbsp";
  217. reg = <0x48096000 0xff>;
  218. reg-names = "mpu";
  219. interrupts = <19>, /* OCP compliant interrupt */
  220. <81>, /* TX interrupt */
  221. <82>; /* RX interrupt */
  222. interrupt-names = "common", "tx", "rx";
  223. ti,buffer-size = <128>;
  224. ti,hwmods = "mcbsp5";
  225. dmas = <&sdma 21>,
  226. <&sdma 22>;
  227. dma-names = "tx", "rx";
  228. status = "disabled";
  229. };
  230. mmc1: mmc@4809c000 {
  231. compatible = "ti,omap2-hsmmc";
  232. reg = <0x4809c000 0x200>;
  233. interrupts = <83>;
  234. ti,hwmods = "mmc1";
  235. ti,dual-volt;
  236. dmas = <&sdma 61>, <&sdma 62>;
  237. dma-names = "tx", "rx";
  238. pbias-supply = <&pbias_mmc_reg>;
  239. };
  240. mmc2: mmc@480b4000 {
  241. compatible = "ti,omap2-hsmmc";
  242. reg = <0x480b4000 0x200>;
  243. interrupts = <86>;
  244. ti,hwmods = "mmc2";
  245. dmas = <&sdma 47>, <&sdma 48>;
  246. dma-names = "tx", "rx";
  247. };
  248. mailbox: mailbox@48094000 {
  249. compatible = "ti,omap2-mailbox";
  250. reg = <0x48094000 0x200>;
  251. interrupts = <26>;
  252. ti,hwmods = "mailbox";
  253. #mbox-cells = <1>;
  254. ti,mbox-num-users = <4>;
  255. ti,mbox-num-fifos = <6>;
  256. mbox_dsp: mbox-dsp {
  257. ti,mbox-tx = <0 0 0>;
  258. ti,mbox-rx = <1 0 0>;
  259. };
  260. };
  261. timer1_target: target-module@49018000 {
  262. compatible = "ti,sysc-omap2-timer", "ti,sysc";
  263. reg = <0x49018000 0x4>,
  264. <0x49018010 0x4>,
  265. <0x49018014 0x4>;
  266. reg-names = "rev", "sysc", "syss";
  267. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  268. SYSC_OMAP2_EMUFREE |
  269. SYSC_OMAP2_ENAWAKEUP |
  270. SYSC_OMAP2_SOFTRESET |
  271. SYSC_OMAP2_AUTOIDLE)>;
  272. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  273. <SYSC_IDLE_NO>,
  274. <SYSC_IDLE_SMART>;
  275. ti,syss-mask = <1>;
  276. clocks = <&gpt1_fck>, <&gpt1_ick>;
  277. clock-names = "fck", "ick";
  278. #address-cells = <1>;
  279. #size-cells = <1>;
  280. ranges = <0x0 0x49018000 0x1000>;
  281. timer1: timer@0 {
  282. compatible = "ti,omap2420-timer";
  283. reg = <0 0x400>;
  284. interrupts = <37>;
  285. ti,timer-alwon;
  286. };
  287. };
  288. mcspi3: spi@480b8000 {
  289. compatible = "ti,omap2-mcspi";
  290. ti,hwmods = "mcspi3";
  291. reg = <0x480b8000 0x100>;
  292. interrupts = <91>;
  293. dmas = <&sdma 15 &sdma 16 &sdma 23 &sdma 24>;
  294. dma-names = "tx0", "rx0", "tx1", "rx1";
  295. };
  296. usb_otg_hs: usb_otg_hs@480ac000 {
  297. compatible = "ti,omap2-musb";
  298. ti,hwmods = "usb_otg_hs";
  299. reg = <0x480ac000 0x1000>;
  300. interrupts = <93>;
  301. };
  302. wd_timer2: wdt@49016000 {
  303. compatible = "ti,omap2-wdt";
  304. ti,hwmods = "wd_timer2";
  305. reg = <0x49016000 0x80>;
  306. };
  307. };
  308. };
  309. &sdma {
  310. compatible = "ti,omap2430-sdma", "ti,omap-sdma";
  311. };
  312. &i2c1 {
  313. compatible = "ti,omap2430-i2c";
  314. };
  315. &i2c2 {
  316. compatible = "ti,omap2430-i2c";
  317. };
  318. #include "omap24xx-clocks.dtsi"
  319. #include "omap2430-clocks.dtsi"
  320. /* Preferred always-on timer for clockevent */
  321. &timer1_target {
  322. ti,no-reset-on-init;
  323. ti,no-idle;
  324. timer@0 {
  325. assigned-clocks = <&gpt1_fck>;
  326. assigned-clock-parents = <&func_32k_ck>;
  327. };
  328. };