nuvoton-npcm750-evb.dts 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2018 Nuvoton Technology [email protected]
  3. // Copyright 2018 Google, Inc.
  4. /dts-v1/;
  5. #include "nuvoton-npcm750.dtsi"
  6. #include "dt-bindings/gpio/gpio.h"
  7. #include "nuvoton-npcm750-pincfg-evb.dtsi"
  8. / {
  9. model = "Nuvoton npcm750 Development Board (Device Tree)";
  10. compatible = "nuvoton,npcm750-evb", "nuvoton,npcm750";
  11. aliases {
  12. ethernet2 = &gmac0;
  13. ethernet3 = &gmac1;
  14. serial0 = &serial0;
  15. serial1 = &serial1;
  16. serial2 = &serial2;
  17. serial3 = &serial3;
  18. i2c0 = &i2c0;
  19. i2c1 = &i2c1;
  20. i2c2 = &i2c2;
  21. i2c3 = &i2c3;
  22. i2c4 = &i2c4;
  23. i2c5 = &i2c5;
  24. i2c6 = &i2c6;
  25. i2c7 = &i2c7;
  26. i2c8 = &i2c8;
  27. i2c9 = &i2c9;
  28. i2c10 = &i2c10;
  29. i2c11 = &i2c11;
  30. i2c12 = &i2c12;
  31. i2c13 = &i2c13;
  32. i2c14 = &i2c14;
  33. i2c15 = &i2c15;
  34. spi0 = &spi0;
  35. spi1 = &spi1;
  36. fiu0 = &fiu0;
  37. fiu1 = &fiu3;
  38. fiu2 = &fiux;
  39. };
  40. chosen {
  41. stdout-path = &serial3;
  42. };
  43. memory {
  44. device_type = "memory";
  45. reg = <0x0 0x20000000>;
  46. };
  47. };
  48. &gmac0 {
  49. phy-mode = "rgmii-id";
  50. status = "okay";
  51. };
  52. &gmac1 {
  53. phy-mode = "rgmii-id";
  54. status = "okay";
  55. };
  56. &ehci1 {
  57. status = "okay";
  58. };
  59. &fiu0 {
  60. status = "okay";
  61. flash@0 {
  62. compatible = "jedec,spi-nor";
  63. #address-cells = <1>;
  64. #size-cells = <1>;
  65. spi-rx-bus-width = <2>;
  66. reg = <0>;
  67. spi-max-frequency = <5000000>;
  68. partitions {
  69. compatible = "fixed-partitions";
  70. #address-cells = <1>;
  71. #size-cells = <1>;
  72. bbuboot1@0 {
  73. label = "bb-uboot-1";
  74. reg = <0x0000000 0x80000>;
  75. read-only;
  76. };
  77. bbuboot2@80000 {
  78. label = "bb-uboot-2";
  79. reg = <0x0080000 0x80000>;
  80. read-only;
  81. };
  82. envparam@100000 {
  83. label = "env-param";
  84. reg = <0x0100000 0x40000>;
  85. read-only;
  86. };
  87. spare@140000 {
  88. label = "spare";
  89. reg = <0x0140000 0xC0000>;
  90. };
  91. kernel@200000 {
  92. label = "kernel";
  93. reg = <0x0200000 0x400000>;
  94. };
  95. rootfs@600000 {
  96. label = "rootfs";
  97. reg = <0x0600000 0x700000>;
  98. };
  99. spare1@d00000 {
  100. label = "spare1";
  101. reg = <0x0D00000 0x200000>;
  102. };
  103. spare2@f00000 {
  104. label = "spare2";
  105. reg = <0x0F00000 0x200000>;
  106. };
  107. spare3@1100000 {
  108. label = "spare3";
  109. reg = <0x1100000 0x200000>;
  110. };
  111. spare4@1300000 {
  112. label = "spare4";
  113. reg = <0x1300000 0x0>;
  114. };
  115. };
  116. };
  117. };
  118. &fiu3 {
  119. pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>;
  120. status = "okay";
  121. flash@0 {
  122. compatible = "jedec,spi-nor";
  123. #address-cells = <1>;
  124. #size-cells = <1>;
  125. spi-rx-bus-width = <2>;
  126. reg = <0>;
  127. spi-max-frequency = <5000000>;
  128. partitions {
  129. compatible = "fixed-partitions";
  130. #address-cells = <1>;
  131. #size-cells = <1>;
  132. system1@0 {
  133. label = "spi3-system1";
  134. reg = <0x0 0x0>;
  135. };
  136. };
  137. };
  138. };
  139. &fiux {
  140. spix-mode;
  141. };
  142. &watchdog1 {
  143. status = "okay";
  144. };
  145. &rng {
  146. status = "okay";
  147. };
  148. &serial0 {
  149. status = "okay";
  150. };
  151. &serial1 {
  152. status = "okay";
  153. };
  154. &serial2 {
  155. status = "okay";
  156. };
  157. &serial3 {
  158. status = "okay";
  159. };
  160. &adc {
  161. status = "okay";
  162. };
  163. &lpc_kcs {
  164. kcs1: kcs1@0 {
  165. status = "okay";
  166. };
  167. kcs2: kcs2@0 {
  168. status = "okay";
  169. };
  170. kcs3: kcs3@0 {
  171. status = "okay";
  172. };
  173. };
  174. /* lm75 on SVB */
  175. &i2c0 {
  176. clock-frequency = <100000>;
  177. status = "okay";
  178. lm75@48 {
  179. compatible = "lm75";
  180. reg = <0x48>;
  181. status = "okay";
  182. };
  183. };
  184. /* lm75 on EB */
  185. &i2c1 {
  186. clock-frequency = <100000>;
  187. status = "okay";
  188. lm75@48 {
  189. compatible = "lm75";
  190. reg = <0x48>;
  191. status = "okay";
  192. };
  193. };
  194. /* tmp100 on EB */
  195. &i2c2 {
  196. clock-frequency = <100000>;
  197. status = "okay";
  198. tmp100@48 {
  199. compatible = "tmp100";
  200. reg = <0x48>;
  201. status = "okay";
  202. };
  203. };
  204. &i2c3 {
  205. clock-frequency = <100000>;
  206. status = "okay";
  207. };
  208. &i2c5 {
  209. clock-frequency = <100000>;
  210. status = "okay";
  211. };
  212. /* tmp100 on SVB */
  213. &i2c6 {
  214. clock-frequency = <100000>;
  215. status = "okay";
  216. tmp100@48 {
  217. compatible = "tmp100";
  218. reg = <0x48>;
  219. status = "okay";
  220. };
  221. };
  222. &i2c7 {
  223. clock-frequency = <100000>;
  224. status = "okay";
  225. };
  226. &i2c8 {
  227. clock-frequency = <100000>;
  228. status = "okay";
  229. };
  230. &i2c9 {
  231. clock-frequency = <100000>;
  232. status = "okay";
  233. };
  234. &i2c10 {
  235. clock-frequency = <100000>;
  236. status = "okay";
  237. };
  238. &i2c11 {
  239. clock-frequency = <100000>;
  240. status = "okay";
  241. };
  242. &i2c14 {
  243. clock-frequency = <100000>;
  244. status = "okay";
  245. };
  246. &pwm_fan {
  247. status = "okay";
  248. fan@0 {
  249. reg = <0x00>;
  250. fan-tach-ch = /bits/ 8 <0x00 0x01>;
  251. cooling-levels = <127 255>;
  252. };
  253. fan@1 {
  254. reg = <0x01>;
  255. fan-tach-ch = /bits/ 8 <0x02 0x03>;
  256. cooling-levels = /bits/ 8 <127 255>;
  257. };
  258. fan@2 {
  259. reg = <0x02>;
  260. fan-tach-ch = /bits/ 8 <0x04 0x05>;
  261. cooling-levels = /bits/ 8 <127 255>;
  262. };
  263. fan@3 {
  264. reg = <0x03>;
  265. fan-tach-ch = /bits/ 8 <0x06 0x07>;
  266. cooling-levels = /bits/ 8 <127 255>;
  267. };
  268. fan@4 {
  269. reg = <0x04>;
  270. fan-tach-ch = /bits/ 8 <0x08 0x09>;
  271. cooling-levels = /bits/ 8 <127 255>;
  272. };
  273. fan@5 {
  274. reg = <0x05>;
  275. fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
  276. cooling-levels = /bits/ 8 <127 255>;
  277. };
  278. fan@6 {
  279. reg = <0x06>;
  280. fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
  281. cooling-levels = /bits/ 8 <127 255>;
  282. };
  283. fan@7 {
  284. reg = <0x07>;
  285. fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
  286. cooling-levels = /bits/ 8 <127 255>;
  287. };
  288. };
  289. &spi0 {
  290. cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
  291. status = "okay";
  292. flash@0 {
  293. compatible = "winbond,w25q128",
  294. "jedec,spi-nor";
  295. reg = <0x0>;
  296. #address-cells = <1>;
  297. #size-cells = <1>;
  298. spi-max-frequency = <5000000>;
  299. partition@0 {
  300. label = "spi0_spare1";
  301. reg = <0x0000000 0x800000>;
  302. };
  303. partition@1 {
  304. label = "spi0_spare2";
  305. reg = <0x800000 0x0>;
  306. };
  307. };
  308. };
  309. &spi1 {
  310. cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
  311. status = "okay";
  312. flash@0 {
  313. compatible = "winbond,w25q128fw",
  314. "jedec,spi-nor";
  315. reg = <0x0>;
  316. #address-cells = <1>;
  317. #size-cells = <1>;
  318. spi-max-frequency = <5000000>;
  319. partition@0 {
  320. label = "spi1_spare1";
  321. reg = <0x0000000 0x800000>;
  322. };
  323. partition@1 {
  324. label = "spi1_spare2";
  325. reg = <0x800000 0x0>;
  326. };
  327. };
  328. };
  329. &pinctrl {
  330. pinctrl-names = "default";
  331. pinctrl-0 = < &iox1_pins
  332. &pin8_input
  333. &pin9_output_high
  334. &pin10_input
  335. &pin11_output_high
  336. &pin16_input
  337. &pin24_output_high
  338. &pin25_output_low
  339. &pin32_output_high
  340. &jtag2_pins
  341. &pin61_output_high
  342. &pin62_output_high
  343. &pin63_output_high
  344. &lpc_pins
  345. &pin160_input
  346. &pin162_input
  347. &pin168_input
  348. &pin169_input
  349. &pin170_input
  350. &pin187_output_high
  351. &pin190_input
  352. &pin191_output_high
  353. &pin192_output_high
  354. &pin197_output_low
  355. &ddc_pins
  356. &pin218_input
  357. &pin219_output_low
  358. &pin220_output_low
  359. &pin221_output_high
  360. &pin222_input
  361. &pin223_output_low
  362. &spix_pins
  363. &pin228_output_low
  364. &pin231_output_high
  365. &pin255_input>;
  366. };