nuvoton-npcm730-gsj.dts 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2019 Quanta Computer lnc. [email protected]
  3. /dts-v1/;
  4. #include "nuvoton-npcm730.dtsi"
  5. #include "nuvoton-npcm730-gsj-gpio.dtsi"
  6. #include <dt-bindings/gpio/gpio.h>
  7. / {
  8. model = "Quanta GSJ Board (Device Tree v12)";
  9. compatible = "nuvoton,npcm750";
  10. aliases {
  11. ethernet1 = &gmac0;
  12. serial3 = &serial3;
  13. i2c1 = &i2c1;
  14. i2c2 = &i2c2;
  15. i2c3 = &i2c3;
  16. i2c4 = &i2c4;
  17. i2c8 = &i2c8;
  18. i2c9 = &i2c9;
  19. i2c10 = &i2c10;
  20. i2c11 = &i2c11;
  21. i2c12 = &i2c12;
  22. i2c15 = &i2c15;
  23. fiu0 = &fiu0;
  24. };
  25. chosen {
  26. stdout-path = &serial3;
  27. };
  28. memory {
  29. reg = <0 0x40000000>;
  30. };
  31. leds {
  32. compatible = "gpio-leds";
  33. led-bmc-live {
  34. gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
  35. linux,default-trigger = "heartbeat";
  36. };
  37. LED_U2_0_LOCATE {
  38. gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
  39. default-state = "off";
  40. };
  41. LED_U2_1_LOCATE {
  42. gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
  43. default-state = "off";
  44. };
  45. LED_U2_2_LOCATE {
  46. gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
  47. default-state = "off";
  48. };
  49. LED_U2_3_LOCATE {
  50. gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
  51. default-state = "off";
  52. };
  53. LED_U2_4_LOCATE {
  54. gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
  55. default-state = "off";
  56. };
  57. LED_U2_5_LOCATE {
  58. gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
  59. default-state = "off";
  60. };
  61. LED_BMC_TRAY_PWRGD {
  62. gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
  63. default-state = "off";
  64. };
  65. LED_U2_7_FAULT {
  66. gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
  67. default-state = "off";
  68. };
  69. LED_U2_6_LOCATE {
  70. gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
  71. default-state = "off";
  72. };
  73. LED_U2_7_LOCATE {
  74. gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
  75. default-state = "off";
  76. };
  77. LED_U2_0_FAULT {
  78. gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
  79. default-state = "off";
  80. };
  81. LED_U2_1_FAULT {
  82. gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
  83. default-state = "off";
  84. };
  85. LED_U2_2_FAULT {
  86. gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
  87. default-state = "off";
  88. };
  89. LED_U2_3_FAULT {
  90. gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
  91. default-state = "off";
  92. };
  93. LED_U2_4_FAULT {
  94. gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
  95. default-state = "off";
  96. };
  97. LED_U2_5_FAULT {
  98. gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
  99. default-state = "off";
  100. };
  101. LED_U2_6_FAULT {
  102. gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
  103. default-state = "off";
  104. };
  105. };
  106. };
  107. &fiu0 {
  108. pinctrl-names = "default";
  109. pinctrl-0 = <&spi0cs1_pins>;
  110. status = "okay";
  111. flash@0 {
  112. compatible = "jedec,spi-nor";
  113. #address-cells = <1>;
  114. #size-cells = <1>;
  115. reg = <0>;
  116. spi-rx-bus-width = <2>;
  117. partitions {
  118. compatible = "fixed-partitions";
  119. #address-cells = <1>;
  120. #size-cells = <1>;
  121. bmc@0{
  122. label = "bmc";
  123. reg = <0x000000 0x2000000>;
  124. };
  125. u-boot@0 {
  126. label = "u-boot";
  127. reg = <0x0000000 0x80000>;
  128. read-only;
  129. };
  130. u-boot-env@100000{
  131. label = "u-boot-env";
  132. reg = <0x00100000 0x40000>;
  133. };
  134. kernel@200000 {
  135. label = "kernel";
  136. reg = <0x0200000 0x600000>;
  137. };
  138. rofs@800000 {
  139. label = "rofs";
  140. reg = <0x800000 0x1400000>;
  141. };
  142. rwfs@1c00000 {
  143. label = "rwfs";
  144. reg = <0x1c00000 0x300000>;
  145. };
  146. reserved@1f00000 {
  147. label = "reserved";
  148. reg = <0x1f00000 0x100000>;
  149. };
  150. };
  151. };
  152. };
  153. &gmac0 {
  154. phy-mode = "rgmii-id";
  155. status = "okay";
  156. };
  157. &ehci1 {
  158. status = "okay";
  159. };
  160. &watchdog1 {
  161. status = "okay";
  162. };
  163. &rng {
  164. status = "okay";
  165. };
  166. &serial0 {
  167. status = "okay";
  168. };
  169. &serial1 {
  170. status = "okay";
  171. };
  172. &serial2 {
  173. status = "okay";
  174. };
  175. &serial3 {
  176. status = "okay";
  177. };
  178. &adc {
  179. status = "okay";
  180. };
  181. &i2c1 {
  182. status = "okay";
  183. lm75@5c {
  184. compatible = "maxim,max31725";
  185. reg = <0x5c>;
  186. status = "okay";
  187. };
  188. };
  189. &i2c2 {
  190. status = "okay";
  191. lm75@5c {
  192. compatible = "maxim,max31725";
  193. reg = <0x5c>;
  194. status = "okay";
  195. };
  196. };
  197. &i2c3 {
  198. status = "okay";
  199. lm75@5c {
  200. compatible = "maxim,max31725";
  201. reg = <0x5c>;
  202. };
  203. };
  204. &i2c4 {
  205. status = "okay";
  206. lm75@5c {
  207. compatible = "maxim,max31725";
  208. reg = <0x5c>;
  209. };
  210. };
  211. &i2c8 {
  212. status = "okay";
  213. };
  214. &i2c9 {
  215. status = "okay";
  216. eeprom@55 {
  217. compatible = "atmel,24c64";
  218. reg = <0x55>;
  219. };
  220. };
  221. &i2c10 {
  222. status = "okay";
  223. eeprom@55 {
  224. compatible = "atmel,24c64";
  225. reg = <0x55>;
  226. };
  227. };
  228. &i2c11 {
  229. status = "okay";
  230. /* P12V Quarter Brick DC/DC Power Module Q54SH12050 @60 */
  231. power-brick@36 {
  232. compatible = "delta,dps800";
  233. reg = <0x36>;
  234. };
  235. hotswap@15 {
  236. compatible = "ti,lm5066i";
  237. reg = <0x15>;
  238. };
  239. };
  240. &i2c12 {
  241. status = "okay";
  242. ucd90160@6b {
  243. compatible = "ti,ucd90160";
  244. reg = <0x6b>;
  245. };
  246. };
  247. &i2c15 {
  248. status = "okay";
  249. i2c-switch@75 {
  250. compatible = "nxp,pca9548";
  251. #address-cells = <1>;
  252. #size-cells = <0>;
  253. reg = <0x75>;
  254. i2c-mux-idle-disconnect;
  255. i2c_u20: i2c@0 {
  256. #address-cells = <1>;
  257. #size-cells = <0>;
  258. reg = <0>;
  259. };
  260. i2c_u21: i2c@1 {
  261. #address-cells = <1>;
  262. #size-cells = <0>;
  263. reg = <1>;
  264. };
  265. i2c_u22: i2c@2 {
  266. #address-cells = <1>;
  267. #size-cells = <0>;
  268. reg = <2>;
  269. };
  270. i2c_u23: i2c@3 {
  271. #address-cells = <1>;
  272. #size-cells = <0>;
  273. reg = <3>;
  274. };
  275. i2c_u24: i2c@4 {
  276. #address-cells = <1>;
  277. #size-cells = <0>;
  278. reg = <4>;
  279. };
  280. i2c_u25: i2c@5 {
  281. #address-cells = <1>;
  282. #size-cells = <0>;
  283. reg = <5>;
  284. };
  285. i2c_u26: i2c@6 {
  286. #address-cells = <1>;
  287. #size-cells = <0>;
  288. reg = <6>;
  289. };
  290. i2c_u27: i2c@7 {
  291. #address-cells = <1>;
  292. #size-cells = <0>;
  293. reg = <7>;
  294. };
  295. };
  296. };
  297. &pwm_fan {
  298. pinctrl-names = "default";
  299. pinctrl-0 = <&pwm0_pins &pwm1_pins &pwm2_pins
  300. &fanin0_pins &fanin1_pins
  301. &fanin2_pins &fanin3_pins
  302. &fanin4_pins &fanin5_pins>;
  303. status = "okay";
  304. fan@0 {
  305. reg = <0x00>;
  306. fan-tach-ch = /bits/ 8 <0x00 0x01>;
  307. cooling-levels = <127 255>;
  308. };
  309. fan@1 {
  310. reg = <0x01>;
  311. fan-tach-ch = /bits/ 8 <0x02 0x03>;
  312. cooling-levels = /bits/ 8 <127 255>;
  313. };
  314. fan@2 {
  315. reg = <0x02>;
  316. fan-tach-ch = /bits/ 8 <0x04 0x05>;
  317. cooling-levels = /bits/ 8 <127 255>;
  318. };
  319. };
  320. &pinctrl {
  321. pinctrl-names = "default";
  322. pinctrl-0 = <
  323. /* GPI pins*/
  324. &gpio8_pins
  325. &gpio9_pins
  326. &gpio12_pins
  327. &gpio13_pins
  328. &gpio14_pins
  329. &gpio60_pins
  330. &gpio83_pins
  331. &gpio91_pins
  332. &gpio92_pins
  333. &gpio95_pins
  334. &gpio136_pins
  335. &gpio137_pins
  336. &gpio141_pins
  337. &gpio144_pins
  338. &gpio145_pins
  339. &gpio146_pins
  340. &gpio147_pins
  341. &gpio148_pins
  342. &gpio149_pins
  343. &gpio150_pins
  344. &gpio151_pins
  345. &gpio152_pins
  346. &gpio153_pins
  347. &gpio154_pins
  348. &gpio155_pins
  349. &gpio156_pins
  350. &gpio157_pins
  351. &gpio158_pins
  352. &gpio159_pins
  353. &gpio161_pins
  354. &gpio162_pins
  355. &gpio163_pins
  356. &gpio164_pins
  357. &gpio165_pins
  358. &gpio166_pins
  359. &gpio167_pins
  360. &gpio168_pins
  361. &gpio169_pins
  362. &gpio170_pins
  363. &gpio177_pins
  364. &gpio191_pins
  365. &gpio192_pins
  366. &gpio203_pins
  367. /* GPO pins*/
  368. &gpio0pp_pins
  369. &gpio1pp_pins
  370. &gpio2pp_pins
  371. &gpio3pp_pins
  372. &gpio4pp_pins
  373. &gpio5pp_pins
  374. &gpio6pp_pins
  375. &gpio7pp_pins
  376. &gpio10pp_pins
  377. &gpio11pp_pins
  378. &gpio15od_pins
  379. &gpio17pp_pins
  380. &gpio18pp_pins
  381. &gpio19pp_pins
  382. &gpio24pp_pins
  383. &gpio25pp_pins
  384. &gpio37od_pins
  385. &gpio59pp_pins
  386. &gpio72od_pins
  387. &gpio73od_pins
  388. &gpio74od_pins
  389. &gpio75od_pins
  390. &gpio76od_pins
  391. &gpio77od_pins
  392. &gpio78od_pins
  393. &gpio79od_pins
  394. &gpio84pp_pins
  395. &gpio85pp_pins
  396. &gpio86pp_pins
  397. &gpio87pp_pins
  398. &gpio88pp_pins
  399. &gpio89pp_pins
  400. &gpio90pp_pins
  401. &gpio93pp_pins
  402. &gpio94pp_pins
  403. &gpio125pp_pins
  404. &gpio126od_pins
  405. &gpio127od_pins
  406. &gpio142od_pins
  407. &gpio143ol_pins
  408. &gpio175od_pins
  409. &gpio176od_pins
  410. &gpio190od_pins
  411. &gpio194pp_pins
  412. &gpio195od_pins
  413. &gpio196od_pins
  414. &gpio197od_pins
  415. &gpio198od_pins
  416. &gpio199od_pins
  417. &gpio200pp_pins
  418. &gpio202od_pins
  419. >;
  420. };