mt6580.dtsi 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2015 MediaTek Inc.
  4. * Author: Mars.C <[email protected]>
  5. *
  6. */
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. #include <dt-bindings/interrupt-controller/arm-gic.h>
  9. / {
  10. compatible = "mediatek,mt6580";
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. interrupt-parent = <&sysirq>;
  14. cpus {
  15. #address-cells = <1>;
  16. #size-cells = <0>;
  17. cpu@0 {
  18. device_type = "cpu";
  19. compatible = "arm,cortex-a7";
  20. reg = <0x0>;
  21. };
  22. cpu@1 {
  23. device_type = "cpu";
  24. compatible = "arm,cortex-a7";
  25. reg = <0x1>;
  26. };
  27. cpu@2 {
  28. device_type = "cpu";
  29. compatible = "arm,cortex-a7";
  30. reg = <0x2>;
  31. };
  32. cpu@3 {
  33. device_type = "cpu";
  34. compatible = "arm,cortex-a7";
  35. reg = <0x3>;
  36. };
  37. };
  38. system_clk: dummy13m {
  39. compatible = "fixed-clock";
  40. clock-frequency = <13000000>;
  41. #clock-cells = <0>;
  42. };
  43. rtc_clk: dummy32k {
  44. compatible = "fixed-clock";
  45. clock-frequency = <32000>;
  46. #clock-cells = <0>;
  47. };
  48. uart_clk: dummy26m {
  49. compatible = "fixed-clock";
  50. clock-frequency = <26000000>;
  51. #clock-cells = <0>;
  52. };
  53. timer: timer@10008000 {
  54. compatible = "mediatek,mt6580-timer",
  55. "mediatek,mt6577-timer";
  56. reg = <0x10008000 0x80>;
  57. interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
  58. clocks = <&system_clk>, <&rtc_clk>;
  59. clock-names = "system-clk", "rtc-clk";
  60. };
  61. sysirq: interrupt-controller@10200100 {
  62. compatible = "mediatek,mt6580-sysirq",
  63. "mediatek,mt6577-sysirq";
  64. interrupt-controller;
  65. #interrupt-cells = <3>;
  66. interrupt-parent = <&gic>;
  67. reg = <0x10200100 0x1c>;
  68. };
  69. gic: interrupt-controller@10211000 {
  70. compatible = "arm,cortex-a7-gic";
  71. interrupt-controller;
  72. #interrupt-cells = <3>;
  73. interrupt-parent = <&gic>;
  74. reg = <0x10211000 0x1000>,
  75. <0x10212000 0x2000>,
  76. <0x10214000 0x2000>,
  77. <0x10216000 0x2000>;
  78. };
  79. uart0: serial@11005000 {
  80. compatible = "mediatek,mt6580-uart",
  81. "mediatek,mt6577-uart";
  82. reg = <0x11005000 0x400>;
  83. interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
  84. clocks = <&uart_clk>;
  85. status = "disabled";
  86. };
  87. uart1: serial@11006000 {
  88. compatible = "mediatek,mt6580-uart",
  89. "mediatek,mt6577-uart";
  90. reg = <0x11006000 0x400>;
  91. interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
  92. clocks = <&uart_clk>;
  93. status = "disabled";
  94. };
  95. };