moxart.dtsi 3.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* moxart.dtsi - Device Tree Include file for MOXA ART family SoC
  3. *
  4. * Copyright (C) 2013 Jonas Jensen <[email protected]>
  5. */
  6. #include <dt-bindings/interrupt-controller/irq.h>
  7. / {
  8. #address-cells = <1>;
  9. #size-cells = <1>;
  10. compatible = "moxa,moxart";
  11. model = "MOXART";
  12. interrupt-parent = <&intc>;
  13. cpus {
  14. #address-cells = <1>;
  15. #size-cells = <0>;
  16. cpu@0 {
  17. device_type = "cpu";
  18. compatible = "faraday,fa526";
  19. reg = <0>;
  20. };
  21. };
  22. clocks {
  23. #address-cells = <1>;
  24. #size-cells = <0>;
  25. };
  26. soc {
  27. compatible = "simple-bus";
  28. #address-cells = <1>;
  29. #size-cells = <1>;
  30. reg = <0x90000000 0x10000000>;
  31. ranges;
  32. intc: interrupt-controller@98800000 {
  33. compatible = "moxa,moxart-ic", "faraday,ftintc010";
  34. reg = <0x98800000 0x100>;
  35. interrupt-controller;
  36. #interrupt-cells = <2>;
  37. interrupt-mask = <0x00080000>;
  38. };
  39. clk_pll: clk_pll@98100000 {
  40. compatible = "moxa,moxart-pll-clock";
  41. #clock-cells = <0>;
  42. reg = <0x98100000 0x34>;
  43. };
  44. clk_apb: clk_apb@98100000 {
  45. compatible = "moxa,moxart-apb-clock";
  46. #clock-cells = <0>;
  47. reg = <0x98100000 0x34>;
  48. clocks = <&clk_pll>;
  49. };
  50. timer: timer@98400000 {
  51. compatible = "moxa,moxart-timer", "faraday,fttmr010";
  52. reg = <0x98400000 0x42>;
  53. interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
  54. clocks = <&clk_apb>;
  55. clock-names = "PCLK";
  56. };
  57. gpio: gpio@98700000 {
  58. gpio-controller;
  59. #gpio-cells = <2>;
  60. compatible = "moxa,moxart-gpio", "faraday,ftgpio010";
  61. reg = <0x98700000 0x100>;
  62. };
  63. rtc: rtc {
  64. compatible = "moxa,moxart-rtc";
  65. gpio-rtc-sclk = <&gpio 5 0>;
  66. gpio-rtc-data = <&gpio 6 0>;
  67. gpio-rtc-reset = <&gpio 7 0>;
  68. };
  69. dma: dma@90500000 {
  70. compatible = "moxa,moxart-dma";
  71. reg = <0x90500080 0x40>;
  72. interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
  73. #dma-cells = <1>;
  74. };
  75. watchdog: watchdog@98500000 {
  76. compatible = "moxa,moxart-watchdog", "faraday,ftwdt010";
  77. reg = <0x98500000 0x10>;
  78. clocks = <&clk_apb>;
  79. clock-names = "PCLK";
  80. };
  81. mmc: mmc@98e00000 {
  82. compatible = "moxa,moxart-mmc";
  83. reg = <0x98e00000 0x5C>;
  84. interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
  85. clocks = <&clk_apb>;
  86. dmas = <&dma 5>,
  87. <&dma 5>;
  88. dma-names = "tx", "rx";
  89. status = "disabled";
  90. };
  91. mdio0: mdio@90900090 {
  92. compatible = "moxa,moxart-mdio";
  93. reg = <0x90900090 0x8>;
  94. #address-cells = <1>;
  95. #size-cells = <0>;
  96. status = "disabled";
  97. };
  98. mdio1: mdio@92000090 {
  99. compatible = "moxa,moxart-mdio";
  100. reg = <0x92000090 0x8>;
  101. #address-cells = <1>;
  102. #size-cells = <0>;
  103. status = "disabled";
  104. };
  105. mac0: mac@90900000 {
  106. compatible = "moxa,moxart-mac";
  107. reg = <0x90900000 0x90>;
  108. interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
  109. phy-handle = <&ethphy0>;
  110. phy-mode = "mii";
  111. status = "disabled";
  112. };
  113. mac1: mac@92000000 {
  114. compatible = "moxa,moxart-mac";
  115. reg = <0x92000000 0x90>;
  116. interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
  117. phy-handle = <&ethphy1>;
  118. phy-mode = "mii";
  119. status = "disabled";
  120. };
  121. uart0: uart@98200000 {
  122. compatible = "ns16550a";
  123. reg = <0x98200000 0x20>;
  124. interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
  125. reg-shift = <2>;
  126. reg-io-width = <4>;
  127. clock-frequency = <14745600>;
  128. status = "disabled";
  129. };
  130. };
  131. };