mmp3.dtsi 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR MIT
  2. /*
  3. * Copyright (C) 2019 Lubomir Rintel <[email protected]>
  4. */
  5. #include <dt-bindings/clock/marvell,mmp2.h>
  6. #include <dt-bindings/power/marvell,mmp2.h>
  7. #include <dt-bindings/interrupt-controller/arm-gic.h>
  8. / {
  9. #address-cells = <1>;
  10. #size-cells = <1>;
  11. cpus {
  12. #address-cells = <1>;
  13. #size-cells = <0>;
  14. enable-method = "marvell,mmp3-smp";
  15. cpu@0 {
  16. compatible = "marvell,pj4b";
  17. device_type = "cpu";
  18. next-level-cache = <&l2>;
  19. reg = <0>;
  20. };
  21. cpu@1 {
  22. compatible = "marvell,pj4b";
  23. device_type = "cpu";
  24. next-level-cache = <&l2>;
  25. reg = <1>;
  26. };
  27. };
  28. soc {
  29. #address-cells = <1>;
  30. #size-cells = <1>;
  31. compatible = "simple-bus";
  32. interrupt-parent = <&gic>;
  33. ranges;
  34. axi@d4200000 {
  35. compatible = "simple-bus";
  36. #address-cells = <1>;
  37. #size-cells = <1>;
  38. reg = <0xd4200000 0x00200000>;
  39. ranges;
  40. interrupt-controller@d4282000 {
  41. compatible = "marvell,mmp3-intc";
  42. interrupt-controller;
  43. #interrupt-cells = <1>;
  44. reg = <0xd4282000 0x1000>,
  45. <0xd4284000 0x100>;
  46. mrvl,intc-nr-irqs = <64>;
  47. };
  48. pmic_mux: interrupt-controller@d4282150 {
  49. compatible = "mrvl,mmp2-mux-intc";
  50. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  51. interrupt-controller;
  52. #interrupt-cells = <1>;
  53. reg = <0x150 0x4>, <0x168 0x4>;
  54. reg-names = "mux status", "mux mask";
  55. mrvl,intc-nr-irqs = <4>;
  56. };
  57. rtc_mux: interrupt-controller@d4282154 {
  58. compatible = "mrvl,mmp2-mux-intc";
  59. interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  60. interrupt-controller;
  61. #interrupt-cells = <1>;
  62. reg = <0x154 0x4>, <0x16c 0x4>;
  63. reg-names = "mux status", "mux mask";
  64. mrvl,intc-nr-irqs = <2>;
  65. };
  66. hsi3_mux: interrupt-controller@d42821bc {
  67. compatible = "mrvl,mmp2-mux-intc";
  68. interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  69. interrupt-controller;
  70. #interrupt-cells = <1>;
  71. reg = <0x1bc 0x4>, <0x1a4 0x4>;
  72. reg-names = "mux status", "mux mask";
  73. mrvl,intc-nr-irqs = <3>;
  74. };
  75. gpu_mux: interrupt-controller@d42821c0 {
  76. compatible = "mrvl,mmp2-mux-intc";
  77. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  78. interrupt-controller;
  79. #interrupt-cells = <1>;
  80. reg = <0x1c0 0x4>, <0x1a8 0x4>;
  81. reg-names = "mux status", "mux mask";
  82. mrvl,intc-nr-irqs = <3>;
  83. };
  84. twsi_mux: interrupt-controller@d4282158 {
  85. compatible = "mrvl,mmp2-mux-intc";
  86. interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  87. interrupt-controller;
  88. #interrupt-cells = <1>;
  89. reg = <0x158 0x4>, <0x170 0x4>;
  90. reg-names = "mux status", "mux mask";
  91. mrvl,intc-nr-irqs = <5>;
  92. };
  93. hsi2_mux: interrupt-controller@d42821c4 {
  94. compatible = "mrvl,mmp2-mux-intc";
  95. interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
  96. interrupt-controller;
  97. #interrupt-cells = <1>;
  98. reg = <0x1c4 0x4>, <0x1ac 0x4>;
  99. reg-names = "mux status", "mux mask";
  100. mrvl,intc-nr-irqs = <2>;
  101. };
  102. dxo_mux: interrupt-controller@d42821c8 {
  103. compatible = "mrvl,mmp2-mux-intc";
  104. interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  105. interrupt-controller;
  106. #interrupt-cells = <1>;
  107. reg = <0x1c8 0x4>, <0x1b0 0x4>;
  108. reg-names = "mux status", "mux mask";
  109. mrvl,intc-nr-irqs = <2>;
  110. };
  111. misc1_mux: interrupt-controller@d428215c {
  112. compatible = "mrvl,mmp2-mux-intc";
  113. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  114. interrupt-controller;
  115. #interrupt-cells = <1>;
  116. reg = <0x15c 0x4>, <0x174 0x4>;
  117. reg-names = "mux status", "mux mask";
  118. mrvl,intc-nr-irqs = <31>;
  119. };
  120. ci_mux: interrupt-controller@d42821cc {
  121. compatible = "mrvl,mmp2-mux-intc";
  122. interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
  123. interrupt-controller;
  124. #interrupt-cells = <1>;
  125. reg = <0x1cc 0x4>, <0x1b4 0x4>;
  126. reg-names = "mux status", "mux mask";
  127. mrvl,intc-nr-irqs = <2>;
  128. };
  129. ssp_mux: interrupt-controller@d4282160 {
  130. compatible = "mrvl,mmp2-mux-intc";
  131. interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
  132. interrupt-controller;
  133. #interrupt-cells = <1>;
  134. reg = <0x160 0x4>, <0x178 0x4>;
  135. reg-names = "mux status", "mux mask";
  136. mrvl,intc-nr-irqs = <2>;
  137. };
  138. hsi1_mux: interrupt-controller@d4282184 {
  139. compatible = "mrvl,mmp2-mux-intc";
  140. interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
  141. interrupt-controller;
  142. #interrupt-cells = <1>;
  143. reg = <0x184 0x4>, <0x17c 0x4>;
  144. reg-names = "mux status", "mux mask";
  145. mrvl,intc-nr-irqs = <4>;
  146. };
  147. misc2_mux: interrupt-controller@d4282188 {
  148. compatible = "mrvl,mmp2-mux-intc";
  149. interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  150. interrupt-controller;
  151. #interrupt-cells = <1>;
  152. reg = <0x188 0x4>, <0x180 0x4>;
  153. reg-names = "mux status", "mux mask";
  154. mrvl,intc-nr-irqs = <20>;
  155. };
  156. hsi0_mux: interrupt-controller@d42821d0 {
  157. compatible = "mrvl,mmp2-mux-intc";
  158. interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
  159. interrupt-controller;
  160. #interrupt-cells = <1>;
  161. reg = <0x1d0 0x4>, <0x1b8 0x4>;
  162. reg-names = "mux status", "mux mask";
  163. mrvl,intc-nr-irqs = <5>;
  164. };
  165. usb_otg_phy0: usb-phy@d4207000 {
  166. compatible = "marvell,mmp3-usb-phy";
  167. reg = <0xd4207000 0x40>;
  168. #phy-cells = <0>;
  169. status = "disabled";
  170. };
  171. usb_otg0: usb@d4208000 {
  172. compatible = "marvell,pxau2o-ehci";
  173. reg = <0xd4208000 0x200>;
  174. interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  175. clocks = <&soc_clocks MMP2_CLK_USB>;
  176. clock-names = "USBCLK";
  177. phys = <&usb_otg_phy0>;
  178. phy-names = "usb";
  179. status = "disabled";
  180. };
  181. hsic_phy0: usb-phy@f0001800 {
  182. compatible = "marvell,mmp3-hsic-phy";
  183. reg = <0xf0001800 0x40>;
  184. #phy-cells = <0>;
  185. status = "disabled";
  186. };
  187. hsic0: usb@f0001000 {
  188. compatible = "marvell,pxau2o-ehci";
  189. reg = <0xf0001000 0x200>;
  190. interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
  191. clocks = <&soc_clocks MMP2_CLK_USBHSIC0>;
  192. clock-names = "USBCLK";
  193. phys = <&hsic_phy0>;
  194. phy-names = "usb";
  195. phy_type = "hsic";
  196. #address-cells = <0x01>;
  197. #size-cells = <0x00>;
  198. status = "disabled";
  199. };
  200. hsic_phy1: usb-phy@f0002800 {
  201. compatible = "marvell,mmp3-hsic-phy";
  202. reg = <0xf0002800 0x40>;
  203. #phy-cells = <0>;
  204. status = "disabled";
  205. };
  206. hsic1: usb@f0002000 {
  207. compatible = "marvell,pxau2o-ehci";
  208. reg = <0xf0002000 0x200>;
  209. interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  210. clocks = <&soc_clocks MMP2_CLK_USBHSIC1>;
  211. clock-names = "USBCLK";
  212. phys = <&hsic_phy1>;
  213. phy-names = "usb";
  214. phy_type = "hsic";
  215. #address-cells = <0x01>;
  216. #size-cells = <0x00>;
  217. status = "disabled";
  218. };
  219. mmc1: mmc@d4280000 {
  220. compatible = "mrvl,pxav3-mmc";
  221. reg = <0xd4280000 0x120>;
  222. clocks = <&soc_clocks MMP2_CLK_SDH0>;
  223. clock-names = "io";
  224. interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
  225. status = "disabled";
  226. };
  227. mmc2: mmc@d4280800 {
  228. compatible = "mrvl,pxav3-mmc";
  229. reg = <0xd4280800 0x120>;
  230. clocks = <&soc_clocks MMP2_CLK_SDH1>;
  231. clock-names = "io";
  232. interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
  233. status = "disabled";
  234. };
  235. mmc3: mmc@d4281000 {
  236. compatible = "mrvl,pxav3-mmc";
  237. reg = <0xd4281000 0x120>;
  238. clocks = <&soc_clocks MMP2_CLK_SDH2>;
  239. clock-names = "io";
  240. interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
  241. status = "disabled";
  242. };
  243. mmc4: mmc@d4281800 {
  244. compatible = "mrvl,pxav3-mmc";
  245. reg = <0xd4281800 0x120>;
  246. clocks = <&soc_clocks MMP2_CLK_SDH3>;
  247. clock-names = "io";
  248. interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
  249. status = "disabled";
  250. };
  251. mmc5: mmc@d4217000 {
  252. compatible = "mrvl,pxav3-mmc";
  253. reg = <0xd4217000 0x120>;
  254. clocks = <&soc_clocks MMP3_CLK_SDH4>;
  255. clock-names = "io";
  256. interrupt-parent = <&hsi1_mux>;
  257. interrupts = <0>;
  258. status = "disabled";
  259. };
  260. camera0: camera@d420a000 {
  261. compatible = "marvell,mmp2-ccic";
  262. reg = <0xd420a000 0x800>;
  263. interrupts = <1>;
  264. interrupt-parent = <&ci_mux>;
  265. clocks = <&soc_clocks MMP2_CLK_CCIC0>;
  266. clock-names = "axi";
  267. power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>;
  268. #clock-cells = <0>;
  269. clock-output-names = "mclk";
  270. status = "disabled";
  271. };
  272. camera1: camera@d420a800 {
  273. compatible = "marvell,mmp2-ccic";
  274. reg = <0xd420a800 0x800>;
  275. interrupts = <2>;
  276. interrupt-parent = <&ci_mux>;
  277. clocks = <&soc_clocks MMP2_CLK_CCIC1>;
  278. clock-names = "axi";
  279. power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>;
  280. #clock-cells = <0>;
  281. clock-output-names = "mclk";
  282. status = "disabled";
  283. };
  284. gpu_3d: gpu@d420d000 {
  285. compatible = "vivante,gc";
  286. reg = <0xd420d000 0x2000>;
  287. interrupt-parent = <&gpu_mux>;
  288. interrupts = <0>;
  289. status = "disabled";
  290. clocks = <&soc_clocks MMP3_CLK_GPU_3D>,
  291. <&soc_clocks MMP3_CLK_GPU_BUS>;
  292. clock-names = "core", "bus";
  293. power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
  294. };
  295. gpu_2d: gpu@d420f000 {
  296. compatible = "vivante,gc";
  297. reg = <0xd420f000 0x2000>;
  298. interrupt-parent = <&gpu_mux>;
  299. interrupts = <2>;
  300. status = "disabled";
  301. clocks = <&soc_clocks MMP3_CLK_GPU_2D>,
  302. <&soc_clocks MMP3_CLK_GPU_BUS>;
  303. clock-names = "core", "bus";
  304. power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
  305. };
  306. };
  307. apb@d4000000 {
  308. compatible = "simple-bus";
  309. #address-cells = <1>;
  310. #size-cells = <1>;
  311. reg = <0xd4000000 0x00200000>;
  312. ranges;
  313. timer: timer@d4014000 {
  314. compatible = "mrvl,mmp-timer";
  315. reg = <0xd4014000 0x100>;
  316. interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  317. clocks = <&soc_clocks MMP2_CLK_TIMER>;
  318. };
  319. uart1: serial@d4030000 {
  320. compatible = "mrvl,mmp-uart", "intel,xscale-uart";
  321. reg = <0xd4030000 0x1000>;
  322. interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
  323. clocks = <&soc_clocks MMP2_CLK_UART0>;
  324. resets = <&soc_clocks MMP2_CLK_UART0>;
  325. reg-shift = <2>;
  326. status = "disabled";
  327. };
  328. uart2: serial@d4017000 {
  329. compatible = "mrvl,mmp-uart", "intel,xscale-uart";
  330. reg = <0xd4017000 0x1000>;
  331. interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  332. clocks = <&soc_clocks MMP2_CLK_UART1>;
  333. resets = <&soc_clocks MMP2_CLK_UART1>;
  334. reg-shift = <2>;
  335. status = "disabled";
  336. };
  337. uart3: serial@d4018000 {
  338. compatible = "mrvl,mmp-uart", "intel,xscale-uart";
  339. reg = <0xd4018000 0x1000>;
  340. interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
  341. clocks = <&soc_clocks MMP2_CLK_UART2>;
  342. resets = <&soc_clocks MMP2_CLK_UART2>;
  343. reg-shift = <2>;
  344. status = "disabled";
  345. };
  346. uart4: serial@d4016000 {
  347. compatible = "mrvl,mmp-uart", "intel,xscale-uart";
  348. reg = <0xd4016000 0x1000>;
  349. interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  350. clocks = <&soc_clocks MMP2_CLK_UART3>;
  351. resets = <&soc_clocks MMP2_CLK_UART3>;
  352. reg-shift = <2>;
  353. status = "disabled";
  354. };
  355. gpio: gpio@d4019000 {
  356. compatible = "marvell,mmp2-gpio";
  357. #address-cells = <1>;
  358. #size-cells = <1>;
  359. reg = <0xd4019000 0x1000>;
  360. gpio-controller;
  361. #gpio-cells = <2>;
  362. interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
  363. interrupt-names = "gpio_mux";
  364. clocks = <&soc_clocks MMP2_CLK_GPIO>;
  365. resets = <&soc_clocks MMP2_CLK_GPIO>;
  366. interrupt-controller;
  367. #interrupt-cells = <2>;
  368. ranges;
  369. gcb0: gpio@d4019000 {
  370. reg = <0xd4019000 0x4>;
  371. };
  372. gcb1: gpio@d4019004 {
  373. reg = <0xd4019004 0x4>;
  374. };
  375. gcb2: gpio@d4019008 {
  376. reg = <0xd4019008 0x4>;
  377. };
  378. gcb3: gpio@d4019100 {
  379. reg = <0xd4019100 0x4>;
  380. };
  381. gcb4: gpio@d4019104 {
  382. reg = <0xd4019104 0x4>;
  383. };
  384. gcb5: gpio@d4019108 {
  385. reg = <0xd4019108 0x4>;
  386. };
  387. };
  388. twsi1: i2c@d4011000 {
  389. compatible = "mrvl,mmp-twsi";
  390. reg = <0xd4011000 0x70>;
  391. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  392. clocks = <&soc_clocks MMP2_CLK_TWSI0>;
  393. resets = <&soc_clocks MMP2_CLK_TWSI0>;
  394. #address-cells = <1>;
  395. #size-cells = <0>;
  396. mrvl,i2c-fast-mode;
  397. status = "disabled";
  398. };
  399. twsi2: i2c@d4031000 {
  400. compatible = "mrvl,mmp-twsi";
  401. reg = <0xd4031000 0x70>;
  402. interrupt-parent = <&twsi_mux>;
  403. interrupts = <0>;
  404. clocks = <&soc_clocks MMP2_CLK_TWSI1>;
  405. resets = <&soc_clocks MMP2_CLK_TWSI1>;
  406. #address-cells = <1>;
  407. #size-cells = <0>;
  408. status = "disabled";
  409. };
  410. twsi3: i2c@d4032000 {
  411. compatible = "mrvl,mmp-twsi";
  412. reg = <0xd4032000 0x70>;
  413. interrupt-parent = <&twsi_mux>;
  414. interrupts = <1>;
  415. clocks = <&soc_clocks MMP2_CLK_TWSI2>;
  416. resets = <&soc_clocks MMP2_CLK_TWSI2>;
  417. #address-cells = <1>;
  418. #size-cells = <0>;
  419. status = "disabled";
  420. };
  421. twsi4: i2c@d4033000 {
  422. compatible = "mrvl,mmp-twsi";
  423. reg = <0xd4033000 0x70>;
  424. interrupt-parent = <&twsi_mux>;
  425. interrupts = <2>;
  426. clocks = <&soc_clocks MMP2_CLK_TWSI3>;
  427. resets = <&soc_clocks MMP2_CLK_TWSI3>;
  428. #address-cells = <1>;
  429. #size-cells = <0>;
  430. status = "disabled";
  431. };
  432. twsi5: i2c@d4033800 {
  433. compatible = "mrvl,mmp-twsi";
  434. reg = <0xd4033800 0x70>;
  435. interrupt-parent = <&twsi_mux>;
  436. interrupts = <3>;
  437. clocks = <&soc_clocks MMP2_CLK_TWSI4>;
  438. resets = <&soc_clocks MMP2_CLK_TWSI4>;
  439. #address-cells = <1>;
  440. #size-cells = <0>;
  441. status = "disabled";
  442. };
  443. twsi6: i2c@d4034000 {
  444. compatible = "mrvl,mmp-twsi";
  445. reg = <0xd4034000 0x70>;
  446. interrupt-parent = <&twsi_mux>;
  447. interrupts = <4>;
  448. clocks = <&soc_clocks MMP2_CLK_TWSI5>;
  449. resets = <&soc_clocks MMP2_CLK_TWSI5>;
  450. #address-cells = <1>;
  451. #size-cells = <0>;
  452. status = "disabled";
  453. };
  454. rtc: rtc@d4010000 {
  455. compatible = "mrvl,mmp-rtc";
  456. reg = <0xd4010000 0x1000>;
  457. interrupts = <1>, <0>;
  458. interrupt-names = "rtc 1Hz", "rtc alarm";
  459. interrupt-parent = <&rtc_mux>;
  460. clocks = <&soc_clocks MMP2_CLK_RTC>;
  461. resets = <&soc_clocks MMP2_CLK_RTC>;
  462. status = "disabled";
  463. };
  464. ssp1: spi@d4035000 {
  465. compatible = "marvell,mmp2-ssp";
  466. reg = <0xd4035000 0x1000>;
  467. clocks = <&soc_clocks MMP2_CLK_SSP0>;
  468. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  469. #address-cells = <1>;
  470. #size-cells = <0>;
  471. status = "disabled";
  472. };
  473. ssp2: spi@d4036000 {
  474. compatible = "marvell,mmp2-ssp";
  475. reg = <0xd4036000 0x1000>;
  476. clocks = <&soc_clocks MMP2_CLK_SSP1>;
  477. interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  478. #address-cells = <1>;
  479. #size-cells = <0>;
  480. status = "disabled";
  481. };
  482. ssp3: spi@d4037000 {
  483. compatible = "marvell,mmp2-ssp";
  484. reg = <0xd4037000 0x1000>;
  485. clocks = <&soc_clocks MMP2_CLK_SSP2>;
  486. interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  487. #address-cells = <1>;
  488. #size-cells = <0>;
  489. status = "disabled";
  490. };
  491. ssp4: spi@d4039000 {
  492. compatible = "marvell,mmp2-ssp";
  493. reg = <0xd4039000 0x1000>;
  494. clocks = <&soc_clocks MMP2_CLK_SSP3>;
  495. interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
  496. #address-cells = <1>;
  497. #size-cells = <0>;
  498. status = "disabled";
  499. };
  500. };
  501. l2: cache-controller@d0020000 {
  502. compatible = "marvell,tauros3-cache", "arm,pl310-cache";
  503. reg = <0xd0020000 0x1000>;
  504. cache-unified;
  505. cache-level = <2>;
  506. };
  507. soc_clocks: clocks@d4050000 {
  508. compatible = "marvell,mmp3-clock";
  509. reg = <0xd4050000 0x2000>,
  510. <0xd4282800 0x400>,
  511. <0xd4015000 0x1000>;
  512. reg-names = "mpmu", "apmu", "apbc";
  513. #clock-cells = <1>;
  514. #reset-cells = <1>;
  515. #power-domain-cells = <1>;
  516. };
  517. snoop-control-unit@e0000000 {
  518. compatible = "arm,arm11mp-scu";
  519. reg = <0xe0000000 0x100>;
  520. };
  521. gic: interrupt-controller@e0001000 {
  522. compatible = "arm,arm11mp-gic";
  523. interrupt-controller;
  524. #interrupt-cells = <3>;
  525. reg = <0xe0001000 0x1000>,
  526. <0xe0000100 0x100>;
  527. };
  528. local-timer@e0000600 {
  529. compatible = "arm,arm11mp-twd-timer";
  530. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  531. IRQ_TYPE_EDGE_RISING)>;
  532. reg = <0xe0000600 0x20>;
  533. };
  534. watchdog@e0000620 {
  535. compatible = "arm,arm11mp-twd-wdt";
  536. reg = <0xe0000620 0x20>;
  537. interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
  538. IRQ_TYPE_EDGE_RISING)>;
  539. };
  540. };
  541. };