mmp2.dtsi 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2012 Marvell Technology Group Ltd.
  4. * Author: Haojian Zhuang <[email protected]>
  5. */
  6. #include <dt-bindings/clock/marvell,mmp2.h>
  7. #include <dt-bindings/power/marvell,mmp2.h>
  8. #include <dt-bindings/clock/marvell,mmp2-audio.h>
  9. / {
  10. #address-cells = <1>;
  11. #size-cells = <1>;
  12. aliases {
  13. serial0 = &uart1;
  14. serial1 = &uart2;
  15. serial2 = &uart3;
  16. serial3 = &uart4;
  17. i2c0 = &twsi1;
  18. i2c1 = &twsi2;
  19. };
  20. soc {
  21. #address-cells = <1>;
  22. #size-cells = <1>;
  23. compatible = "simple-bus";
  24. interrupt-parent = <&intc>;
  25. ranges;
  26. L2: l2-cache {
  27. compatible = "marvell,tauros2-cache";
  28. marvell,tauros2-cache-features = <0x3>;
  29. };
  30. axi@d4200000 { /* AXI */
  31. compatible = "mrvl,axi-bus", "simple-bus";
  32. #address-cells = <1>;
  33. #size-cells = <1>;
  34. reg = <0xd4200000 0x00200000>;
  35. ranges;
  36. gpu: gpu@d420d000 {
  37. compatible = "vivante,gc";
  38. reg = <0xd420d000 0x4000>;
  39. interrupts = <8>;
  40. status = "disabled";
  41. clocks = <&soc_clocks MMP2_CLK_GPU_3D>,
  42. <&soc_clocks MMP2_CLK_GPU_BUS>;
  43. clock-names = "core", "bus";
  44. power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
  45. };
  46. intc: interrupt-controller@d4282000 {
  47. compatible = "mrvl,mmp2-intc";
  48. interrupt-controller;
  49. #interrupt-cells = <1>;
  50. reg = <0xd4282000 0x1000>;
  51. mrvl,intc-nr-irqs = <64>;
  52. };
  53. intcmux4: interrupt-controller@d4282150 {
  54. compatible = "mrvl,mmp2-mux-intc";
  55. interrupts = <4>;
  56. interrupt-controller;
  57. #interrupt-cells = <1>;
  58. reg = <0x150 0x4>, <0x168 0x4>;
  59. reg-names = "mux status", "mux mask";
  60. mrvl,intc-nr-irqs = <2>;
  61. };
  62. intcmux5: interrupt-controller@d4282154 {
  63. compatible = "mrvl,mmp2-mux-intc";
  64. interrupts = <5>;
  65. interrupt-controller;
  66. #interrupt-cells = <1>;
  67. reg = <0x154 0x4>, <0x16c 0x4>;
  68. reg-names = "mux status", "mux mask";
  69. mrvl,intc-nr-irqs = <2>;
  70. mrvl,clr-mfp-irq = <1>;
  71. };
  72. intcmux9: interrupt-controller@d4282180 {
  73. compatible = "mrvl,mmp2-mux-intc";
  74. interrupts = <9>;
  75. interrupt-controller;
  76. #interrupt-cells = <1>;
  77. reg = <0x180 0x4>, <0x17c 0x4>;
  78. reg-names = "mux status", "mux mask";
  79. mrvl,intc-nr-irqs = <3>;
  80. };
  81. intcmux17: interrupt-controller@d4282158 {
  82. compatible = "mrvl,mmp2-mux-intc";
  83. interrupts = <17>;
  84. interrupt-controller;
  85. #interrupt-cells = <1>;
  86. reg = <0x158 0x4>, <0x170 0x4>;
  87. reg-names = "mux status", "mux mask";
  88. mrvl,intc-nr-irqs = <5>;
  89. };
  90. intcmux35: interrupt-controller@d428215c {
  91. compatible = "mrvl,mmp2-mux-intc";
  92. interrupts = <35>;
  93. interrupt-controller;
  94. #interrupt-cells = <1>;
  95. reg = <0x15c 0x4>, <0x174 0x4>;
  96. reg-names = "mux status", "mux mask";
  97. mrvl,intc-nr-irqs = <15>;
  98. };
  99. intcmux51: interrupt-controller@d4282160 {
  100. compatible = "mrvl,mmp2-mux-intc";
  101. interrupts = <51>;
  102. interrupt-controller;
  103. #interrupt-cells = <1>;
  104. reg = <0x160 0x4>, <0x178 0x4>;
  105. reg-names = "mux status", "mux mask";
  106. mrvl,intc-nr-irqs = <2>;
  107. };
  108. intcmux55: interrupt-controller@d4282188 {
  109. compatible = "mrvl,mmp2-mux-intc";
  110. interrupts = <55>;
  111. interrupt-controller;
  112. #interrupt-cells = <1>;
  113. reg = <0x188 0x4>, <0x184 0x4>;
  114. reg-names = "mux status", "mux mask";
  115. mrvl,intc-nr-irqs = <2>;
  116. };
  117. usb_phy0: usb-phy@d4207000 {
  118. compatible = "marvell,mmp2-usb-phy";
  119. reg = <0xd4207000 0x40>;
  120. #phy-cells = <0>;
  121. status = "disabled";
  122. };
  123. usb_otg0: usb-otg@d4208000 {
  124. compatible = "marvell,pxau2o-ehci";
  125. reg = <0xd4208000 0x200>;
  126. interrupts = <44>;
  127. clocks = <&soc_clocks MMP2_CLK_USB>;
  128. clock-names = "USBCLK";
  129. phys = <&usb_phy0>;
  130. phy-names = "usb";
  131. status = "disabled";
  132. };
  133. mmc1: mmc@d4280000 {
  134. compatible = "mrvl,pxav3-mmc";
  135. reg = <0xd4280000 0x120>;
  136. clocks = <&soc_clocks MMP2_CLK_SDH0>;
  137. clock-names = "io";
  138. interrupts = <39>;
  139. status = "disabled";
  140. };
  141. mmc2: mmc@d4280800 {
  142. compatible = "mrvl,pxav3-mmc";
  143. reg = <0xd4280800 0x120>;
  144. clocks = <&soc_clocks MMP2_CLK_SDH1>;
  145. clock-names = "io";
  146. interrupts = <52>;
  147. status = "disabled";
  148. };
  149. mmc3: mmc@d4281000 {
  150. compatible = "mrvl,pxav3-mmc";
  151. reg = <0xd4281000 0x120>;
  152. clocks = <&soc_clocks MMP2_CLK_SDH2>;
  153. clock-names = "io";
  154. interrupts = <53>;
  155. status = "disabled";
  156. };
  157. mmc4: mmc@d4281800 {
  158. compatible = "mrvl,pxav3-mmc";
  159. reg = <0xd4281800 0x120>;
  160. clocks = <&soc_clocks MMP2_CLK_SDH3>;
  161. clock-names = "io";
  162. interrupts = <54>;
  163. status = "disabled";
  164. };
  165. camera0: camera@d420a000 {
  166. compatible = "marvell,mmp2-ccic";
  167. reg = <0xd420a000 0x800>;
  168. interrupts = <42>;
  169. clocks = <&soc_clocks MMP2_CLK_CCIC0>;
  170. clock-names = "axi";
  171. #clock-cells = <0>;
  172. clock-output-names = "mclk";
  173. status = "disabled";
  174. };
  175. camera1: camera@d420a800 {
  176. compatible = "marvell,mmp2-ccic";
  177. reg = <0xd420a800 0x800>;
  178. interrupts = <30>;
  179. clocks = <&soc_clocks MMP2_CLK_CCIC1>;
  180. clock-names = "axi";
  181. #clock-cells = <0>;
  182. clock-output-names = "mclk";
  183. status = "disabled";
  184. };
  185. adma0: dma-controller@d42a0800 {
  186. compatible = "marvell,adma-1.0";
  187. reg = <0xd42a0800 0x100>;
  188. interrupts = <48>;
  189. #dma-cells = <1>;
  190. asram = <&asram>;
  191. iram = <&asram>;
  192. status = "disabled";
  193. };
  194. adma1: dma-controller@d42a0900 {
  195. compatible = "marvell,adma-1.0";
  196. reg = <0xd42a0900 0x100>;
  197. interrupts = <48>;
  198. #dma-cells = <1>;
  199. status = "disabled";
  200. };
  201. audio_clk: clocks@d42a0c30 {
  202. compatible = "marvell,mmp2-audio-clock";
  203. reg = <0xd42a0c30 0x10>;
  204. clock-names = "audio", "vctcxo", "i2s0", "i2s1";
  205. clocks = <&soc_clocks MMP2_CLK_AUDIO>,
  206. <&soc_clocks MMP2_CLK_VCTCXO>,
  207. <&soc_clocks MMP2_CLK_I2S0>,
  208. <&soc_clocks MMP2_CLK_I2S1>;
  209. power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
  210. #clock-cells = <1>;
  211. status = "disabled";
  212. };
  213. sspa0: audio-controller@d42a0c00 {
  214. compatible = "marvell,mmp-sspa";
  215. reg = <0xd42a0c00 0x30>,
  216. <0xd42a0c80 0x30>;
  217. interrupts = <2>;
  218. clock-names = "audio", "bitclk";
  219. clocks = <&soc_clocks MMP2_CLK_AUDIO>,
  220. <&audio_clk MMP2_CLK_AUDIO_SSPA0>;
  221. power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
  222. #sound-dai-cells = <0>;
  223. status = "disabled";
  224. };
  225. sspa1: audio-controller@d42a0d00 {
  226. compatible = "marvell,mmp-sspa";
  227. reg = <0xd42a0d00 0x30>,
  228. <0xd42a0d80 0x30>;
  229. interrupts = <3>;
  230. clock-names = "audio", "bitclk";
  231. clocks = <&soc_clocks MMP2_CLK_AUDIO>,
  232. <&audio_clk MMP2_CLK_AUDIO_SSPA1>;
  233. power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
  234. #sound-dai-cells = <0>;
  235. status = "disabled";
  236. };
  237. };
  238. apb@d4000000 { /* APB */
  239. compatible = "mrvl,apb-bus", "simple-bus";
  240. #address-cells = <1>;
  241. #size-cells = <1>;
  242. reg = <0xd4000000 0x00200000>;
  243. ranges;
  244. dma-controller@d4000000 {
  245. compatible = "marvell,pdma-1.0";
  246. reg = <0xd4000000 0x10000>;
  247. interrupts = <48>;
  248. /* For backwards compatibility: */
  249. #dma-channels = <16>;
  250. dma-channels = <16>;
  251. status = "disabled";
  252. };
  253. timer0: timer@d4014000 {
  254. compatible = "mrvl,mmp-timer";
  255. reg = <0xd4014000 0x100>;
  256. interrupts = <13>;
  257. clocks = <&soc_clocks MMP2_CLK_TIMER>;
  258. };
  259. uart1: serial@d4030000 {
  260. compatible = "mrvl,mmp-uart", "intel,xscale-uart";
  261. reg = <0xd4030000 0x1000>;
  262. interrupts = <27>;
  263. clocks = <&soc_clocks MMP2_CLK_UART0>;
  264. resets = <&soc_clocks MMP2_CLK_UART0>;
  265. reg-shift = <2>;
  266. status = "disabled";
  267. };
  268. uart2: serial@d4017000 {
  269. compatible = "mrvl,mmp-uart", "intel,xscale-uart";
  270. reg = <0xd4017000 0x1000>;
  271. interrupts = <28>;
  272. clocks = <&soc_clocks MMP2_CLK_UART1>;
  273. resets = <&soc_clocks MMP2_CLK_UART1>;
  274. reg-shift = <2>;
  275. status = "disabled";
  276. };
  277. uart3: serial@d4018000 {
  278. compatible = "mrvl,mmp-uart", "intel,xscale-uart";
  279. reg = <0xd4018000 0x1000>;
  280. interrupts = <24>;
  281. clocks = <&soc_clocks MMP2_CLK_UART2>;
  282. resets = <&soc_clocks MMP2_CLK_UART2>;
  283. reg-shift = <2>;
  284. status = "disabled";
  285. };
  286. uart4: serial@d4016000 {
  287. compatible = "mrvl,mmp-uart", "intel,xscale-uart";
  288. reg = <0xd4016000 0x1000>;
  289. interrupts = <46>;
  290. clocks = <&soc_clocks MMP2_CLK_UART3>;
  291. resets = <&soc_clocks MMP2_CLK_UART3>;
  292. reg-shift = <2>;
  293. status = "disabled";
  294. };
  295. gpio: gpio@d4019000 {
  296. compatible = "marvell,mmp2-gpio";
  297. #address-cells = <1>;
  298. #size-cells = <1>;
  299. reg = <0xd4019000 0x1000>;
  300. gpio-controller;
  301. #gpio-cells = <2>;
  302. interrupts = <49>;
  303. interrupt-names = "gpio_mux";
  304. clocks = <&soc_clocks MMP2_CLK_GPIO>;
  305. resets = <&soc_clocks MMP2_CLK_GPIO>;
  306. interrupt-controller;
  307. #interrupt-cells = <2>;
  308. ranges;
  309. gcb0: gpio@d4019000 {
  310. reg = <0xd4019000 0x4>;
  311. };
  312. gcb1: gpio@d4019004 {
  313. reg = <0xd4019004 0x4>;
  314. };
  315. gcb2: gpio@d4019008 {
  316. reg = <0xd4019008 0x4>;
  317. };
  318. gcb3: gpio@d4019100 {
  319. reg = <0xd4019100 0x4>;
  320. };
  321. gcb4: gpio@d4019104 {
  322. reg = <0xd4019104 0x4>;
  323. };
  324. gcb5: gpio@d4019108 {
  325. reg = <0xd4019108 0x4>;
  326. };
  327. };
  328. twsi1: i2c@d4011000 {
  329. compatible = "mrvl,mmp-twsi";
  330. reg = <0xd4011000 0x1000>;
  331. interrupts = <7>;
  332. clocks = <&soc_clocks MMP2_CLK_TWSI0>;
  333. resets = <&soc_clocks MMP2_CLK_TWSI0>;
  334. #address-cells = <1>;
  335. #size-cells = <0>;
  336. mrvl,i2c-fast-mode;
  337. status = "disabled";
  338. };
  339. twsi2: i2c@d4031000 {
  340. compatible = "mrvl,mmp-twsi";
  341. reg = <0xd4031000 0x1000>;
  342. interrupt-parent = <&intcmux17>;
  343. interrupts = <0>;
  344. clocks = <&soc_clocks MMP2_CLK_TWSI1>;
  345. resets = <&soc_clocks MMP2_CLK_TWSI1>;
  346. #address-cells = <1>;
  347. #size-cells = <0>;
  348. status = "disabled";
  349. };
  350. twsi3: i2c@d4032000 {
  351. compatible = "mrvl,mmp-twsi";
  352. reg = <0xd4032000 0x1000>;
  353. interrupt-parent = <&intcmux17>;
  354. interrupts = <1>;
  355. clocks = <&soc_clocks MMP2_CLK_TWSI2>;
  356. resets = <&soc_clocks MMP2_CLK_TWSI2>;
  357. #address-cells = <1>;
  358. #size-cells = <0>;
  359. status = "disabled";
  360. };
  361. twsi4: i2c@d4033000 {
  362. compatible = "mrvl,mmp-twsi";
  363. reg = <0xd4033000 0x1000>;
  364. interrupt-parent = <&intcmux17>;
  365. interrupts = <2>;
  366. clocks = <&soc_clocks MMP2_CLK_TWSI3>;
  367. resets = <&soc_clocks MMP2_CLK_TWSI3>;
  368. #address-cells = <1>;
  369. #size-cells = <0>;
  370. status = "disabled";
  371. };
  372. twsi5: i2c@d4033800 {
  373. compatible = "mrvl,mmp-twsi";
  374. reg = <0xd4033800 0x1000>;
  375. interrupt-parent = <&intcmux17>;
  376. interrupts = <3>;
  377. clocks = <&soc_clocks MMP2_CLK_TWSI4>;
  378. resets = <&soc_clocks MMP2_CLK_TWSI4>;
  379. #address-cells = <1>;
  380. #size-cells = <0>;
  381. status = "disabled";
  382. };
  383. twsi6: i2c@d4034000 {
  384. compatible = "mrvl,mmp-twsi";
  385. reg = <0xd4034000 0x1000>;
  386. interrupt-parent = <&intcmux17>;
  387. interrupts = <4>;
  388. clocks = <&soc_clocks MMP2_CLK_TWSI5>;
  389. resets = <&soc_clocks MMP2_CLK_TWSI5>;
  390. #address-cells = <1>;
  391. #size-cells = <0>;
  392. status = "disabled";
  393. };
  394. rtc: rtc@d4010000 {
  395. compatible = "mrvl,mmp-rtc";
  396. reg = <0xd4010000 0x1000>;
  397. interrupts = <1>, <0>;
  398. interrupt-names = "rtc 1Hz", "rtc alarm";
  399. interrupt-parent = <&intcmux5>;
  400. clocks = <&soc_clocks MMP2_CLK_RTC>;
  401. resets = <&soc_clocks MMP2_CLK_RTC>;
  402. status = "disabled";
  403. };
  404. ssp1: spi@d4035000 {
  405. compatible = "marvell,mmp2-ssp";
  406. reg = <0xd4035000 0x1000>;
  407. clocks = <&soc_clocks MMP2_CLK_SSP0>;
  408. interrupts = <0>;
  409. #address-cells = <1>;
  410. #size-cells = <0>;
  411. status = "disabled";
  412. };
  413. ssp2: spi@d4036000 {
  414. compatible = "marvell,mmp2-ssp";
  415. reg = <0xd4036000 0x1000>;
  416. clocks = <&soc_clocks MMP2_CLK_SSP1>;
  417. interrupts = <1>;
  418. #address-cells = <1>;
  419. #size-cells = <0>;
  420. status = "disabled";
  421. };
  422. ssp3: spi@d4037000 {
  423. compatible = "marvell,mmp2-ssp";
  424. reg = <0xd4037000 0x1000>;
  425. clocks = <&soc_clocks MMP2_CLK_SSP2>;
  426. interrupts = <20>;
  427. #address-cells = <1>;
  428. #size-cells = <0>;
  429. status = "disabled";
  430. };
  431. ssp4: spi@d4039000 {
  432. compatible = "marvell,mmp2-ssp";
  433. reg = <0xd4039000 0x1000>;
  434. clocks = <&soc_clocks MMP2_CLK_SSP3>;
  435. interrupts = <21>;
  436. #address-cells = <1>;
  437. #size-cells = <0>;
  438. status = "disabled";
  439. };
  440. };
  441. asram: sram@e0000000 {
  442. compatible = "mmio-sram";
  443. reg = <0xe0000000 0x10000>;
  444. ranges = <0 0xe0000000 0x10000>;
  445. #address-cells = <1>;
  446. #size-cells = <1>;
  447. status = "disabled";
  448. };
  449. soc_clocks: clocks {
  450. compatible = "marvell,mmp2-clock";
  451. reg = <0xd4050000 0x2000>,
  452. <0xd4282800 0x400>,
  453. <0xd4015000 0x1000>;
  454. reg-names = "mpmu", "apmu", "apbc";
  455. #clock-cells = <1>;
  456. #reset-cells = <1>;
  457. #power-domain-cells = <1>;
  458. };
  459. };
  460. };