meson8m2.dtsi 2.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101
  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2017 Martin Blumenstingl <[email protected]>.
  4. */
  5. #include "meson8.dtsi"
  6. / {
  7. model = "Amlogic Meson8m2 SoC";
  8. compatible = "amlogic,meson8m2";
  9. }; /* end of / */
  10. &clkc {
  11. compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc";
  12. };
  13. &dmcbus {
  14. /* the offset of the canvas registers has changed compared to Meson8 */
  15. /delete-node/ video-lut@20;
  16. canvas: video-lut@48 {
  17. compatible = "amlogic,meson8m2-canvas", "amlogic,canvas";
  18. reg = <0x48 0x14>;
  19. };
  20. };
  21. &ethmac {
  22. compatible = "amlogic,meson8m2-dwmac", "snps,dwmac";
  23. reg = <0xc9410000 0x10000
  24. 0xc1108140 0x8>;
  25. clocks = <&clkc CLKID_ETH>,
  26. <&clkc CLKID_MPLL2>,
  27. <&clkc CLKID_MPLL2>,
  28. <&clkc CLKID_FCLK_DIV2>;
  29. clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
  30. resets = <&reset RESET_ETHERNET>;
  31. reset-names = "stmmaceth";
  32. };
  33. &pinctrl_aobus {
  34. compatible = "amlogic,meson8m2-aobus-pinctrl",
  35. "amlogic,meson8-aobus-pinctrl";
  36. };
  37. &pinctrl_cbus {
  38. compatible = "amlogic,meson8m2-cbus-pinctrl",
  39. "amlogic,meson8-cbus-pinctrl";
  40. eth_rgmii_pins: ethernet {
  41. mux {
  42. groups = "eth_tx_clk_50m", "eth_tx_en",
  43. "eth_txd3", "eth_txd2",
  44. "eth_txd1", "eth_txd0",
  45. "eth_rx_clk_in", "eth_rx_dv",
  46. "eth_rxd3", "eth_rxd2",
  47. "eth_rxd1", "eth_rxd0",
  48. "eth_mdio", "eth_mdc";
  49. function = "ethernet";
  50. bias-disable;
  51. };
  52. };
  53. };
  54. &pwrc {
  55. compatible = "amlogic,meson8m2-pwrc";
  56. resets = <&reset RESET_DBLK>,
  57. <&reset RESET_PIC_DC>,
  58. <&reset RESET_HDMI_APB>,
  59. <&reset RESET_HDMI_SYSTEM_RESET>,
  60. <&reset RESET_VENCI>,
  61. <&reset RESET_VENCP>,
  62. <&reset RESET_VDAC_4>,
  63. <&reset RESET_VENCL>,
  64. <&reset RESET_VIU>,
  65. <&reset RESET_VENC>,
  66. <&reset RESET_RDMA>;
  67. reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", "venci",
  68. "vencp", "vdac", "vencl", "viu", "venc", "rdma";
  69. assigned-clocks = <&clkc CLKID_VPU>;
  70. assigned-clock-rates = <364000000>;
  71. };
  72. &saradc {
  73. compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc";
  74. };
  75. &sdhc {
  76. compatible = "amlogic,meson8m2-sdhc", "amlogic,meson-mx-sdhc";
  77. };
  78. &usb0_phy {
  79. compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy";
  80. };
  81. &usb1_phy {
  82. compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy";
  83. };
  84. &wdt {
  85. compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt";
  86. };