meson6.dtsi 1.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR MIT
  2. /*
  3. * Copyright 2014 Carlo Caione <[email protected]>
  4. */
  5. #include "meson.dtsi"
  6. / {
  7. model = "Amlogic Meson6 SoC";
  8. compatible = "amlogic,meson6";
  9. cpus {
  10. #address-cells = <1>;
  11. #size-cells = <0>;
  12. cpu@200 {
  13. device_type = "cpu";
  14. compatible = "arm,cortex-a9";
  15. next-level-cache = <&L2>;
  16. reg = <0x200>;
  17. };
  18. cpu@201 {
  19. device_type = "cpu";
  20. compatible = "arm,cortex-a9";
  21. next-level-cache = <&L2>;
  22. reg = <0x201>;
  23. };
  24. };
  25. apb2: bus@d0000000 {
  26. compatible = "simple-bus";
  27. reg = <0xd0000000 0x40000>;
  28. #address-cells = <1>;
  29. #size-cells = <1>;
  30. ranges = <0x0 0xd0000000 0x40000>;
  31. };
  32. clk81: clk@0 {
  33. #clock-cells = <0>;
  34. compatible = "fixed-clock";
  35. clock-frequency = <200000000>;
  36. };
  37. }; /* end of / */
  38. &efuse {
  39. status = "disabled";
  40. };
  41. &timer_abcde {
  42. clocks = <&xtal>, <&clk81>;
  43. clock-names = "xtal", "pclk";
  44. };
  45. &uart_AO {
  46. clocks = <&xtal>, <&clk81>, <&clk81>;
  47. clock-names = "xtal", "pclk", "baud";
  48. };
  49. &uart_A {
  50. clocks = <&xtal>, <&clk81>, <&clk81>;
  51. clock-names = "xtal", "pclk", "baud";
  52. };
  53. &uart_B {
  54. clocks = <&xtal>, <&clk81>, <&clk81>;
  55. clock-names = "xtal", "pclk", "baud";
  56. };
  57. &uart_C {
  58. clocks = <&xtal>, <&clk81>, <&clk81>;
  59. clock-names = "xtal", "pclk", "baud";
  60. };