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- // SPDX-License-Identifier: GPL-2.0 OR MIT
- /*
- * Copyright 2014 Carlo Caione <[email protected]>
- */
- #include "meson.dtsi"
- / {
- model = "Amlogic Meson6 SoC";
- compatible = "amlogic,meson6";
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu@200 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- next-level-cache = <&L2>;
- reg = <0x200>;
- };
- cpu@201 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- next-level-cache = <&L2>;
- reg = <0x201>;
- };
- };
- apb2: bus@d0000000 {
- compatible = "simple-bus";
- reg = <0xd0000000 0x40000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xd0000000 0x40000>;
- };
- clk81: clk@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <200000000>;
- };
- }; /* end of / */
- &efuse {
- status = "disabled";
- };
- &timer_abcde {
- clocks = <&xtal>, <&clk81>;
- clock-names = "xtal", "pclk";
- };
- &uart_AO {
- clocks = <&xtal>, <&clk81>, <&clk81>;
- clock-names = "xtal", "pclk", "baud";
- };
- &uart_A {
- clocks = <&xtal>, <&clk81>, <&clk81>;
- clock-names = "xtal", "pclk", "baud";
- };
- &uart_B {
- clocks = <&xtal>, <&clk81>, <&clk81>;
- clock-names = "xtal", "pclk", "baud";
- };
- &uart_C {
- clocks = <&xtal>, <&clk81>, <&clk81>;
- clock-names = "xtal", "pclk", "baud";
- };
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