lpc4350-hitex-eval.dts 8.5 KB

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  1. /*
  2. * Hitex LPC4350 Evaluation Board
  3. *
  4. * Copyright 2015 Ariel D'Alessandro <[email protected]>
  5. *
  6. * This code is released using a dual license strategy: BSD/GPL
  7. * You can choose the licence that better fits your requirements.
  8. *
  9. * Released under the terms of 3-clause BSD License
  10. * Released under the terms of GNU General Public License Version 2.0
  11. *
  12. */
  13. /dts-v1/;
  14. #include "lpc18xx.dtsi"
  15. #include "lpc4350.dtsi"
  16. #include "dt-bindings/input/input.h"
  17. #include "dt-bindings/gpio/gpio.h"
  18. / {
  19. model = "Hitex LPC4350 Evaluation Board";
  20. compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
  21. aliases {
  22. serial0 = &uart0;
  23. serial1 = &uart1;
  24. serial2 = &uart2;
  25. serial3 = &uart3;
  26. };
  27. chosen {
  28. stdout-path = &uart0;
  29. };
  30. memory@28000000 {
  31. device_type = "memory";
  32. reg = <0x28000000 0x800000>; /* 8 MB */
  33. };
  34. pca_buttons {
  35. compatible = "gpio-keys-polled";
  36. poll-interval = <100>;
  37. autorepeat;
  38. button0 {
  39. label = "joy:right";
  40. linux,code = <KEY_RIGHT>;
  41. gpios = <&pca_gpio 8 GPIO_ACTIVE_LOW>;
  42. };
  43. button1 {
  44. label = "joy:up";
  45. linux,code = <KEY_UP>;
  46. gpios = <&pca_gpio 9 GPIO_ACTIVE_LOW>;
  47. };
  48. button2 {
  49. label = "joy:enter";
  50. linux,code = <KEY_ENTER>;
  51. gpios = <&pca_gpio 10 GPIO_ACTIVE_LOW>;
  52. };
  53. button3 {
  54. label = "joy:left";
  55. linux,code = <KEY_LEFT>;
  56. gpios = <&pca_gpio 11 GPIO_ACTIVE_LOW>;
  57. };
  58. button4 {
  59. label = "joy:down";
  60. linux,code = <KEY_DOWN>;
  61. gpios = <&pca_gpio 12 GPIO_ACTIVE_LOW>;
  62. };
  63. button5 {
  64. label = "user:sw3";
  65. linux,code = <KEY_F1>;
  66. gpios = <&pca_gpio 13 GPIO_ACTIVE_LOW>;
  67. };
  68. button6 {
  69. label = "user:sw4";
  70. linux,code = <KEY_F2>;
  71. gpios = <&pca_gpio 14 GPIO_ACTIVE_LOW>;
  72. };
  73. button7 {
  74. label = "user:sw5";
  75. linux,code = <KEY_F3>;
  76. gpios = <&pca_gpio 15 GPIO_ACTIVE_LOW>;
  77. };
  78. };
  79. pca_leds {
  80. compatible = "gpio-leds";
  81. led0 {
  82. label = "ext:led0";
  83. gpios = <&pca_gpio 0 GPIO_ACTIVE_LOW>;
  84. linux,default-trigger = "heartbeat";
  85. };
  86. led1 {
  87. label = "ext:led1";
  88. gpios = <&pca_gpio 1 GPIO_ACTIVE_LOW>;
  89. };
  90. led2 {
  91. label = "ext:led2";
  92. gpios = <&pca_gpio 2 GPIO_ACTIVE_LOW>;
  93. };
  94. led3 {
  95. label = "ext:led3";
  96. gpios = <&pca_gpio 3 GPIO_ACTIVE_LOW>;
  97. };
  98. };
  99. vcc: vcc_fixed {
  100. compatible = "regulator-fixed";
  101. regulator-name = "3v3io";
  102. regulator-min-microvolt = <3300000>;
  103. regulator-max-microvolt = <3300000>;
  104. };
  105. };
  106. &pinctrl {
  107. adc1_pins: adc1-pins {
  108. adc1_pins_cfg {
  109. pins = "pf_9";
  110. function = "adc";
  111. input-disable;
  112. bias-disable;
  113. };
  114. };
  115. emc_pins: emc-pins {
  116. emc_addr0_23_cfg {
  117. pins = "p2_9", "p2_10", "p2_11", "p2_12",
  118. "p2_13", "p1_0", "p1_1", "p1_2",
  119. "p2_8", "p2_7", "p2_6", "p2_2",
  120. "p2_1", "p2_0", "p6_8", "p6_7",
  121. "pd_16", "pd_15", "pe_0", "pe_1",
  122. "pe_2", "pe_3", "pe_4", "pa_4";
  123. function = "emc";
  124. slew-rate = <1>;
  125. bias-disable;
  126. input-enable;
  127. input-schmitt-disable;
  128. };
  129. emc_data0_15_cfg {
  130. pins = "p1_7", "p1_8", "p1_9", "p1_10",
  131. "p1_11", "p1_12", "p1_13", "p1_14",
  132. "p5_4", "p5_5", "p5_6", "p5_7",
  133. "p5_0", "p5_1", "p5_2", "p5_3";
  134. function = "emc";
  135. slew-rate = <1>;
  136. bias-disable;
  137. input-enable;
  138. input-schmitt-disable;
  139. };
  140. emc_we_oe_cfg {
  141. pins = "p1_6", "p1_3";
  142. function = "emc";
  143. slew-rate = <1>;
  144. bias-disable;
  145. input-enable;
  146. input-schmitt-disable;
  147. };
  148. emc_bls0_3_cfg {
  149. pins = "p1_4", "p6_6", "pd_13", "pd_10";
  150. function = "emc";
  151. slew-rate = <1>;
  152. bias-disable;
  153. input-enable;
  154. input-schmitt-disable;
  155. };
  156. emc_cs0_cs2_cfg {
  157. pins = "p1_5", "pd_12";
  158. function = "emc";
  159. slew-rate = <1>;
  160. bias-disable;
  161. input-enable;
  162. input-schmitt-disable;
  163. };
  164. emc_sdram_dqm0_3_cfg {
  165. pins = "p6_12", "p6_10", "pd_0", "pe_13";
  166. function = "emc";
  167. slew-rate = <1>;
  168. bias-disable;
  169. input-enable;
  170. input-schmitt-disable;
  171. };
  172. emc_sdram_ras_cas_cfg {
  173. pins = "p6_5", "p6_4";
  174. function = "emc";
  175. slew-rate = <1>;
  176. bias-disable;
  177. input-enable;
  178. input-schmitt-disable;
  179. };
  180. emc_sdram_dycs0_cfg {
  181. pins = "p6_9";
  182. function = "emc";
  183. slew-rate = <1>;
  184. bias-disable;
  185. input-enable;
  186. input-schmitt-disable;
  187. };
  188. emc_sdram_cke_cfg {
  189. pins = "p6_11";
  190. function = "emc";
  191. slew-rate = <1>;
  192. bias-disable;
  193. input-enable;
  194. input-schmitt-disable;
  195. };
  196. emc_sdram_clock_cfg {
  197. pins = "clk0", "clk1", "clk2", "clk3";
  198. function = "emc";
  199. slew-rate = <1>;
  200. bias-disable;
  201. input-enable;
  202. input-schmitt-disable;
  203. };
  204. };
  205. enet_mii_pins: enet-mii-pins {
  206. enet_mii_rxd0_3_cfg {
  207. pins = "p1_15", "p0_0", "p9_3", "p9_2";
  208. function = "enet";
  209. bias-disable;
  210. input-enable;
  211. };
  212. enet_mii_txd0_3_cfg {
  213. pins = "p1_18", "p1_20", "p9_4", "p9_5";
  214. function = "enet";
  215. bias-disable;
  216. };
  217. enet_mii_crs_col_cfg {
  218. pins = "p9_0", "p9_6";
  219. function = "enet";
  220. bias-disable;
  221. input-enable;
  222. };
  223. enet_mii_rx_clk_dv_er_cfg {
  224. pins = "pc_0", "p1_16", "p9_1";
  225. function = "enet";
  226. bias-disable;
  227. input-enable;
  228. };
  229. enet_mii_tx_clk_en_cfg {
  230. pins = "p1_19", "p0_1";
  231. function = "enet";
  232. bias-disable;
  233. input-enable;
  234. };
  235. enet_mdio_cfg {
  236. pins = "p1_17";
  237. function = "enet";
  238. bias-disable;
  239. input-enable;
  240. };
  241. enet_mdc_cfg {
  242. pins = "pc_1";
  243. function = "enet";
  244. bias-disable;
  245. };
  246. };
  247. i2c0_pins: i2c0-pins {
  248. i2c0_pins_cfg {
  249. pins = "i2c0_scl", "i2c0_sda";
  250. function = "i2c0";
  251. input-enable;
  252. };
  253. };
  254. spifi_pins: spifi-pins {
  255. spifi_clk_cfg {
  256. pins = "p3_3";
  257. function = "spifi";
  258. slew-rate = <1>;
  259. bias-disable;
  260. input-enable;
  261. input-schmitt-disable;
  262. };
  263. spifi_mosi_miso_sio2_3_cfg {
  264. pins = "p3_7", "p3_6", "p3_5", "p3_4";
  265. function = "spifi";
  266. slew-rate = <1>;
  267. bias-disable;
  268. input-enable;
  269. input-schmitt-disable;
  270. };
  271. spifi_cs_cfg {
  272. pins = "p3_8";
  273. function = "spifi";
  274. slew-rate = <1>;
  275. bias-disable;
  276. input-enable;
  277. input-schmitt-disable;
  278. };
  279. };
  280. uart0_pins: uart0-pins {
  281. uart0_rx_cfg {
  282. pins = "pf_11";
  283. function = "uart0";
  284. input-schmitt-disable;
  285. bias-disable;
  286. input-enable;
  287. };
  288. uart0_tx_cfg {
  289. pins = "pf_10";
  290. function = "uart0";
  291. bias-pull-down;
  292. };
  293. };
  294. };
  295. &adc1 {
  296. status = "okay";
  297. vref-supply = <&vcc>;
  298. pinctrl-names = "default";
  299. pinctrl-0 = <&adc1_pins>;
  300. };
  301. &emc {
  302. status = "okay";
  303. pinctrl-names = "default";
  304. pinctrl-0 = <&emc_pins>;
  305. cs0 {
  306. #address-cells = <2>;
  307. #size-cells = <1>;
  308. ranges;
  309. mpmc,cs = <0>;
  310. mpmc,memory-width = <16>;
  311. mpmc,byte-lane-low;
  312. mpmc,write-enable-delay = <0>;
  313. mpmc,output-enable-delay = <0>;
  314. mpmc,read-access-delay = <70>;
  315. mpmc,page-mode-read-delay = <70>;
  316. flash@0,0 {
  317. compatible = "sst,sst39vf320", "cfi-flash";
  318. reg = <0 0 0x400000>;
  319. bank-width = <2>;
  320. #address-cells = <1>;
  321. #size-cells = <1>;
  322. partition@0 {
  323. label = "bootloader";
  324. reg = <0x000000 0x040000>; /* 256 KiB */
  325. };
  326. partition@1 {
  327. label = "kernel";
  328. reg = <0x040000 0x2C0000>; /* 2.75 MiB */
  329. };
  330. partition@2 {
  331. label = "rootfs";
  332. reg = <0x300000 0x100000>; /* 1 MiB */
  333. };
  334. };
  335. };
  336. cs2 {
  337. #address-cells = <2>;
  338. #size-cells = <1>;
  339. ranges;
  340. mpmc,cs = <2>;
  341. mpmc,memory-width = <16>;
  342. mpmc,byte-lane-low;
  343. mpmc,write-enable-delay = <0>;
  344. mpmc,output-enable-delay = <30>;
  345. mpmc,read-access-delay = <90>;
  346. mpmc,page-mode-read-delay = <55>;
  347. mpmc,write-access-delay = <55>;
  348. mpmc,turn-round-delay = <55>;
  349. ext_sram: sram@2,0 {
  350. compatible = "mmio-sram";
  351. reg = <2 0 0x80000>; /* 512 KiB SRAM on IS62WV25616 */
  352. };
  353. };
  354. };
  355. &enet_tx_clk {
  356. clock-frequency = <25000000>;
  357. };
  358. &i2c0 {
  359. status = "okay";
  360. pinctrl-names = "default";
  361. pinctrl-0 = <&i2c0_pins>;
  362. clock-frequency = <400000>;
  363. /* NXP SE97BTP with temperature sensor + eeprom */
  364. sensor@18 {
  365. compatible = "nxp,se97", "jedec,jc-42.4-temp";
  366. reg = <0x18>;
  367. };
  368. eeprom@50 {
  369. compatible = "nxp,24c02", "atmel,24c02";
  370. reg = <0x50>;
  371. };
  372. pca_gpio: gpio@24 {
  373. compatible = "nxp,pca9673";
  374. reg = <0x24>;
  375. gpio-controller;
  376. #gpio-cells = <2>;
  377. };
  378. };
  379. &mac {
  380. status = "okay";
  381. phy-mode = "mii";
  382. pinctrl-names = "default";
  383. pinctrl-0 = <&enet_mii_pins>;
  384. };
  385. &spifi {
  386. status = "okay";
  387. pinctrl-names = "default";
  388. pinctrl-0 = <&spifi_pins>;
  389. flash {
  390. compatible = "jedec,spi-nor";
  391. spi-rx-bus-width = <4>;
  392. #address-cells = <1>;
  393. #size-cells = <1>;
  394. partition@0 {
  395. label = "bootloader";
  396. reg = <0x000000 0x040000>; /* 256 KiB */
  397. };
  398. partition@1 {
  399. label = "kernel";
  400. reg = <0x040000 0x2c0000>; /* 2.75 MiB */
  401. };
  402. partition@2 {
  403. label = "rootfs";
  404. reg = <0x300000 0x500000>; /* 5 MiB */
  405. };
  406. };
  407. };
  408. &uart0 {
  409. status = "okay";
  410. pinctrl-names = "default";
  411. pinctrl-0 = <&uart0_pins>;
  412. };