kirkwood-pogoplug-series-4.dts 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * kirkwood-pogoplug-series-4.dts - Device tree file for PogoPlug Series 4
  4. * inspired by the board files made by Kevin Mihelich for ArchLinux,
  5. * and their DTS file.
  6. *
  7. * Copyright (C) 2015 Linus Walleij <[email protected]>
  8. */
  9. /dts-v1/;
  10. #include "kirkwood.dtsi"
  11. #include "kirkwood-6192.dtsi"
  12. #include <dt-bindings/input/linux-event-codes.h>
  13. / {
  14. model = "Cloud Engines PogoPlug Series 4";
  15. compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192",
  16. "marvell,kirkwood";
  17. memory {
  18. device_type = "memory";
  19. reg = <0x00000000 0x08000000>;
  20. };
  21. chosen {
  22. stdout-path = "uart0:115200n8";
  23. };
  24. gpio_keys {
  25. compatible = "gpio-keys";
  26. #address-cells = <1>;
  27. #size-cells = <0>;
  28. pinctrl-0 = <&pmx_button_eject>;
  29. pinctrl-names = "default";
  30. eject {
  31. debounce-interval = <50>;
  32. wakeup-source;
  33. linux,code = <KEY_EJECTCD>;
  34. label = "Eject Button";
  35. gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
  36. };
  37. };
  38. gpio-leds {
  39. compatible = "gpio-leds";
  40. pinctrl-0 = <&pmx_led_green &pmx_led_red>;
  41. pinctrl-names = "default";
  42. health {
  43. label = "pogoplugv4:green:health";
  44. gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
  45. default-state = "on";
  46. };
  47. fault {
  48. label = "pogoplugv4:red:fault";
  49. gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
  50. };
  51. };
  52. };
  53. &pinctrl {
  54. pmx_sata0: pmx-sata0 {
  55. marvell,pins = "mpp21";
  56. marvell,function = "sata0";
  57. };
  58. pmx_sata1: pmx-sata1 {
  59. marvell,pins = "mpp20";
  60. marvell,function = "sata1";
  61. };
  62. pmx_sdio_cd: pmx-sdio-cd {
  63. marvell,pins = "mpp27";
  64. marvell,function = "gpio";
  65. };
  66. pmx_sdio_wp: pmx-sdio-wp {
  67. marvell,pins = "mpp28";
  68. marvell,function = "gpio";
  69. };
  70. pmx_button_eject: pmx-button-eject {
  71. marvell,pins = "mpp29";
  72. marvell,function = "gpio";
  73. };
  74. pmx_led_green: pmx-led-green {
  75. marvell,pins = "mpp22";
  76. marvell,function = "gpio";
  77. };
  78. pmx_led_red: pmx-led-red {
  79. marvell,pins = "mpp24";
  80. marvell,function = "gpio";
  81. };
  82. };
  83. &uart0 {
  84. status = "okay";
  85. };
  86. /*
  87. * This PCIE controller has a USB 3.0 XHCI controller at 1,0
  88. */
  89. &pciec {
  90. status = "okay";
  91. };
  92. &pcie0 {
  93. status = "okay";
  94. };
  95. &sata {
  96. status = "okay";
  97. pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
  98. pinctrl-names = "default";
  99. nr-ports = <1>;
  100. };
  101. &sdio {
  102. status = "okay";
  103. pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>;
  104. pinctrl-names = "default";
  105. cd-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
  106. wp-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
  107. };
  108. &nand {
  109. /* 128 MiB of NAND flash */
  110. chip-delay = <40>;
  111. status = "okay";
  112. partitions {
  113. compatible = "fixed-partitions";
  114. #address-cells = <1>;
  115. #size-cells = <1>;
  116. partition@0 {
  117. label = "u-boot";
  118. reg = <0x00000000 0x200000>;
  119. read-only;
  120. };
  121. partition@200000 {
  122. label = "uImage";
  123. reg = <0x00200000 0x300000>;
  124. };
  125. partition@500000 {
  126. label = "uImage2";
  127. reg = <0x00500000 0x300000>;
  128. };
  129. partition@800000 {
  130. label = "failsafe";
  131. reg = <0x00800000 0x800000>;
  132. };
  133. partition@1000000 {
  134. label = "root";
  135. reg = <0x01000000 0x7000000>;
  136. };
  137. };
  138. };
  139. &mdio {
  140. status = "okay";
  141. ethphy0: ethernet-phy@0 {
  142. reg = <0>;
  143. };
  144. };
  145. &eth0 {
  146. status = "okay";
  147. ethernet0-port@0 {
  148. phy-handle = <&ethphy0>;
  149. };
  150. };