imx7d-zii-rpu2.dts 20 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Device tree file for ZII's RPU2 board
  4. *
  5. * RPU - Remote Peripheral Unit
  6. *
  7. * Copyright (C) 2019 Zodiac Inflight Innovations
  8. */
  9. /dts-v1/;
  10. #include <dt-bindings/thermal/thermal.h>
  11. #include "imx7d.dtsi"
  12. / {
  13. model = "ZII RPU2 Board";
  14. compatible = "zii,imx7d-rpu2", "fsl,imx7d";
  15. chosen {
  16. stdout-path = &uart2;
  17. };
  18. cs2000_ref: oscillator {
  19. compatible = "fixed-clock";
  20. #clock-cells = <0>;
  21. clock-frequency = <24576000>;
  22. };
  23. cs2000_in_dummy: dummy-oscillator {
  24. compatible = "fixed-clock";
  25. #clock-cells = <0>;
  26. clock-frequency = <0>;
  27. };
  28. gpio-leds {
  29. compatible = "gpio-leds";
  30. pinctrl-0 = <&pinctrl_leds_debug>;
  31. pinctrl-names = "default";
  32. led-debug {
  33. label = "zii:green:debug1";
  34. gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
  35. linux,default-trigger = "heartbeat";
  36. };
  37. };
  38. iio-hwmon {
  39. compatible = "iio-hwmon";
  40. io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>,
  41. <&adc2 1>;
  42. };
  43. reg_can1_stby: regulator-can1-stby {
  44. compatible = "regulator-fixed";
  45. pinctrl-names = "default";
  46. pinctrl-0 = <&pinctrl_flexcan1_stby>;
  47. regulator-name = "can1-3v3";
  48. regulator-min-microvolt = <3300000>;
  49. regulator-max-microvolt = <3300000>;
  50. gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  51. enable-active-high;
  52. };
  53. reg_can2_stby: regulator-can2-stby {
  54. compatible = "regulator-fixed";
  55. pinctrl-names = "default";
  56. pinctrl-0 = <&pinctrl_flexcan2_stby>;
  57. regulator-name = "can2-3v3";
  58. regulator-min-microvolt = <3300000>;
  59. regulator-max-microvolt = <3300000>;
  60. gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
  61. enable-active-high;
  62. };
  63. reg_vref_1v8: regulator-vref-1v8 {
  64. compatible = "regulator-fixed";
  65. regulator-name = "vref-1v8";
  66. regulator-min-microvolt = <1800000>;
  67. regulator-max-microvolt = <1800000>;
  68. regulator-always-on;
  69. };
  70. reg_3p3v: regulator-3p3v {
  71. compatible = "regulator-fixed";
  72. regulator-name = "GEN_3V3";
  73. regulator-min-microvolt = <3300000>;
  74. regulator-max-microvolt = <3300000>;
  75. regulator-always-on;
  76. };
  77. reg_5p0v_main: regulator-5p0v-main {
  78. compatible = "regulator-fixed";
  79. regulator-name = "5V_MAIN";
  80. regulator-min-microvolt = <5000000>;
  81. regulator-max-microvolt = <5000000>;
  82. regulator-always-on;
  83. };
  84. sound1 {
  85. compatible = "simple-audio-card";
  86. simple-audio-card,name = "Audio Output 1";
  87. simple-audio-card,format = "i2s";
  88. simple-audio-card,bitclock-master = <&sound1_codec>;
  89. simple-audio-card,frame-master = <&sound1_codec>;
  90. simple-audio-card,widgets =
  91. "Headphone", "Headphone Jack";
  92. simple-audio-card,routing =
  93. "Headphone Jack", "HPLEFT",
  94. "Headphone Jack", "HPRIGHT",
  95. "LEFTIN", "HPL",
  96. "RIGHTIN", "HPR";
  97. simple-audio-card,aux-devs = <&hpa1>;
  98. simple-audio-card,cpu {
  99. sound-dai = <&sai1>;
  100. };
  101. sound1_codec: simple-audio-card,codec {
  102. sound-dai = <&codec1>;
  103. clocks = <&cs2000>;
  104. };
  105. };
  106. sound2 {
  107. compatible = "simple-audio-card";
  108. simple-audio-card,name = "Audio Output 2";
  109. simple-audio-card,format = "i2s";
  110. simple-audio-card,bitclock-master = <&sound2_codec>;
  111. simple-audio-card,frame-master = <&sound2_codec>;
  112. simple-audio-card,widgets =
  113. "Headphone", "Headphone Jack";
  114. simple-audio-card,routing =
  115. "Headphone Jack", "HPLEFT",
  116. "Headphone Jack", "HPRIGHT",
  117. "LEFTIN", "HPL",
  118. "RIGHTIN", "HPR";
  119. simple-audio-card,aux-devs = <&hpa2>;
  120. simple-audio-card,cpu {
  121. sound-dai = <&sai2>;
  122. };
  123. sound2_codec: simple-audio-card,codec {
  124. sound-dai = <&codec2>;
  125. clocks = <&cs2000>;
  126. };
  127. };
  128. sound3 {
  129. compatible = "simple-audio-card";
  130. simple-audio-card,name = "Audio Output 3";
  131. simple-audio-card,format = "i2s";
  132. simple-audio-card,bitclock-master = <&sound3_codec>;
  133. simple-audio-card,frame-master = <&sound3_codec>;
  134. simple-audio-card,widgets =
  135. "Headphone", "Headphone Jack";
  136. simple-audio-card,routing =
  137. "Headphone Jack", "HPLEFT",
  138. "Headphone Jack", "HPRIGHT",
  139. "LEFTIN", "HPL",
  140. "RIGHTIN", "HPR";
  141. simple-audio-card,aux-devs = <&hpa3>;
  142. simple-audio-card,cpu {
  143. sound-dai = <&sai3>;
  144. };
  145. sound3_codec: simple-audio-card,codec {
  146. sound-dai = <&codec3>;
  147. clocks = <&cs2000>;
  148. };
  149. };
  150. };
  151. &adc1 {
  152. vref-supply = <&reg_vref_1v8>;
  153. status = "okay";
  154. };
  155. &adc2 {
  156. vref-supply = <&reg_vref_1v8>;
  157. status = "okay";
  158. };
  159. &cpu0 {
  160. cpu-supply = <&sw1a_reg>;
  161. };
  162. &clks {
  163. assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
  164. assigned-clock-rates = <884736000>;
  165. };
  166. &ecspi1 {
  167. pinctrl-names = "default";
  168. pinctrl-0 = <&pinctrl_ecspi1>;
  169. cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
  170. status = "okay";
  171. flash@0 {
  172. compatible = "jedec,spi-nor";
  173. spi-max-frequency = <20000000>;
  174. reg = <0>;
  175. #address-cells = <1>;
  176. #size-cells = <1>;
  177. };
  178. };
  179. &fec1 {
  180. pinctrl-names = "default";
  181. pinctrl-0 = <&pinctrl_enet1>;
  182. assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
  183. <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
  184. assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
  185. assigned-clock-rates = <0>, <100000000>;
  186. phy-mode = "rgmii";
  187. status = "okay";
  188. fixed-link {
  189. speed = <1000>;
  190. full-duplex;
  191. };
  192. mdio1: mdio {
  193. #address-cells = <1>;
  194. #size-cells = <0>;
  195. status = "okay";
  196. switch: switch@0 {
  197. compatible = "marvell,mv88e6085";
  198. pinctrl-names = "default";
  199. pinctrl-0 = <&pinctrl_switch>;
  200. reg = <0>;
  201. eeprom-length = <512>;
  202. interrupt-parent = <&gpio1>;
  203. interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
  204. interrupt-controller;
  205. #interrupt-cells = <2>;
  206. ports {
  207. #address-cells = <1>;
  208. #size-cells = <0>;
  209. port@0 {
  210. reg = <0>;
  211. label = "eth_cu_1000_1";
  212. };
  213. port@1 {
  214. reg = <1>;
  215. label = "eth_cu_1000_2";
  216. };
  217. port@2 {
  218. reg = <2>;
  219. label = "pic";
  220. fixed-link {
  221. speed = <100>;
  222. full-duplex;
  223. };
  224. };
  225. port@5 {
  226. reg = <5>;
  227. label = "cpu";
  228. ethernet = <&fec1>;
  229. phy-mode = "rgmii-id";
  230. fixed-link {
  231. speed = <1000>;
  232. full-duplex;
  233. };
  234. };
  235. port@6 {
  236. reg = <6>;
  237. label = "gigabit_proc";
  238. ethernet = <&fec2>;
  239. phy-mode = "rgmii-id";
  240. fixed-link {
  241. speed = <1000>;
  242. full-duplex;
  243. };
  244. };
  245. };
  246. };
  247. };
  248. };
  249. &fec2 {
  250. pinctrl-names = "default";
  251. pinctrl-0 = <&pinctrl_enet2>;
  252. assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
  253. <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
  254. assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
  255. assigned-clock-rates = <0>, <100000000>;
  256. phy-mode = "rgmii";
  257. fsl,magic-packet;
  258. status = "okay";
  259. fixed-link {
  260. speed = <1000>;
  261. full-duplex;
  262. };
  263. };
  264. &flexcan1 {
  265. pinctrl-names = "default";
  266. pinctrl-0 = <&pinctrl_flexcan1>;
  267. xceiver-supply = <&reg_can1_stby>;
  268. status = "okay";
  269. };
  270. &flexcan2 {
  271. pinctrl-names = "default";
  272. pinctrl-0 = <&pinctrl_flexcan2>;
  273. xceiver-supply = <&reg_can2_stby>;
  274. status = "okay";
  275. };
  276. &gpio1 {
  277. pinctrl-names = "default";
  278. pinctrl-0 = <&pinctrl_gpio1>;
  279. gpio-line-names = "", "", "", "", "", "", "", "",
  280. "", "",
  281. "usb_1_en_b",
  282. "usb_2_en_b",
  283. "", "", "", "", "", "", "", "",
  284. "", "", "", "", "", "", "", "",
  285. "", "", "", "";
  286. };
  287. &gpio2 {
  288. pinctrl-names = "default";
  289. pinctrl-0 = <&pinctrl_gpio2>;
  290. gpio-line-names = "12v_out_en_1",
  291. "12v_out_en_2",
  292. "12v_out_en_3",
  293. "28v_out_en_5",
  294. "28v_out_en_1",
  295. "28v_out_en_2",
  296. "28v_out_en_3",
  297. "28v_out_en_4",
  298. "", "",
  299. "usb_3_en_b",
  300. "usb_4_en_b",
  301. "", "", "", "", "", "", "", "",
  302. "", "", "", "", "", "", "", "",
  303. "", "", "", "";
  304. };
  305. &i2c1 {
  306. clock-frequency = <100000>;
  307. pinctrl-names = "default";
  308. pinctrl-0 = <&pinctrl_i2c1>;
  309. status = "okay";
  310. pmic: pmic@8 {
  311. compatible = "fsl,pfuze3000";
  312. reg = <0x08>;
  313. regulators {
  314. sw1a_reg: sw1a {
  315. regulator-min-microvolt = <700000>;
  316. regulator-max-microvolt = <3300000>;
  317. regulator-boot-on;
  318. regulator-always-on;
  319. regulator-ramp-delay = <6250>;
  320. };
  321. sw1c_reg: sw1b {
  322. regulator-min-microvolt = <700000>;
  323. regulator-max-microvolt = <1475000>;
  324. regulator-boot-on;
  325. regulator-always-on;
  326. regulator-ramp-delay = <6250>;
  327. };
  328. sw2_reg: sw2 {
  329. regulator-min-microvolt = <1500000>;
  330. regulator-max-microvolt = <1850000>;
  331. regulator-boot-on;
  332. regulator-always-on;
  333. };
  334. sw3a_reg: sw3 {
  335. regulator-min-microvolt = <900000>;
  336. regulator-max-microvolt = <1650000>;
  337. regulator-boot-on;
  338. regulator-always-on;
  339. };
  340. swbst_reg: swbst {
  341. regulator-min-microvolt = <5000000>;
  342. regulator-max-microvolt = <5150000>;
  343. };
  344. snvs_reg: vsnvs {
  345. regulator-min-microvolt = <1000000>;
  346. regulator-max-microvolt = <3000000>;
  347. regulator-boot-on;
  348. regulator-always-on;
  349. };
  350. vref_reg: vrefddr {
  351. regulator-boot-on;
  352. regulator-always-on;
  353. };
  354. vgen1_reg: vldo1 {
  355. regulator-min-microvolt = <1800000>;
  356. regulator-max-microvolt = <3300000>;
  357. regulator-always-on;
  358. };
  359. vgen2_reg: vldo2 {
  360. regulator-min-microvolt = <800000>;
  361. regulator-max-microvolt = <1550000>;
  362. regulator-always-on;
  363. };
  364. vgen3_reg: vccsd {
  365. regulator-min-microvolt = <2850000>;
  366. regulator-max-microvolt = <3300000>;
  367. regulator-always-on;
  368. };
  369. vgen4_reg: v33 {
  370. regulator-min-microvolt = <2850000>;
  371. regulator-max-microvolt = <3300000>;
  372. regulator-always-on;
  373. };
  374. vgen5_reg: vldo3 {
  375. regulator-min-microvolt = <1800000>;
  376. regulator-max-microvolt = <3300000>;
  377. regulator-always-on;
  378. };
  379. vgen6_reg: vldo4 {
  380. regulator-min-microvolt = <1800000>;
  381. regulator-max-microvolt = <3300000>;
  382. regulator-always-on;
  383. };
  384. };
  385. };
  386. cs2000: clkgen@4e {
  387. compatible = "cirrus,cs2000-cp";
  388. reg = <0x4e>;
  389. #clock-cells = <0>;
  390. clock-names = "clk_in", "ref_clk";
  391. clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
  392. assigned-clocks = <&cs2000>;
  393. assigned-clock-rates = <24000000>;
  394. };
  395. eeprom@50 {
  396. compatible = "atmel,24c04";
  397. reg = <0x50>;
  398. };
  399. eeprom@52 {
  400. compatible = "atmel,24c04";
  401. reg = <0x52>;
  402. };
  403. };
  404. &i2c2 {
  405. clock-frequency = <100000>;
  406. pinctrl-names = "default";
  407. pinctrl-0 = <&pinctrl_i2c2>;
  408. status = "okay";
  409. codec2: codec@18 {
  410. compatible = "ti,tlv320dac3100";
  411. pinctrl-names = "default";
  412. pinctrl-0 = <&pinctrl_codec2>;
  413. reg = <0x18>;
  414. #sound-dai-cells = <0>;
  415. HPVDD-supply = <&reg_3p3v>;
  416. SPRVDD-supply = <&reg_3p3v>;
  417. SPLVDD-supply = <&reg_3p3v>;
  418. AVDD-supply = <&reg_3p3v>;
  419. IOVDD-supply = <&reg_3p3v>;
  420. DVDD-supply = <&vgen4_reg>;
  421. gpio-reset = <&gpio1 6 GPIO_ACTIVE_LOW>;
  422. };
  423. hpa2: amp@60 {
  424. compatible = "ti,tpa6130a2";
  425. pinctrl-names = "default";
  426. pinctrl-0 = <&pinctrl_tpa2>;
  427. reg = <0x60>;
  428. power-gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>;
  429. Vdd-supply = <&reg_5p0v_main>;
  430. };
  431. };
  432. &i2c3 {
  433. clock-frequency = <100000>;
  434. pinctrl-names = "default";
  435. pinctrl-0 = <&pinctrl_i2c3>;
  436. status = "okay";
  437. codec3: codec@18 {
  438. compatible = "ti,tlv320dac3100";
  439. pinctrl-names = "default";
  440. pinctrl-0 = <&pinctrl_codec3>;
  441. reg = <0x18>;
  442. #sound-dai-cells = <0>;
  443. HPVDD-supply = <&reg_3p3v>;
  444. SPRVDD-supply = <&reg_3p3v>;
  445. SPLVDD-supply = <&reg_3p3v>;
  446. AVDD-supply = <&reg_3p3v>;
  447. IOVDD-supply = <&reg_3p3v>;
  448. DVDD-supply = <&vgen4_reg>;
  449. gpio-reset = <&gpio1 7 GPIO_ACTIVE_LOW>;
  450. };
  451. hpa3: amp@60 {
  452. compatible = "ti,tpa6130a2";
  453. pinctrl-names = "default";
  454. pinctrl-0 = <&pinctrl_tpa3>;
  455. reg = <0x60>;
  456. power-gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
  457. Vdd-supply = <&reg_5p0v_main>;
  458. };
  459. };
  460. &i2c4 {
  461. clock-frequency = <100000>;
  462. pinctrl-names = "default";
  463. pinctrl-0 = <&pinctrl_i2c4>;
  464. status = "okay";
  465. codec1: codec@18 {
  466. compatible = "ti,tlv320dac3100";
  467. pinctrl-names = "default";
  468. pinctrl-0 = <&pinctrl_codec1>;
  469. reg = <0x18>;
  470. #sound-dai-cells = <0>;
  471. HPVDD-supply = <&reg_3p3v>;
  472. SPRVDD-supply = <&reg_3p3v>;
  473. SPLVDD-supply = <&reg_3p3v>;
  474. AVDD-supply = <&reg_3p3v>;
  475. IOVDD-supply = <&reg_3p3v>;
  476. DVDD-supply = <&vgen4_reg>;
  477. gpio-reset = <&gpio1 5 GPIO_ACTIVE_LOW>;
  478. };
  479. hpa1: amp@60 {
  480. compatible = "ti,tpa6130a2";
  481. pinctrl-names = "default";
  482. pinctrl-0 = <&pinctrl_tpa1>;
  483. reg = <0x60>;
  484. power-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;
  485. Vdd-supply = <&reg_5p0v_main>;
  486. };
  487. };
  488. &sai1 {
  489. pinctrl-names = "default";
  490. pinctrl-0 = <&pinctrl_sai1>;
  491. assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
  492. <&clks IMX7D_SAI1_ROOT_CLK>;
  493. assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
  494. assigned-clock-rates = <0>, <36864000>;
  495. status = "okay";
  496. };
  497. &sai2 {
  498. pinctrl-names = "default";
  499. pinctrl-0 = <&pinctrl_sai2>;
  500. assigned-clocks = <&clks IMX7D_SAI2_ROOT_SRC>,
  501. <&clks IMX7D_SAI2_ROOT_CLK>;
  502. assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
  503. assigned-clock-rates = <0>, <36864000>;
  504. status = "okay";
  505. };
  506. &sai3 {
  507. pinctrl-names = "default";
  508. pinctrl-0 = <&pinctrl_sai3>;
  509. assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
  510. <&clks IMX7D_SAI3_ROOT_CLK>;
  511. assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
  512. assigned-clock-rates = <0>, <36864000>;
  513. status = "okay";
  514. };
  515. &uart2 {
  516. pinctrl-names = "default";
  517. pinctrl-0 = <&pinctrl_uart2>;
  518. assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
  519. assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
  520. status = "okay";
  521. };
  522. &uart4 {
  523. pinctrl-names = "default";
  524. pinctrl-0 = <&pinctrl_uart4>;
  525. assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
  526. assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
  527. status = "okay";
  528. rave-sp {
  529. compatible = "zii,rave-sp-rdu2";
  530. current-speed = <1000000>;
  531. #address-cells = <1>;
  532. #size-cells = <1>;
  533. watchdog {
  534. compatible = "zii,rave-sp-watchdog";
  535. };
  536. eeprom@a3 {
  537. compatible = "zii,rave-sp-eeprom";
  538. reg = <0xa3 0x4000>;
  539. #address-cells = <1>;
  540. #size-cells = <1>;
  541. zii,eeprom-name = "main-eeprom";
  542. };
  543. };
  544. };
  545. &usbotg1 {
  546. dr_mode = "host";
  547. disable-over-current;
  548. status = "okay";
  549. };
  550. &usbotg2 {
  551. dr_mode = "host";
  552. disable-over-current;
  553. status = "okay";
  554. };
  555. &usdhc1 {
  556. pinctrl-names = "default";
  557. pinctrl-0 = <&pinctrl_usdhc1>;
  558. bus-width = <4>;
  559. no-1-8-v;
  560. no-sdio;
  561. keep-power-in-suspend;
  562. status = "okay";
  563. };
  564. &usdhc3 {
  565. pinctrl-names = "default";
  566. pinctrl-0 = <&pinctrl_usdhc3>;
  567. bus-width = <8>;
  568. no-1-8-v;
  569. non-removable;
  570. no-sdio;
  571. no-sd;
  572. keep-power-in-suspend;
  573. status = "okay";
  574. };
  575. &wdog1 {
  576. status = "disabled";
  577. };
  578. &snvs_rtc {
  579. status = "disabled";
  580. };
  581. &iomuxc {
  582. pinctrl_ecspi1: ecspi1grp {
  583. fsl,pins = <
  584. MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2
  585. MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2
  586. MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2
  587. MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59
  588. >;
  589. };
  590. pinctrl_enet1: enet1grp {
  591. fsl,pins = <
  592. MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
  593. MX7D_PAD_SD2_WP__ENET1_MDC 0x3
  594. MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
  595. MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
  596. MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
  597. MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
  598. MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
  599. MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
  600. MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
  601. MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
  602. MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
  603. MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
  604. MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
  605. MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
  606. >;
  607. };
  608. pinctrl_enet2: enet2grp {
  609. fsl,pins = <
  610. MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
  611. MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
  612. MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
  613. MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
  614. MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
  615. MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
  616. MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
  617. MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
  618. MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
  619. MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
  620. MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
  621. MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
  622. MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x1
  623. >;
  624. };
  625. pinctrl_flexcan1: flexcan1grp {
  626. fsl,pins = <
  627. MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x59
  628. MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x59
  629. >;
  630. };
  631. pinctrl_flexcan1_stby: flexcan1stbygrp {
  632. fsl,pins = <
  633. MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x59
  634. >;
  635. };
  636. pinctrl_flexcan2: flexcan2grp {
  637. fsl,pins = <
  638. MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
  639. MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
  640. >;
  641. };
  642. pinctrl_flexcan2_stby: flexcan2stbygrp {
  643. fsl,pins = <
  644. MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
  645. >;
  646. };
  647. pinctrl_gpio1: gpio1grp {
  648. fsl,pins = <
  649. MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x00
  650. MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x00
  651. >;
  652. };
  653. pinctrl_gpio2: gpio2grp {
  654. fsl,pins = <
  655. MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x00
  656. MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x00
  657. MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x00
  658. MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x03
  659. MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x03
  660. MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x03
  661. MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x03
  662. MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x03
  663. MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x00
  664. MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x00
  665. >;
  666. };
  667. pinctrl_i2c1: i2c1grp {
  668. fsl,pins = <
  669. MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
  670. MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
  671. >;
  672. };
  673. pinctrl_i2c2: i2c2grp {
  674. fsl,pins = <
  675. MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
  676. MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
  677. >;
  678. };
  679. pinctrl_i2c3: i2c3grp {
  680. fsl,pins = <
  681. MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
  682. MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
  683. >;
  684. };
  685. pinctrl_i2c3_gpio: i2c3gpiogrp {
  686. fsl,pins = <
  687. MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x4000007f
  688. MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x4000007f
  689. >;
  690. };
  691. pinctrl_i2c4: i2c4grp {
  692. fsl,pins = <
  693. MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
  694. MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
  695. >;
  696. };
  697. pinctrl_i2c4_gpio: i2c4gpiogrp {
  698. fsl,pins = <
  699. MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x4000007f
  700. MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x4000007f
  701. >;
  702. };
  703. pinctrl_leds_debug: debuggrp {
  704. fsl,pins = <
  705. MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59
  706. >;
  707. };
  708. pinctrl_sai1: sai1grp {
  709. fsl,pins = <
  710. MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f
  711. MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
  712. MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30
  713. >;
  714. };
  715. pinctrl_sai2: sai2grp {
  716. fsl,pins = <
  717. MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f
  718. MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f
  719. MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30
  720. >;
  721. };
  722. pinctrl_sai3: sai3grp {
  723. fsl,pins = <
  724. MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f
  725. MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f
  726. MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30
  727. >;
  728. };
  729. pinctrl_tpa1: tpa6130-1grp {
  730. fsl,pins = <
  731. MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x40000038
  732. >;
  733. };
  734. pinctrl_tpa2: tpa6130-2grp {
  735. fsl,pins = <
  736. MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x40000038
  737. >;
  738. };
  739. pinctrl_tpa3: tpa6130-3grp {
  740. fsl,pins = <
  741. MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x40000038
  742. >;
  743. };
  744. pinctrl_uart2: uart2grp {
  745. fsl,pins = <
  746. MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79
  747. MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79
  748. >;
  749. };
  750. pinctrl_uart4: uart4grp {
  751. fsl,pins = <
  752. MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79
  753. MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79
  754. >;
  755. };
  756. pinctrl_usdhc1: usdhc1grp {
  757. fsl,pins = <
  758. MX7D_PAD_SD1_CMD__SD1_CMD 0x59
  759. MX7D_PAD_SD1_CLK__SD1_CLK 0x19
  760. MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
  761. MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
  762. MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
  763. MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
  764. >;
  765. };
  766. pinctrl_usdhc3: usdhc3grp {
  767. fsl,pins = <
  768. MX7D_PAD_SD3_CMD__SD3_CMD 0x59
  769. MX7D_PAD_SD3_CLK__SD3_CLK 0x19
  770. MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
  771. MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
  772. MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
  773. MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
  774. MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
  775. MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
  776. MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
  777. MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
  778. MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59
  779. >;
  780. };
  781. };
  782. &iomuxc_lpsr {
  783. pinctrl_codec1: dac1grp {
  784. fsl,pins = <
  785. MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x40000038
  786. >;
  787. };
  788. pinctrl_codec2: dac2grp {
  789. fsl,pins = <
  790. MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x40000038
  791. >;
  792. };
  793. pinctrl_codec3: dac3grp {
  794. fsl,pins = <
  795. MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x40000038
  796. >;
  797. };
  798. pinctrl_switch: switchgrp {
  799. fsl,pins = <
  800. MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x08
  801. >;
  802. };
  803. };