imx7d-pico.dtsi 15 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. //
  3. // Copyright 2017 NXP
  4. /dts-v1/;
  5. #include "imx7d.dtsi"
  6. / {
  7. backlight: backlight {
  8. compatible = "pwm-backlight";
  9. pwms = <&pwm4 0 50000 0>;
  10. brightness-levels = <0 36 72 108 144 180 216 255>;
  11. default-brightness-level = <6>;
  12. };
  13. /* Will be filled by the bootloader */
  14. memory@80000000 {
  15. device_type = "memory";
  16. reg = <0x80000000 0>;
  17. };
  18. panel {
  19. compatible = "vxt,vl050-8048nt-c01";
  20. backlight = <&backlight>;
  21. power-supply = <&reg_lcd_3v3>;
  22. port {
  23. panel_in: endpoint {
  24. remote-endpoint = <&display_out>;
  25. };
  26. };
  27. };
  28. reg_lcd_3v3: regulator-lcd-3v3 {
  29. compatible = "regulator-fixed";
  30. pinctrl-names = "default";
  31. pinctrl-0 = <&pinctrl_reg_lcdreg_on>;
  32. regulator-name = "lcd-3v3";
  33. regulator-min-microvolt = <3300000>;
  34. regulator-max-microvolt = <3300000>;
  35. gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
  36. enable-active-high;
  37. };
  38. reg_wlreg_on: regulator-wlreg_on {
  39. compatible = "regulator-fixed";
  40. pinctrl-names = "default";
  41. pinctrl-0 = <&pinctrl_reg_wlreg_on>;
  42. regulator-name = "wlreg_on";
  43. regulator-min-microvolt = <3300000>;
  44. regulator-max-microvolt = <3300000>;
  45. gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
  46. enable-active-high;
  47. };
  48. reg_2p5v: regulator-2p5v {
  49. compatible = "regulator-fixed";
  50. regulator-name = "2P5V";
  51. regulator-min-microvolt = <2500000>;
  52. regulator-max-microvolt = <2500000>;
  53. regulator-always-on;
  54. };
  55. reg_3p3v: regulator-3p3v {
  56. compatible = "regulator-fixed";
  57. regulator-name = "3P3V";
  58. regulator-min-microvolt = <3300000>;
  59. regulator-max-microvolt = <3300000>;
  60. regulator-always-on;
  61. };
  62. reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  63. pinctrl-names = "default";
  64. pinctrl-0 = <&pinctrl_usbotg1_pwr>;
  65. compatible = "regulator-fixed";
  66. regulator-name = "usb_otg1_vbus";
  67. regulator-min-microvolt = <5000000>;
  68. regulator-max-microvolt = <5000000>;
  69. gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
  70. };
  71. reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
  72. compatible = "regulator-fixed";
  73. regulator-name = "usb_otg2_vbus";
  74. regulator-min-microvolt = <5000000>;
  75. regulator-max-microvolt = <5000000>;
  76. };
  77. reg_vref_1v8: regulator-vref-1v8 {
  78. compatible = "regulator-fixed";
  79. regulator-name = "vref-1v8";
  80. regulator-min-microvolt = <1800000>;
  81. regulator-max-microvolt = <1800000>;
  82. };
  83. usdhc2_pwrseq: usdhc2_pwrseq {
  84. compatible = "mmc-pwrseq-simple";
  85. clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
  86. clock-names = "ext_clock";
  87. };
  88. };
  89. &clks {
  90. assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
  91. <&clks IMX7D_CLKO2_ROOT_DIV>;
  92. assigned-clock-parents = <&clks IMX7D_CKIL>;
  93. assigned-clock-rates = <0>, <32768>;
  94. };
  95. &ecspi3 {
  96. cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
  97. pinctrl-names = "default";
  98. pinctrl-0 = <&pinctrl_ecspi3>;
  99. status = "okay";
  100. };
  101. &fec1 {
  102. pinctrl-names = "default";
  103. pinctrl-0 = <&pinctrl_enet1>;
  104. assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
  105. <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
  106. assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
  107. assigned-clock-rates = <0>, <100000000>;
  108. phy-mode = "rgmii-id";
  109. phy-handle = <&ethphy0>;
  110. fsl,magic-packet;
  111. phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
  112. status = "okay";
  113. mdio {
  114. #address-cells = <1>;
  115. #size-cells = <0>;
  116. ethphy0: ethernet-phy@1 {
  117. compatible = "ethernet-phy-ieee802.3-c22";
  118. reg = <1>;
  119. status = "okay";
  120. };
  121. };
  122. };
  123. &flexcan1 {
  124. pinctrl-names = "default";
  125. pinctrl-0 = <&pinctrl_can1>;
  126. status = "okay";
  127. };
  128. &flexcan2 {
  129. pinctrl-names = "default";
  130. pinctrl-0 = <&pinctrl_can2>;
  131. status = "okay";
  132. };
  133. &i2c1 {
  134. clock-frequency = <100000>;
  135. pinctrl-names = "default";
  136. pinctrl-0 = <&pinctrl_i2c1>;
  137. status = "okay";
  138. };
  139. &i2c2 {
  140. pinctrl-names = "default";
  141. pinctrl-0 = <&pinctrl_i2c2>;
  142. status = "okay";
  143. };
  144. &i2c4 {
  145. pinctrl-names = "default";
  146. pinctrl-0 = <&pinctrl_i2c4>;
  147. status = "okay";
  148. pmic: pfuze3000@8 {
  149. compatible = "fsl,pfuze3000";
  150. reg = <0x08>;
  151. regulators {
  152. sw1a_reg: sw1a {
  153. regulator-min-microvolt = <700000>;
  154. regulator-max-microvolt = <3300000>;
  155. regulator-boot-on;
  156. regulator-always-on;
  157. regulator-ramp-delay = <6250>;
  158. };
  159. /* use sw1c_reg to align with pfuze100/pfuze200 */
  160. sw1c_reg: sw1b {
  161. regulator-min-microvolt = <700000>;
  162. regulator-max-microvolt = <1475000>;
  163. regulator-boot-on;
  164. regulator-always-on;
  165. regulator-ramp-delay = <6250>;
  166. };
  167. sw2_reg: sw2 {
  168. regulator-min-microvolt = <1800000>;
  169. regulator-max-microvolt = <1850000>;
  170. regulator-boot-on;
  171. regulator-always-on;
  172. };
  173. sw3a_reg: sw3 {
  174. regulator-min-microvolt = <900000>;
  175. regulator-max-microvolt = <1650000>;
  176. regulator-boot-on;
  177. regulator-always-on;
  178. };
  179. swbst_reg: swbst {
  180. regulator-min-microvolt = <5000000>;
  181. regulator-max-microvolt = <5150000>;
  182. };
  183. snvs_reg: vsnvs {
  184. regulator-min-microvolt = <1000000>;
  185. regulator-max-microvolt = <3000000>;
  186. regulator-boot-on;
  187. regulator-always-on;
  188. };
  189. vref_reg: vrefddr {
  190. regulator-boot-on;
  191. regulator-always-on;
  192. };
  193. vgen1_reg: vldo1 {
  194. regulator-min-microvolt = <1800000>;
  195. regulator-max-microvolt = <3300000>;
  196. regulator-always-on;
  197. };
  198. vgen2_reg: vldo2 {
  199. regulator-min-microvolt = <800000>;
  200. regulator-max-microvolt = <1550000>;
  201. };
  202. vgen3_reg: vccsd {
  203. regulator-min-microvolt = <2850000>;
  204. regulator-max-microvolt = <3300000>;
  205. regulator-always-on;
  206. };
  207. vgen4_reg: v33 {
  208. regulator-min-microvolt = <2850000>;
  209. regulator-max-microvolt = <3300000>;
  210. regulator-always-on;
  211. };
  212. vgen5_reg: vldo3 {
  213. regulator-min-microvolt = <1800000>;
  214. regulator-max-microvolt = <3300000>;
  215. regulator-always-on;
  216. };
  217. vgen6_reg: vldo4 {
  218. regulator-min-microvolt = <1800000>;
  219. regulator-max-microvolt = <3300000>;
  220. regulator-always-on;
  221. };
  222. };
  223. };
  224. };
  225. &lcdif {
  226. pinctrl-names = "default";
  227. pinctrl-0 = <&pinctrl_lcdif>;
  228. status = "okay";
  229. port {
  230. display_out: endpoint {
  231. remote-endpoint = <&panel_in>;
  232. };
  233. };
  234. };
  235. &sai1 {
  236. pinctrl-names = "default";
  237. pinctrl-0 = <&pinctrl_sai1>;
  238. assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
  239. <&clks IMX7D_SAI1_ROOT_CLK>;
  240. assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
  241. assigned-clock-rates = <0>, <24576000>;
  242. status = "okay";
  243. };
  244. &pwm1 {
  245. pinctrl-names = "default";
  246. pinctrl-0 = <&pinctrl_pwm1>;
  247. status = "okay";
  248. };
  249. &pwm2 {
  250. pinctrl-names = "default";
  251. pinctrl-0 = <&pinctrl_pwm2>;
  252. status = "okay";
  253. };
  254. &pwm3 {
  255. pinctrl-names = "default";
  256. pinctrl-0 = <&pinctrl_pwm3>;
  257. status = "okay";
  258. };
  259. &pwm4 { /* Backlight */
  260. pinctrl-names = "default";
  261. pinctrl-0 = <&pinctrl_pwm4>;
  262. status = "okay";
  263. };
  264. &uart5 {
  265. pinctrl-names = "default";
  266. pinctrl-0 = <&pinctrl_uart5>;
  267. assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
  268. assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
  269. status = "okay";
  270. };
  271. &uart6 {
  272. pinctrl-names = "default";
  273. pinctrl-0 = <&pinctrl_uart6>;
  274. assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
  275. assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
  276. uart-has-rtscts;
  277. status = "okay";
  278. };
  279. &uart7 { /* Bluetooth */
  280. pinctrl-names = "default";
  281. pinctrl-0 = <&pinctrl_uart7>;
  282. assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
  283. assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
  284. uart-has-rtscts;
  285. status = "okay";
  286. };
  287. &usbotg1 {
  288. vbus-supply = <&reg_usb_otg1_vbus>;
  289. status = "okay";
  290. };
  291. &usbotg2 {
  292. vbus-supply = <&reg_usb_otg2_vbus>;
  293. dr_mode = "host";
  294. status = "okay";
  295. };
  296. &usdhc1 {
  297. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  298. pinctrl-0 = <&pinctrl_usdhc1>;
  299. pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
  300. pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
  301. cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
  302. bus-width = <4>;
  303. fsl,tuning-step = <2>;
  304. vmmc-supply = <&reg_3p3v>;
  305. wakeup-source;
  306. no-1-8-v;
  307. keep-power-in-suspend;
  308. status = "okay";
  309. };
  310. &usdhc2 { /* Wifi SDIO */
  311. pinctrl-names = "default";
  312. pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>;
  313. no-1-8-v;
  314. non-removable;
  315. keep-power-in-suspend;
  316. wakeup-source;
  317. vmmc-supply = <&reg_wlreg_on>;
  318. mmc-pwrseq = <&usdhc2_pwrseq>;
  319. status = "okay";
  320. };
  321. &usdhc3 {
  322. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  323. pinctrl-0 = <&pinctrl_usdhc3>;
  324. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  325. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  326. assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
  327. assigned-clock-rates = <400000000>;
  328. bus-width = <8>;
  329. no-1-8-v;
  330. fsl,tuning-step = <2>;
  331. non-removable;
  332. status = "okay";
  333. };
  334. &wdog1 {
  335. pinctrl-names = "default";
  336. pinctrl-0 = <&pinctrl_wdog>;
  337. fsl,ext-reset-output;
  338. status = "okay";
  339. };
  340. &iomuxc {
  341. pinctrl_ecspi3: ecspi3grp {
  342. fsl,pins = <
  343. MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2
  344. MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2
  345. MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2
  346. MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14
  347. >;
  348. };
  349. pinctrl_i2c1: i2c1grp {
  350. fsl,pins = <
  351. MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f
  352. MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f
  353. >;
  354. };
  355. pinctrl_i2c2: i2c2grp {
  356. fsl,pins = <
  357. MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x4000007f
  358. MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x4000007f
  359. >;
  360. };
  361. pinctrl_enet1: enet1grp {
  362. fsl,pins = <
  363. MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
  364. MX7D_PAD_SD2_WP__ENET1_MDC 0x3
  365. MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
  366. MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
  367. MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
  368. MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
  369. MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
  370. MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
  371. MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
  372. MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
  373. MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
  374. MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
  375. MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
  376. MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
  377. MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */
  378. >;
  379. };
  380. pinctrl_can1: can1frp {
  381. fsl,pins = <
  382. MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59
  383. MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59
  384. >;
  385. };
  386. pinctrl_can2: can2frp {
  387. fsl,pins = <
  388. MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59
  389. MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59
  390. >;
  391. };
  392. pinctrl_i2c4: i2c4grp {
  393. fsl,pins = <
  394. MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
  395. MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
  396. >;
  397. };
  398. pinctrl_lcdif: lcdifgrp {
  399. fsl,pins = <
  400. MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
  401. MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
  402. MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
  403. MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
  404. MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
  405. MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
  406. MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
  407. MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
  408. MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
  409. MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
  410. MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
  411. MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
  412. MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
  413. MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
  414. MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
  415. MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
  416. MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
  417. MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
  418. MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
  419. MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
  420. MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
  421. MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
  422. MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
  423. MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
  424. MX7D_PAD_LCD_CLK__LCD_CLK 0x79
  425. MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x78
  426. MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x78
  427. MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x78
  428. MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14
  429. >;
  430. };
  431. pinctrl_pwm1: pwm1 {
  432. fsl,pins = <
  433. MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f
  434. >;
  435. };
  436. pinctrl_pwm2: pwm2 {
  437. fsl,pins = <
  438. MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f
  439. >;
  440. };
  441. pinctrl_pwm3: pwm3 {
  442. fsl,pins = <
  443. MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f
  444. >;
  445. };
  446. pinctrl_pwm4: pwm4grp{
  447. fsl,pins = <
  448. MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x7f
  449. >;
  450. };
  451. pinctrl_reg_wlreg_on: regregongrp {
  452. fsl,pins = <
  453. MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59
  454. >;
  455. };
  456. pinctrl_sai1: sai1grp {
  457. fsl,pins = <
  458. MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
  459. MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
  460. MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
  461. MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
  462. >;
  463. };
  464. pinctrl_uart5: uart5grp {
  465. fsl,pins = <
  466. MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79
  467. MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79
  468. >;
  469. };
  470. pinctrl_uart6: uart6grp {
  471. fsl,pins = <
  472. MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79
  473. MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79
  474. MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x79
  475. MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x79
  476. >;
  477. };
  478. pinctrl_uart7: uart7grp {
  479. fsl,pins = <
  480. MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x79
  481. MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x79
  482. MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x79
  483. MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x79
  484. >;
  485. };
  486. pinctrl_usbotg1_pwr: usbotg_pwr {
  487. fsl,pins = <
  488. MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14
  489. >;
  490. };
  491. pinctrl_usdhc1: usdhc1grp {
  492. fsl,pins = <
  493. MX7D_PAD_SD1_CMD__SD1_CMD 0x59
  494. MX7D_PAD_SD1_CLK__SD1_CLK 0x19
  495. MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
  496. MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
  497. MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
  498. MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
  499. MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
  500. >;
  501. };
  502. pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
  503. fsl,pins = <
  504. MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
  505. MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
  506. MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
  507. MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
  508. MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
  509. MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
  510. MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
  511. >;
  512. };
  513. pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
  514. fsl,pins = <
  515. MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
  516. MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
  517. MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
  518. MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
  519. MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
  520. MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
  521. MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
  522. >;
  523. };
  524. pinctrl_usdhc2: usdhc2grp {
  525. fsl,pins = <
  526. MX7D_PAD_SD2_CMD__SD2_CMD 0x59
  527. MX7D_PAD_SD2_CLK__SD2_CLK 0x19
  528. MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
  529. MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
  530. MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
  531. MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
  532. >;
  533. };
  534. pinctrl_usdhc3: usdhc3grp {
  535. fsl,pins = <
  536. MX7D_PAD_SD3_CMD__SD3_CMD 0x59
  537. MX7D_PAD_SD3_CLK__SD3_CLK 0x19
  538. MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
  539. MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
  540. MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
  541. MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
  542. MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
  543. MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
  544. MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
  545. MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
  546. >;
  547. };
  548. pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
  549. fsl,pins = <
  550. MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
  551. MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
  552. MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
  553. MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
  554. MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
  555. MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
  556. MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
  557. MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
  558. MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
  559. MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
  560. >;
  561. };
  562. pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
  563. fsl,pins = <
  564. MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
  565. MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
  566. MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
  567. MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
  568. MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
  569. MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
  570. MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
  571. MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
  572. MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
  573. MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
  574. >;
  575. };
  576. };
  577. &iomuxc_lpsr {
  578. pinctrl_wifi_clk: wificlkgrp {
  579. fsl,pins = <
  580. MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d
  581. >;
  582. };
  583. pinctrl_reg_lcdreg_on: reglcdongrp {
  584. fsl,pins = <
  585. MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x59
  586. >;
  587. };
  588. pinctrl_wdog: wdoggrp {
  589. fsl,pins = <
  590. MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
  591. >;
  592. };
  593. };