imx7-tqma7.dtsi 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR X11
  2. /*
  3. * Device Tree Include file for TQ-Systems TQMa7x boards with full mounted PCB.
  4. *
  5. * Copyright (C) 2016 TQ-Systems GmbH
  6. * Author: Markus Niebel <[email protected]>
  7. * Copyright (C) 2019 Bruno Thomsen <[email protected]>
  8. */
  9. / {
  10. memory@80000000 {
  11. device_type = "memory";
  12. /* 512 MB - default configuration */
  13. reg = <0x80000000 0x20000000>;
  14. };
  15. };
  16. &cpu0 {
  17. cpu-supply = <&sw1a_reg>;
  18. };
  19. &gpio2 {
  20. /* Configured as pullup by QSPI pin group */
  21. qspi-reset-hog {
  22. gpio-hog;
  23. gpios = <4 GPIO_ACTIVE_LOW>;
  24. input;
  25. line-name = "qspi-reset";
  26. };
  27. };
  28. &i2c1 {
  29. pinctrl-names = "default";
  30. pinctrl-0 = <&pinctrl_i2c1>;
  31. clock-frequency = <100000>;
  32. status = "okay";
  33. pfuze3000: pmic@8 {
  34. pinctrl-names = "default";
  35. pinctrl-0 = <&pinctrl_pmic1>;
  36. compatible = "fsl,pfuze3000";
  37. reg = <0x08>;
  38. regulators {
  39. sw1a_reg: sw1a {
  40. regulator-min-microvolt = <700000>;
  41. regulator-max-microvolt = <3300000>;
  42. regulator-boot-on;
  43. regulator-always-on;
  44. regulator-ramp-delay = <6250>;
  45. };
  46. /* use sw1c_reg to align with pfuze100/pfuze200 */
  47. sw1c_reg: sw1b {
  48. regulator-min-microvolt = <700000>;
  49. regulator-max-microvolt = <1475000>;
  50. regulator-boot-on;
  51. regulator-always-on;
  52. regulator-ramp-delay = <6250>;
  53. };
  54. sw2_reg: sw2 {
  55. regulator-min-microvolt = <1500000>;
  56. regulator-max-microvolt = <1850000>;
  57. regulator-boot-on;
  58. regulator-always-on;
  59. };
  60. sw3a_reg: sw3 {
  61. regulator-min-microvolt = <900000>;
  62. regulator-max-microvolt = <1650000>;
  63. regulator-boot-on;
  64. regulator-always-on;
  65. };
  66. swbst_reg: swbst {
  67. regulator-min-microvolt = <5000000>;
  68. regulator-max-microvolt = <5150000>;
  69. };
  70. snvs_reg: vsnvs {
  71. regulator-min-microvolt = <1000000>;
  72. regulator-max-microvolt = <3000000>;
  73. regulator-boot-on;
  74. regulator-always-on;
  75. };
  76. vref_reg: vrefddr {
  77. regulator-boot-on;
  78. regulator-always-on;
  79. };
  80. vgen1_reg: vldo1 {
  81. regulator-min-microvolt = <1800000>;
  82. regulator-max-microvolt = <3300000>;
  83. regulator-always-on;
  84. };
  85. vgen2_reg: vldo2 {
  86. regulator-min-microvolt = <800000>;
  87. regulator-max-microvolt = <1550000>;
  88. regulator-always-on;
  89. };
  90. vgen3_reg: vccsd {
  91. regulator-min-microvolt = <2850000>;
  92. regulator-max-microvolt = <3300000>;
  93. regulator-always-on;
  94. };
  95. vgen4_reg: v33 {
  96. regulator-min-microvolt = <2850000>;
  97. regulator-max-microvolt = <3300000>;
  98. regulator-always-on;
  99. };
  100. vgen5_reg: vldo3 {
  101. regulator-min-microvolt = <1800000>;
  102. regulator-max-microvolt = <3300000>;
  103. regulator-always-on;
  104. };
  105. vgen6_reg: vldo4 {
  106. regulator-min-microvolt = <1800000>;
  107. regulator-max-microvolt = <3300000>;
  108. regulator-always-on;
  109. };
  110. };
  111. };
  112. /* NXP SE97BTP with temperature sensor + eeprom */
  113. se97b: temperature-sensor-eeprom@1e {
  114. compatible = "nxp,se97b", "jedec,jc-42.4-temp";
  115. reg = <0x1e>;
  116. status = "okay";
  117. };
  118. /* ST M24C64 */
  119. m24c64: eeprom@50 {
  120. compatible = "atmel,24c64";
  121. reg = <0x50>;
  122. pagesize = <32>;
  123. status = "okay";
  124. };
  125. at24c02: eeprom@56 {
  126. compatible = "atmel,24c02";
  127. reg = <0x56>;
  128. pagesize = <16>;
  129. status = "okay";
  130. };
  131. ds1339: rtc@68 {
  132. compatible = "dallas,ds1339";
  133. reg = <0x68>;
  134. };
  135. };
  136. &iomuxc {
  137. pinctrl_i2c1: i2c1grp {
  138. fsl,pins = <
  139. MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078
  140. MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078
  141. >;
  142. };
  143. pinctrl_pmic1: pmic1grp {
  144. fsl,pins = <
  145. MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C
  146. >;
  147. };
  148. pinctrl_qspi: qspigrp {
  149. fsl,pins = <
  150. MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A
  151. MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A
  152. MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A
  153. MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A
  154. MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11
  155. MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54
  156. MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54
  157. >;
  158. };
  159. pinctrl_qspi_reset: qspi_resetgrp {
  160. fsl,pins = <
  161. /* #QSPI_RESET */
  162. MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52
  163. >;
  164. };
  165. pinctrl_usdhc3: usdhc3grp {
  166. fsl,pins = <
  167. MX7D_PAD_SD3_CMD__SD3_CMD 0x59
  168. MX7D_PAD_SD3_CLK__SD3_CLK 0x56
  169. MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
  170. MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
  171. MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
  172. MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
  173. MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
  174. MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
  175. MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
  176. MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
  177. MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
  178. >;
  179. };
  180. pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
  181. fsl,pins = <
  182. MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
  183. MX7D_PAD_SD3_CLK__SD3_CLK 0x51
  184. MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
  185. MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
  186. MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
  187. MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
  188. MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
  189. MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
  190. MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
  191. MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
  192. MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
  193. >;
  194. };
  195. pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
  196. fsl,pins = <
  197. MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
  198. MX7D_PAD_SD3_CLK__SD3_CLK 0x51
  199. MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
  200. MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
  201. MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
  202. MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
  203. MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
  204. MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
  205. MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
  206. MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
  207. MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
  208. >;
  209. };
  210. };
  211. &iomuxc_lpsr {
  212. pinctrl_wdog1: wdog1grp {
  213. fsl,pins = <
  214. MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30
  215. >;
  216. };
  217. };
  218. &qspi {
  219. pinctrl-names = "default";
  220. pinctrl-0 = <&pinctrl_qspi &pinctrl_qspi_reset>;
  221. status = "okay";
  222. flash0: flash@0 {
  223. compatible = "jedec,spi-nor";
  224. reg = <0>;
  225. spi-max-frequency = <29000000>;
  226. spi-rx-bus-width = <4>;
  227. spi-tx-bus-width = <4>;
  228. };
  229. };
  230. &sdma {
  231. status = "okay";
  232. };
  233. &usdhc3 {
  234. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  235. pinctrl-0 = <&pinctrl_usdhc3>;
  236. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  237. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  238. assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
  239. assigned-clock-rates = <400000000>;
  240. bus-width = <8>;
  241. non-removable;
  242. vmmc-supply = <&vgen4_reg>;
  243. vqmmc-supply = <&sw2_reg>;
  244. status = "okay";
  245. };
  246. &wdog1 {
  247. pinctrl-names = "default";
  248. pinctrl-0 = <&pinctrl_wdog1>;
  249. /*
  250. * Errata e10574:
  251. * WDOG reset needs to run with WDOG_RESET_B signal enabled.
  252. * X1-51 (WDOG1#) signal needs carrier board handling to reset
  253. * TQMa7 on X1-22 (RESET_IN#).
  254. */
  255. fsl,ext-reset-output;
  256. status = "okay";
  257. };