imx7-mba7.dtsi 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR X11
  2. /*
  3. * Device Tree Include file for TQ-Systems MBa7 carrier board.
  4. *
  5. * Copyright (C) 2016 TQ-Systems GmbH
  6. * Author: Markus Niebel <[email protected]>
  7. * Copyright (C) 2019 Bruno Thomsen <[email protected]>
  8. *
  9. * Note: This file does not include nodes for all peripheral devices.
  10. * As device driver coverage increases additional nodes can be added.
  11. */
  12. #include <dt-bindings/input/input.h>
  13. #include <dt-bindings/net/ti-dp83867.h>
  14. / {
  15. aliases {
  16. mmc0 = &usdhc3;
  17. mmc1 = &usdhc1;
  18. /delete-property/ mmc2;
  19. };
  20. beeper {
  21. compatible = "gpio-beeper";
  22. gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>;
  23. };
  24. chosen {
  25. stdout-path = &uart6;
  26. };
  27. gpio_buttons: gpio-keys {
  28. compatible = "gpio-keys";
  29. button-0 {
  30. /* #SWITCH_A */
  31. label = "S11";
  32. linux,code = <KEY_1>;
  33. gpios = <&pca9555 13 GPIO_ACTIVE_LOW>;
  34. };
  35. button-1 {
  36. /* #SWITCH_B */
  37. label = "S12";
  38. linux,code = <KEY_2>;
  39. gpios = <&pca9555 14 GPIO_ACTIVE_LOW>;
  40. };
  41. button-2 {
  42. /* #SWITCH_C */
  43. label = "S13";
  44. linux,code = <KEY_3>;
  45. gpios = <&pca9555 15 GPIO_ACTIVE_LOW>;
  46. };
  47. };
  48. gpio-leds {
  49. compatible = "gpio-leds";
  50. led1 {
  51. label = "led1";
  52. gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>;
  53. linux,default-trigger = "default-on";
  54. };
  55. led2 {
  56. label = "led2";
  57. gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>;
  58. linux,default-trigger = "heartbeat";
  59. };
  60. };
  61. reg_sd1_vmmc: regulator-sd1-vmmc {
  62. compatible = "regulator-fixed";
  63. regulator-name = "VCC3V3_SD1";
  64. regulator-min-microvolt = <3300000>;
  65. regulator-max-microvolt = <3300000>;
  66. regulator-always-on;
  67. };
  68. reg_fec1_pwdn: regulator-fec1-pwdn {
  69. compatible = "regulator-fixed";
  70. regulator-name = "PWDN_FEC1";
  71. regulator-min-microvolt = <3300000>;
  72. regulator-max-microvolt = <3300000>;
  73. regulator-always-on;
  74. gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  75. enable-active-high;
  76. };
  77. reg_fec2_pwdn: regulator-fec2-pwdn {
  78. compatible = "regulator-fixed";
  79. regulator-name = "PWDN_FEC2";
  80. regulator-min-microvolt = <3300000>;
  81. regulator-max-microvolt = <3300000>;
  82. regulator-always-on;
  83. gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
  84. enable-active-high;
  85. };
  86. reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  87. compatible = "regulator-fixed";
  88. regulator-name = "VBUS_USBOTG1";
  89. regulator-min-microvolt = <5000000>;
  90. regulator-max-microvolt = <5000000>;
  91. gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  92. enable-active-high;
  93. };
  94. reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
  95. compatible = "regulator-fixed";
  96. regulator-name = "VBUS_USBOTG2";
  97. regulator-min-microvolt = <5000000>;
  98. regulator-max-microvolt = <5000000>;
  99. gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
  100. enable-active-high;
  101. };
  102. reg_mpcie_1v5: regulator-mpcie-1v5 {
  103. compatible = "regulator-fixed";
  104. regulator-name = "VCC1V5_MPCIE";
  105. regulator-min-microvolt = <1500000>;
  106. regulator-max-microvolt = <1500000>;
  107. gpio = <&pca9555 12 GPIO_ACTIVE_HIGH>;
  108. enable-active-high;
  109. regulator-always-on;
  110. };
  111. reg_mpcie_3v3: regulator-mpcie-3v3 {
  112. compatible = "regulator-fixed";
  113. regulator-name = "VCC3V3_MPCIE";
  114. regulator-min-microvolt = <3300000>;
  115. regulator-max-microvolt = <3300000>;
  116. gpio = <&pca9555 10 GPIO_ACTIVE_HIGH>;
  117. enable-active-high;
  118. regulator-always-on;
  119. };
  120. reg_mba_12v0: regulator-mba-12v0 {
  121. compatible = "regulator-fixed";
  122. regulator-name = "VCC12V0_MBA7";
  123. regulator-min-microvolt = <12000000>;
  124. regulator-max-microvolt = <12000000>;
  125. gpio = <&pca9555 11 GPIO_ACTIVE_HIGH>;
  126. enable-active-high;
  127. };
  128. reg_lvds_transmitter: regulator-lvds-transmitter {
  129. compatible = "regulator-fixed";
  130. regulator-name = "#SHTDN_LVDS";
  131. regulator-min-microvolt = <3300000>;
  132. regulator-max-microvolt = <3300000>;
  133. gpio = <&pca9555 1 GPIO_ACTIVE_HIGH>;
  134. enable-active-high;
  135. };
  136. reg_vref_1v8: regulator-vref-1v8 {
  137. compatible = "regulator-fixed";
  138. regulator-name = "VCC1V8_REF";
  139. regulator-min-microvolt = <1800000>;
  140. regulator-max-microvolt = <1800000>;
  141. regulator-always-on;
  142. vin-supply = <&sw2_reg>;
  143. };
  144. reg_audio_3v3: regulator-audio-3v3 {
  145. compatible = "regulator-fixed";
  146. regulator-name = "VCC3V3_AUDIO";
  147. regulator-min-microvolt = <3300000>;
  148. regulator-max-microvolt = <3300000>;
  149. regulator-always-on;
  150. };
  151. sound {
  152. compatible = "fsl,imx-audio-tlv320aic32x4";
  153. model = "imx-audio-tlv320aic32x4";
  154. ssi-controller = <&sai1>;
  155. audio-codec = <&tlv320aic32x4>;
  156. audio-routing =
  157. "IN3_L", "Mic Jack",
  158. "Mic Jack", "Mic Bias",
  159. "IN1_L", "Line In Jack",
  160. "IN1_R", "Line In Jack",
  161. "Line Out Jack", "LOL",
  162. "Line Out Jack", "LOR";
  163. };
  164. };
  165. &adc1 {
  166. vref-supply = <&reg_vref_1v8>;
  167. status = "okay";
  168. };
  169. &adc2 {
  170. vref-supply = <&reg_vref_1v8>;
  171. status = "okay";
  172. };
  173. &ecspi1 {
  174. pinctrl-names = "default";
  175. pinctrl-0 = <&pinctrl_ecspi1>;
  176. cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>,
  177. <&gpio4 2 GPIO_ACTIVE_LOW>;
  178. status = "okay";
  179. };
  180. &ecspi2 {
  181. pinctrl-names = "default";
  182. pinctrl-0 = <&pinctrl_ecspi2>;
  183. status = "okay";
  184. };
  185. &fec1 {
  186. pinctrl-names = "default";
  187. pinctrl-0 = <&pinctrl_enet1>;
  188. phy-mode = "rgmii-id";
  189. phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
  190. phy-reset-duration = <1>;
  191. phy-supply = <&reg_fec1_pwdn>;
  192. phy-handle = <&ethphy1_0>;
  193. fsl,magic-packet;
  194. status = "okay";
  195. mdio {
  196. #address-cells = <1>;
  197. #size-cells = <0>;
  198. ethphy1_0: ethernet-phy@0 {
  199. compatible = "ethernet-phy-ieee802.3-c22";
  200. reg = <0>;
  201. ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
  202. ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
  203. ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  204. ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
  205. };
  206. };
  207. };
  208. &flash0 {
  209. partitions {
  210. compatible = "fixed-partitions";
  211. #address-cells = <1>;
  212. #size-cells = <1>;
  213. uboot@0 {
  214. label = "U-Boot";
  215. reg = <0x0 0xd0000>;
  216. };
  217. env1@d0000 {
  218. label = "ENV1";
  219. reg = <0xd0000 0x10000>;
  220. };
  221. env2@e0000 {
  222. label = "ENV2";
  223. reg = <0xe0000 0x10000>;
  224. };
  225. dtb@f0000 {
  226. label = "DTB";
  227. reg = <0xf0000 0x10000>;
  228. };
  229. linux@100000 {
  230. label = "Linux";
  231. reg = <0x100000 0x700000>;
  232. };
  233. rootfs@800000 {
  234. label = "RootFS";
  235. reg = <0x800000 0x3800000>;
  236. };
  237. };
  238. };
  239. &flexcan1 {
  240. pinctrl-names = "default";
  241. pinctrl-0 = <&pinctrl_flexcan1>;
  242. status = "okay";
  243. };
  244. &flexcan2 {
  245. pinctrl-names = "default";
  246. pinctrl-0 = <&pinctrl_flexcan2>;
  247. status = "okay";
  248. };
  249. &i2c1 {
  250. lm75: temperature-sensor@49 {
  251. compatible = "national,lm75";
  252. reg = <0x49>;
  253. };
  254. };
  255. &i2c2 {
  256. clock-frequency = <100000>;
  257. pinctrl-names = "default";
  258. pinctrl-0 = <&pinctrl_i2c2>;
  259. status = "okay";
  260. tlv320aic32x4: audio-codec@18 {
  261. compatible = "ti,tlv320aic32x4";
  262. reg = <0x18>;
  263. clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
  264. clock-names = "mclk";
  265. ldoin-supply = <&reg_audio_3v3>;
  266. iov-supply = <&reg_audio_3v3>;
  267. };
  268. pca9555: gpio-expander@20 {
  269. compatible = "nxp,pca9555";
  270. reg = <0x20>;
  271. pinctrl-names = "default";
  272. pinctrl-0 = <&pinctrl_pca9555>;
  273. gpio-controller;
  274. #gpio-cells = <2>;
  275. interrupt-parent = <&gpio7>;
  276. interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
  277. interrupt-controller;
  278. #interrupt-cells = <2>;
  279. };
  280. };
  281. &i2c3 {
  282. clock-frequency = <100000>;
  283. pinctrl-names = "default";
  284. pinctrl-0 = <&pinctrl_i2c3>;
  285. status = "okay";
  286. };
  287. &iomuxc {
  288. pinctrl-names = "default";
  289. pinctrl-0 = <&pinctrl_hog_mba7_1>;
  290. pinctrl_ecspi1: ecspi1grp {
  291. fsl,pins = <
  292. MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c
  293. MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74
  294. MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74
  295. MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74
  296. MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74
  297. MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74
  298. >;
  299. };
  300. pinctrl_ecspi2: ecspi2grp {
  301. fsl,pins = <
  302. MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c
  303. MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74
  304. MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74
  305. MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74
  306. >;
  307. };
  308. pinctrl_enet1: enet1grp {
  309. fsl,pins = <
  310. MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02
  311. MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00
  312. MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71
  313. MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71
  314. MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71
  315. MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71
  316. MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71
  317. MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71
  318. MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79
  319. MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79
  320. MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79
  321. MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79
  322. MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79
  323. MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79
  324. /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
  325. MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070
  326. /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
  327. MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078
  328. >;
  329. };
  330. pinctrl_flexcan1: flexcan1grp {
  331. fsl,pins = <
  332. MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a
  333. MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52
  334. >;
  335. };
  336. pinctrl_flexcan2: flexcan2grp {
  337. fsl,pins = <
  338. MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a
  339. MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52
  340. >;
  341. };
  342. pinctrl_hog_mba7_1: hogmba71grp {
  343. fsl,pins = <
  344. /* Limitation: WDOG2_B / WDOG2_RESET not usable */
  345. MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c
  346. MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074
  347. /* #BOOT_EN */
  348. MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010
  349. >;
  350. };
  351. pinctrl_i2c2: i2c2grp {
  352. fsl,pins = <
  353. MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078
  354. MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078
  355. >;
  356. };
  357. pinctrl_i2c3: i2c3grp {
  358. fsl,pins = <
  359. MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078
  360. MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078
  361. >;
  362. };
  363. pinctrl_pca9555: pca95550grp {
  364. fsl,pins = <
  365. MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78
  366. >;
  367. };
  368. pinctrl_sai1: sai1grp {
  369. fsl,pins = <
  370. MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11
  371. MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c
  372. MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c
  373. MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c
  374. MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c
  375. MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14
  376. MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14
  377. >;
  378. };
  379. pinctrl_uart3: uart3grp {
  380. fsl,pins = <
  381. MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e
  382. MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76
  383. MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76
  384. MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e
  385. >;
  386. };
  387. pinctrl_uart4: uart4grp {
  388. fsl,pins = <
  389. MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e
  390. MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76
  391. MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76
  392. MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e
  393. >;
  394. };
  395. pinctrl_uart5: uart5grp {
  396. fsl,pins = <
  397. MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e
  398. MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76
  399. >;
  400. };
  401. pinctrl_uart6: uart6grp {
  402. fsl,pins = <
  403. MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d
  404. MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75
  405. MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75
  406. MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d
  407. >;
  408. };
  409. pinctrl_uart7: uart7grp {
  410. fsl,pins = <
  411. MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e
  412. MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76
  413. MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76
  414. /* Limitation: RTS is not connected */
  415. MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e
  416. >;
  417. };
  418. pinctrl_usdhc1_gpio: usdhc1grp_gpio {
  419. fsl,pins = <
  420. /* WP */
  421. MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c
  422. /* CD */
  423. MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c
  424. /* VSELECT */
  425. MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59
  426. >;
  427. };
  428. pinctrl_usdhc1: usdhc1grp {
  429. fsl,pins = <
  430. MX7D_PAD_SD1_CMD__SD1_CMD 0x5e
  431. MX7D_PAD_SD1_CLK__SD1_CLK 0x57
  432. MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e
  433. MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e
  434. MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e
  435. MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e
  436. >;
  437. };
  438. pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
  439. fsl,pins = <
  440. MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
  441. MX7D_PAD_SD1_CLK__SD1_CLK 0x57
  442. MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
  443. MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
  444. MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
  445. MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
  446. >;
  447. };
  448. pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
  449. fsl,pins = <
  450. MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
  451. MX7D_PAD_SD1_CLK__SD1_CLK 0x57
  452. MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
  453. MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
  454. MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
  455. MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
  456. >;
  457. };
  458. };
  459. &iomuxc_lpsr {
  460. pinctrl_pwm1: pwm1grp {
  461. fsl,pins = <
  462. /* LCD_CONTRAST */
  463. MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50
  464. >;
  465. };
  466. pinctrl_usbotg1: usbotg1grp {
  467. fsl,pins = <
  468. MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c
  469. MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59
  470. >;
  471. };
  472. pinctrl_wdog1: wdog1grp {
  473. fsl,pins = <
  474. MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30
  475. >;
  476. };
  477. };
  478. &pwm1 {
  479. pinctrl-names = "default";
  480. pinctrl-0 = <&pinctrl_pwm1>;
  481. status = "okay";
  482. };
  483. &sai1 {
  484. pinctrl-names = "default";
  485. pinctrl-0 = <&pinctrl_sai1>;
  486. assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
  487. <&clks IMX7D_SAI1_ROOT_CLK>;
  488. assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
  489. assigned-clock-rates = <0>, <36864000>;
  490. status = "okay";
  491. };
  492. &uart3 {
  493. pinctrl-names = "default";
  494. pinctrl-0 = <&pinctrl_uart3>;
  495. assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
  496. assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
  497. status = "okay";
  498. };
  499. &uart4 {
  500. pinctrl-names = "default";
  501. pinctrl-0 = <&pinctrl_uart4>;
  502. assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
  503. assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
  504. status = "okay";
  505. };
  506. &uart5 {
  507. pinctrl-names = "default";
  508. pinctrl-0 = <&pinctrl_uart5>;
  509. assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
  510. assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
  511. status = "okay";
  512. };
  513. &uart6 {
  514. pinctrl-names = "default";
  515. pinctrl-0 = <&pinctrl_uart6>;
  516. assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
  517. assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
  518. status = "okay";
  519. };
  520. &uart7 {
  521. pinctrl-names = "default";
  522. pinctrl-0 = <&pinctrl_uart7>;
  523. assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
  524. assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
  525. uart-has-rtscts;
  526. linux,rs485-enabled-at-boot-time;
  527. rs485-rts-active-low;
  528. rs485-rx-during-tx;
  529. status = "okay";
  530. };
  531. &usbh {
  532. status = "okay";
  533. };
  534. &usbotg1 {
  535. pinctrl-names = "default";
  536. pinctrl-0 = <&pinctrl_usbotg1>;
  537. vbus-supply = <&reg_usb_otg1_vbus>;
  538. srp-disable;
  539. hnp-disable;
  540. adp-disable;
  541. over-current-active-low;
  542. dr_mode = "otg";
  543. status = "okay";
  544. };
  545. &usdhc1 {
  546. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  547. pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
  548. pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
  549. pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
  550. cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
  551. wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
  552. vmmc-supply = <&reg_sd1_vmmc>;
  553. bus-width = <4>;
  554. no-1-8-v;
  555. status = "okay";
  556. };
  557. &wdog1 {
  558. pinctrl-names = "default";
  559. pinctrl-0 = <&pinctrl_wdog1>;
  560. fsl,ext-reset-output;
  561. };