imx6ull-opos6uldev.dts 1.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR MIT
  2. //
  3. // Copyright 2019 Armadeus Systems <[email protected]>
  4. /dts-v1/;
  5. #include "imx6ull-opos6ul.dtsi"
  6. #include "imx6ul-imx6ull-opos6uldev.dtsi"
  7. / {
  8. model = "Armadeus Systems OPOS6UL SoM (i.MX6ULL) on OPOS6ULDev board";
  9. compatible = "armadeus,imx6ull-opos6uldev", "armadeus,imx6ull-opos6ul", "fsl,imx6ull";
  10. };
  11. &iomuxc_snvs {
  12. pinctrl-names = "default";
  13. pinctrl-0 = <&pinctrl_tamper_gpios>;
  14. pinctrl_tamper_gpios: tampergpiosgrp {
  15. fsl,pins = <
  16. MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0
  17. MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0
  18. MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0
  19. MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0
  20. MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0
  21. MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0
  22. MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0
  23. MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0b0b0
  24. >;
  25. };
  26. pinctrl_usbotg2_vbus: usbotg2vbusgrp {
  27. fsl,pins = <
  28. MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
  29. >;
  30. };
  31. pinctrl_w1: w1grp {
  32. fsl,pins = <
  33. MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0
  34. >;
  35. };
  36. };