imx6ul-kontron-bl-common.dtsi 8.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2017 exceet electronics GmbH
  4. * Copyright (C) 2018 Kontron Electronics GmbH
  5. * Copyright (c) 2019 Krzysztof Kozlowski <[email protected]>
  6. */
  7. #include <dt-bindings/gpio/gpio.h>
  8. / {
  9. gpio-leds {
  10. compatible = "gpio-leds";
  11. pinctrl-names = "default";
  12. pinctrl-0 = <&pinctrl_gpio_leds>;
  13. led1 {
  14. label = "debug-led1";
  15. gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
  16. default-state = "off";
  17. linux,default-trigger = "heartbeat";
  18. };
  19. led2 {
  20. label = "debug-led2";
  21. gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
  22. default-state = "off";
  23. };
  24. led3 {
  25. label = "debug-led3";
  26. gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
  27. default-state = "off";
  28. };
  29. };
  30. pwm-beeper {
  31. compatible = "pwm-beeper";
  32. pwms = <&pwm8 0 5000>;
  33. };
  34. reg_3v3: regulator-3v3 {
  35. compatible = "regulator-fixed";
  36. regulator-name = "3v3";
  37. regulator-min-microvolt = <3300000>;
  38. regulator-max-microvolt = <3300000>;
  39. };
  40. reg_5v: regulator-5v {
  41. compatible = "regulator-fixed";
  42. regulator-name = "5v";
  43. regulator-min-microvolt = <5000000>;
  44. regulator-max-microvolt = <5000000>;
  45. };
  46. reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  47. compatible = "regulator-fixed";
  48. regulator-name = "usb_otg1_vbus";
  49. regulator-min-microvolt = <5000000>;
  50. regulator-max-microvolt = <5000000>;
  51. gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
  52. enable-active-high;
  53. };
  54. reg_vref_adc: regulator-vref-adc {
  55. compatible = "regulator-fixed";
  56. regulator-name = "vref-adc";
  57. regulator-min-microvolt = <3300000>;
  58. regulator-max-microvolt = <3300000>;
  59. };
  60. };
  61. &adc1 {
  62. pinctrl-names = "default";
  63. pinctrl-0 = <&pinctrl_adc1>;
  64. vref-supply = <&reg_vref_adc>;
  65. status = "okay";
  66. };
  67. &can2 {
  68. pinctrl-names = "default";
  69. pinctrl-0 = <&pinctrl_flexcan2>;
  70. status = "okay";
  71. };
  72. &ecspi1 {
  73. cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
  74. pinctrl-names = "default";
  75. pinctrl-0 = <&pinctrl_ecspi1>;
  76. status = "okay";
  77. eeprom@0 {
  78. compatible = "anvo,anv32e61w", "atmel,at25";
  79. reg = <0>;
  80. spi-max-frequency = <20000000>;
  81. spi-cpha;
  82. spi-cpol;
  83. pagesize = <1>;
  84. size = <8192>;
  85. address-width = <16>;
  86. };
  87. };
  88. &fec1 {
  89. pinctrl-0 = <&pinctrl_enet1>;
  90. /delete-node/ mdio;
  91. };
  92. &fec2 {
  93. pinctrl-names = "default";
  94. pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
  95. phy-mode = "rmii";
  96. phy-handle = <&ethphy2>;
  97. status = "okay";
  98. mdio {
  99. #address-cells = <1>;
  100. #size-cells = <0>;
  101. ethphy1: ethernet-phy@1 {
  102. reg = <1>;
  103. micrel,led-mode = <0>;
  104. clocks = <&clks IMX6UL_CLK_ENET_REF>;
  105. clock-names = "rmii-ref";
  106. };
  107. ethphy2: ethernet-phy@2 {
  108. reg = <2>;
  109. micrel,led-mode = <0>;
  110. clocks = <&clks IMX6UL_CLK_ENET2_REF>;
  111. clock-names = "rmii-ref";
  112. };
  113. };
  114. };
  115. &i2c1 {
  116. clock-frequency = <100000>;
  117. pinctrl-names = "default";
  118. pinctrl-0 = <&pinctrl_i2c1>;
  119. status = "okay";
  120. };
  121. &i2c4 {
  122. clock-frequency = <100000>;
  123. pinctrl-names = "default";
  124. pinctrl-0 = <&pinctrl_i2c4>;
  125. status = "okay";
  126. rtc@32 {
  127. compatible = "epson,rx8900";
  128. reg = <0x32>;
  129. };
  130. };
  131. &pwm8 {
  132. #pwm-cells = <2>;
  133. pinctrl-names = "default";
  134. pinctrl-0 = <&pinctrl_pwm8>;
  135. status = "okay";
  136. };
  137. &uart1 {
  138. pinctrl-names = "default";
  139. pinctrl-0 = <&pinctrl_uart1>;
  140. status = "okay";
  141. };
  142. &uart2 {
  143. pinctrl-names = "default";
  144. pinctrl-0 = <&pinctrl_uart2>;
  145. linux,rs485-enabled-at-boot-time;
  146. rs485-rx-during-tx;
  147. rs485-rts-active-low;
  148. uart-has-rtscts;
  149. status = "okay";
  150. };
  151. &uart3 {
  152. pinctrl-names = "default";
  153. pinctrl-0 = <&pinctrl_uart3>;
  154. uart-has-rtscts;
  155. status = "okay";
  156. };
  157. &uart4 {
  158. pinctrl-names = "default";
  159. pinctrl-0 = <&pinctrl_uart4>;
  160. status = "okay";
  161. };
  162. &usbotg1 {
  163. pinctrl-names = "default";
  164. pinctrl-0 = <&pinctrl_usbotg1>;
  165. dr_mode = "otg";
  166. srp-disable;
  167. hnp-disable;
  168. adp-disable;
  169. over-current-active-low;
  170. vbus-supply = <&reg_usb_otg1_vbus>;
  171. status = "okay";
  172. };
  173. &usbotg2 {
  174. dr_mode = "host";
  175. disable-over-current;
  176. vbus-supply = <&reg_5v>;
  177. status = "okay";
  178. };
  179. &usdhc1 {
  180. pinctrl-names = "default";
  181. pinctrl-0 = <&pinctrl_usdhc1>;
  182. cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
  183. keep-power-in-suspend;
  184. wakeup-source;
  185. vmmc-supply = <&reg_3v3>;
  186. voltage-ranges = <3300 3300>;
  187. no-1-8-v;
  188. status = "okay";
  189. };
  190. &usdhc2 {
  191. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  192. pinctrl-0 = <&pinctrl_usdhc2>;
  193. pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
  194. pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
  195. non-removable;
  196. keep-power-in-suspend;
  197. wakeup-source;
  198. vmmc-supply = <&reg_3v3>;
  199. voltage-ranges = <3300 3300>;
  200. no-1-8-v;
  201. status = "okay";
  202. };
  203. &iomuxc {
  204. pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
  205. pinctrl_adc1: adc1grp {
  206. fsl,pins = <
  207. MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
  208. MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
  209. MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
  210. >;
  211. };
  212. pinctrl_ecspi1: ecspi1grp {
  213. fsl,pins = <
  214. MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
  215. MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
  216. MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
  217. MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
  218. >;
  219. };
  220. pinctrl_enet2: enet2grp {
  221. fsl,pins = <
  222. MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
  223. MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
  224. MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
  225. MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
  226. MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
  227. MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
  228. MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
  229. MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
  230. >;
  231. };
  232. pinctrl_enet2_mdio: enet2mdiogrp {
  233. fsl,pins = <
  234. MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
  235. MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
  236. >;
  237. };
  238. pinctrl_flexcan2: flexcan2grp{
  239. fsl,pins = <
  240. MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
  241. MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
  242. >;
  243. };
  244. pinctrl_gpio: gpiogrp {
  245. fsl,pins = <
  246. MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
  247. MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
  248. MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
  249. MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
  250. >;
  251. };
  252. pinctrl_gpio_leds: gpioledsgrp {
  253. fsl,pins = <
  254. MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
  255. MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
  256. MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
  257. >;
  258. };
  259. pinctrl_i2c1: i2c1grp {
  260. fsl,pins = <
  261. MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
  262. MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
  263. >;
  264. };
  265. pinctrl_i2c4: i2c4grp {
  266. fsl,pins = <
  267. MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
  268. MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
  269. >;
  270. };
  271. pinctrl_pwm8: pwm8grp {
  272. fsl,pins = <
  273. MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
  274. >;
  275. };
  276. pinctrl_uart1: uart1grp {
  277. fsl,pins = <
  278. MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
  279. MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
  280. >;
  281. };
  282. pinctrl_uart2: uart2grp {
  283. fsl,pins = <
  284. MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
  285. MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
  286. MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
  287. /*
  288. * mux unused RTS to make sure it doesn't cause
  289. * any interrupts when it is undefined
  290. */
  291. MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
  292. >;
  293. };
  294. pinctrl_uart3: uart3grp {
  295. fsl,pins = <
  296. MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
  297. MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
  298. MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
  299. MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
  300. >;
  301. };
  302. pinctrl_uart4: uart4grp {
  303. fsl,pins = <
  304. MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
  305. MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
  306. >;
  307. };
  308. pinctrl_usbotg1: usbotg1 {
  309. fsl,pins = <
  310. MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
  311. >;
  312. };
  313. pinctrl_usdhc1: usdhc1grp {
  314. fsl,pins = <
  315. MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
  316. MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
  317. MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
  318. MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
  319. MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
  320. MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
  321. MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
  322. >;
  323. };
  324. pinctrl_usdhc2: usdhc2grp {
  325. fsl,pins = <
  326. MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
  327. MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
  328. MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
  329. MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
  330. MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
  331. MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
  332. >;
  333. };
  334. pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
  335. fsl,pins = <
  336. MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
  337. MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
  338. MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
  339. MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
  340. MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
  341. MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
  342. >;
  343. };
  344. pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
  345. fsl,pins = <
  346. MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
  347. MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
  348. MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
  349. MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
  350. MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
  351. MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
  352. >;
  353. };
  354. };