imx6ul-14x14-evk.dtsi 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (C) 2015 Freescale Semiconductor, Inc.
  4. / {
  5. chosen {
  6. stdout-path = &uart1;
  7. };
  8. memory@80000000 {
  9. device_type = "memory";
  10. reg = <0x80000000 0x20000000>;
  11. };
  12. backlight_display: backlight-display {
  13. compatible = "pwm-backlight";
  14. pwms = <&pwm1 0 5000000>;
  15. brightness-levels = <0 4 8 16 32 64 128 255>;
  16. default-brightness-level = <6>;
  17. status = "okay";
  18. };
  19. reg_sd1_vmmc: regulator-sd1-vmmc {
  20. compatible = "regulator-fixed";
  21. regulator-name = "VSD_3V3";
  22. regulator-min-microvolt = <3300000>;
  23. regulator-max-microvolt = <3300000>;
  24. gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  25. enable-active-high;
  26. };
  27. reg_peri_3v3: regulator-peri-3v3 {
  28. compatible = "regulator-fixed";
  29. pinctrl-names = "default";
  30. pinctrl-0 = <&pinctrl_peri_3v3>;
  31. regulator-name = "VPERI_3V3";
  32. regulator-min-microvolt = <3300000>;
  33. regulator-max-microvolt = <3300000>;
  34. gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
  35. /*
  36. * If you want to want to make this dynamic please
  37. * check schematics and test all affected peripherals:
  38. *
  39. * - sensors
  40. * - ethernet phy
  41. * - can
  42. * - bluetooth
  43. * - wm8960 audio codec
  44. * - ov5640 camera
  45. */
  46. regulator-always-on;
  47. };
  48. reg_can_3v3: regulator-can-3v3 {
  49. compatible = "regulator-fixed";
  50. regulator-name = "can-3v3";
  51. regulator-min-microvolt = <3300000>;
  52. regulator-max-microvolt = <3300000>;
  53. gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
  54. };
  55. sound-wm8960 {
  56. compatible = "fsl,imx-audio-wm8960";
  57. model = "wm8960-audio";
  58. audio-cpu = <&sai2>;
  59. audio-codec = <&codec>;
  60. audio-asrc = <&asrc>;
  61. hp-det-gpio = <&gpio5 4 0>;
  62. audio-routing =
  63. "Headphone Jack", "HP_L",
  64. "Headphone Jack", "HP_R",
  65. "Ext Spk", "SPK_LP",
  66. "Ext Spk", "SPK_LN",
  67. "Ext Spk", "SPK_RP",
  68. "Ext Spk", "SPK_RN",
  69. "LINPUT2", "Mic Jack",
  70. "LINPUT3", "Mic Jack",
  71. "RINPUT1", "AMIC",
  72. "RINPUT2", "AMIC",
  73. "Mic Jack", "MICB",
  74. "AMIC", "MICB";
  75. };
  76. spi-4 {
  77. compatible = "spi-gpio";
  78. pinctrl-names = "default";
  79. pinctrl-0 = <&pinctrl_spi4>;
  80. status = "okay";
  81. gpio-sck = <&gpio5 11 0>;
  82. gpio-mosi = <&gpio5 10 0>;
  83. cs-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
  84. num-chipselects = <1>;
  85. #address-cells = <1>;
  86. #size-cells = <0>;
  87. gpio_spi: gpio@0 {
  88. compatible = "fairchild,74hc595";
  89. gpio-controller;
  90. #gpio-cells = <2>;
  91. reg = <0>;
  92. registers-number = <1>;
  93. spi-max-frequency = <100000>;
  94. enable-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
  95. };
  96. };
  97. panel {
  98. compatible = "innolux,at043tn24";
  99. backlight = <&backlight_display>;
  100. port {
  101. panel_in: endpoint {
  102. remote-endpoint = <&display_out>;
  103. };
  104. };
  105. };
  106. };
  107. &clks {
  108. assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
  109. assigned-clock-rates = <786432000>;
  110. };
  111. &i2c2 {
  112. clock-frequency = <100000>;
  113. pinctrl-names = "default";
  114. pinctrl-0 = <&pinctrl_i2c2>;
  115. status = "okay";
  116. codec: wm8960@1a {
  117. #sound-dai-cells = <0>;
  118. compatible = "wlf,wm8960";
  119. reg = <0x1a>;
  120. wlf,shared-lrclk;
  121. wlf,hp-cfg = <3 2 3>;
  122. wlf,gpio-cfg = <1 3>;
  123. clocks = <&clks IMX6UL_CLK_SAI2>;
  124. clock-names = "mclk";
  125. };
  126. camera@3c {
  127. compatible = "ovti,ov5640";
  128. reg = <0x3c>;
  129. pinctrl-names = "default";
  130. pinctrl-0 = <&pinctrl_camera_clock>;
  131. clocks = <&clks IMX6UL_CLK_CSI>;
  132. clock-names = "xclk";
  133. powerdown-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>;
  134. reset-gpios = <&gpio_spi 5 GPIO_ACTIVE_LOW>;
  135. port {
  136. ov5640_to_parallel: endpoint {
  137. remote-endpoint = <&parallel_from_ov5640>;
  138. bus-width = <8>;
  139. data-shift = <2>; /* lines 9:2 are used */
  140. hsync-active = <0>;
  141. vsync-active = <0>;
  142. pclk-sample = <1>;
  143. };
  144. };
  145. };
  146. };
  147. &csi {
  148. pinctrl-names = "default";
  149. pinctrl-0 = <&pinctrl_csi1>;
  150. status = "okay";
  151. port {
  152. parallel_from_ov5640: endpoint {
  153. remote-endpoint = <&ov5640_to_parallel>;
  154. bus-type = <5>; /* Parallel bus */
  155. };
  156. };
  157. };
  158. &fec1 {
  159. pinctrl-names = "default";
  160. pinctrl-0 = <&pinctrl_enet1>;
  161. phy-mode = "rmii";
  162. phy-handle = <&ethphy0>;
  163. phy-supply = <&reg_peri_3v3>;
  164. status = "okay";
  165. };
  166. &fec2 {
  167. pinctrl-names = "default";
  168. pinctrl-0 = <&pinctrl_enet2>;
  169. phy-mode = "rmii";
  170. phy-handle = <&ethphy1>;
  171. phy-supply = <&reg_peri_3v3>;
  172. status = "okay";
  173. mdio {
  174. #address-cells = <1>;
  175. #size-cells = <0>;
  176. ethphy0: ethernet-phy@2 {
  177. compatible = "ethernet-phy-id0022.1560";
  178. reg = <2>;
  179. micrel,led-mode = <1>;
  180. clocks = <&clks IMX6UL_CLK_ENET_REF>;
  181. clock-names = "rmii-ref";
  182. };
  183. ethphy1: ethernet-phy@1 {
  184. compatible = "ethernet-phy-id0022.1560";
  185. reg = <1>;
  186. micrel,led-mode = <1>;
  187. clocks = <&clks IMX6UL_CLK_ENET2_REF>;
  188. clock-names = "rmii-ref";
  189. };
  190. };
  191. };
  192. &can1 {
  193. pinctrl-names = "default";
  194. pinctrl-0 = <&pinctrl_flexcan1>;
  195. xceiver-supply = <&reg_can_3v3>;
  196. status = "okay";
  197. };
  198. &can2 {
  199. pinctrl-names = "default";
  200. pinctrl-0 = <&pinctrl_flexcan2>;
  201. xceiver-supply = <&reg_can_3v3>;
  202. status = "okay";
  203. };
  204. &gpio_spi {
  205. eth0-phy-hog {
  206. gpio-hog;
  207. gpios = <1 GPIO_ACTIVE_HIGH>;
  208. output-high;
  209. line-name = "eth0-phy";
  210. };
  211. eth1-phy-hog {
  212. gpio-hog;
  213. gpios = <2 GPIO_ACTIVE_HIGH>;
  214. output-high;
  215. line-name = "eth1-phy";
  216. };
  217. };
  218. &i2c1 {
  219. clock-frequency = <100000>;
  220. pinctrl-names = "default";
  221. pinctrl-0 = <&pinctrl_i2c1>;
  222. status = "okay";
  223. magnetometer@e {
  224. compatible = "fsl,mag3110";
  225. reg = <0x0e>;
  226. vdd-supply = <&reg_peri_3v3>;
  227. vddio-supply = <&reg_peri_3v3>;
  228. };
  229. };
  230. &lcdif {
  231. assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
  232. assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
  233. pinctrl-names = "default";
  234. pinctrl-0 = <&pinctrl_lcdif_dat
  235. &pinctrl_lcdif_ctrl>;
  236. status = "okay";
  237. port {
  238. display_out: endpoint {
  239. remote-endpoint = <&panel_in>;
  240. };
  241. };
  242. };
  243. &pwm1 {
  244. #pwm-cells = <2>;
  245. pinctrl-names = "default";
  246. pinctrl-0 = <&pinctrl_pwm1>;
  247. status = "okay";
  248. };
  249. &qspi {
  250. pinctrl-names = "default";
  251. pinctrl-0 = <&pinctrl_qspi>;
  252. status = "okay";
  253. flash0: flash@0 {
  254. #address-cells = <1>;
  255. #size-cells = <1>;
  256. compatible = "micron,n25q256a", "jedec,spi-nor";
  257. spi-max-frequency = <29000000>;
  258. spi-rx-bus-width = <4>;
  259. spi-tx-bus-width = <1>;
  260. reg = <0>;
  261. };
  262. };
  263. &sai2 {
  264. pinctrl-names = "default";
  265. pinctrl-0 = <&pinctrl_sai2>;
  266. assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
  267. <&clks IMX6UL_CLK_SAI2>;
  268. assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
  269. assigned-clock-rates = <0>, <12288000>;
  270. fsl,sai-mclk-direction-output;
  271. status = "okay";
  272. };
  273. &snvs_poweroff {
  274. status = "okay";
  275. };
  276. &snvs_pwrkey {
  277. status = "okay";
  278. };
  279. &tsc {
  280. pinctrl-names = "default";
  281. pinctrl-0 = <&pinctrl_tsc>;
  282. xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
  283. measure-delay-time = <0xffff>;
  284. pre-charge-time = <0xfff>;
  285. status = "okay";
  286. };
  287. &uart1 {
  288. pinctrl-names = "default";
  289. pinctrl-0 = <&pinctrl_uart1>;
  290. status = "okay";
  291. };
  292. &uart2 {
  293. pinctrl-names = "default";
  294. pinctrl-0 = <&pinctrl_uart2>;
  295. uart-has-rtscts;
  296. status = "okay";
  297. };
  298. &usbotg1 {
  299. dr_mode = "otg";
  300. pinctrl-names = "default";
  301. pinctrl-0 = <&pinctrl_usb_otg1>;
  302. status = "okay";
  303. };
  304. &usbotg2 {
  305. dr_mode = "host";
  306. disable-over-current;
  307. status = "okay";
  308. };
  309. &usbphy1 {
  310. fsl,tx-d-cal = <106>;
  311. };
  312. &usbphy2 {
  313. fsl,tx-d-cal = <106>;
  314. };
  315. &usdhc1 {
  316. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  317. pinctrl-0 = <&pinctrl_usdhc1>;
  318. pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
  319. pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
  320. cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
  321. keep-power-in-suspend;
  322. wakeup-source;
  323. vmmc-supply = <&reg_sd1_vmmc>;
  324. status = "okay";
  325. };
  326. &usdhc2 {
  327. pinctrl-names = "default";
  328. pinctrl-0 = <&pinctrl_usdhc2>;
  329. no-1-8-v;
  330. broken-cd;
  331. keep-power-in-suspend;
  332. wakeup-source;
  333. status = "okay";
  334. };
  335. &wdog1 {
  336. pinctrl-names = "default";
  337. pinctrl-0 = <&pinctrl_wdog>;
  338. fsl,ext-reset-output;
  339. };
  340. &iomuxc {
  341. pinctrl-names = "default";
  342. pinctrl_camera_clock: cameraclockgrp {
  343. fsl,pins = <
  344. MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
  345. >;
  346. };
  347. pinctrl_csi1: csi1grp {
  348. fsl,pins = <
  349. MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
  350. MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
  351. MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
  352. MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
  353. MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
  354. MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
  355. MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
  356. MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
  357. MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
  358. MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
  359. MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
  360. >;
  361. };
  362. pinctrl_enet1: enet1grp {
  363. fsl,pins = <
  364. MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
  365. MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
  366. MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
  367. MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
  368. MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
  369. MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
  370. MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
  371. MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
  372. >;
  373. };
  374. pinctrl_enet2: enet2grp {
  375. fsl,pins = <
  376. MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
  377. MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
  378. MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
  379. MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
  380. MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
  381. MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
  382. MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
  383. MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
  384. MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
  385. MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
  386. >;
  387. };
  388. pinctrl_flexcan1: flexcan1grp{
  389. fsl,pins = <
  390. MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
  391. MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
  392. >;
  393. };
  394. pinctrl_flexcan2: flexcan2grp{
  395. fsl,pins = <
  396. MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
  397. MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
  398. >;
  399. };
  400. pinctrl_i2c1: i2c1grp {
  401. fsl,pins = <
  402. MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
  403. MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
  404. >;
  405. };
  406. pinctrl_i2c2: i2c2grp {
  407. fsl,pins = <
  408. MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
  409. MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
  410. >;
  411. };
  412. pinctrl_lcdif_dat: lcdifdatgrp {
  413. fsl,pins = <
  414. MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
  415. MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
  416. MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
  417. MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
  418. MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
  419. MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
  420. MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
  421. MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
  422. MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
  423. MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
  424. MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
  425. MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
  426. MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
  427. MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
  428. MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
  429. MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
  430. MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
  431. MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
  432. MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
  433. MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
  434. MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
  435. MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
  436. MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
  437. MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
  438. >;
  439. };
  440. pinctrl_lcdif_ctrl: lcdifctrlgrp {
  441. fsl,pins = <
  442. MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
  443. MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
  444. MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
  445. MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
  446. /* used for lcd reset */
  447. MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
  448. >;
  449. };
  450. pinctrl_qspi: qspigrp {
  451. fsl,pins = <
  452. MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
  453. MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
  454. MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
  455. MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
  456. MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
  457. MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
  458. >;
  459. };
  460. pinctrl_sai2: sai2grp {
  461. fsl,pins = <
  462. MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
  463. MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
  464. MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
  465. MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
  466. MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
  467. MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
  468. >;
  469. };
  470. pinctrl_peri_3v3: peri3v3grp {
  471. fsl,pins = <
  472. MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
  473. >;
  474. };
  475. pinctrl_pwm1: pwm1grp {
  476. fsl,pins = <
  477. MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
  478. >;
  479. };
  480. pinctrl_sim2: sim2grp {
  481. fsl,pins = <
  482. MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808
  483. MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31
  484. MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808
  485. MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808
  486. MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809
  487. MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
  488. >;
  489. };
  490. pinctrl_spi4: spi4grp {
  491. fsl,pins = <
  492. MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
  493. MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1
  494. MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1
  495. MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000
  496. >;
  497. };
  498. pinctrl_tsc: tscgrp {
  499. fsl,pins = <
  500. MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
  501. MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
  502. MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
  503. MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
  504. >;
  505. };
  506. pinctrl_uart1: uart1grp {
  507. fsl,pins = <
  508. MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
  509. MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
  510. >;
  511. };
  512. pinctrl_uart2: uart2grp {
  513. fsl,pins = <
  514. MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
  515. MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
  516. MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
  517. MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
  518. >;
  519. };
  520. pinctrl_usb_otg1: usbotg1grp {
  521. fsl,pins = <
  522. MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
  523. >;
  524. };
  525. pinctrl_usdhc1: usdhc1grp {
  526. fsl,pins = <
  527. MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
  528. MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
  529. MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
  530. MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
  531. MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
  532. MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
  533. MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
  534. MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
  535. MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
  536. >;
  537. };
  538. pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
  539. fsl,pins = <
  540. MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
  541. MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
  542. MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
  543. MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
  544. MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
  545. MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
  546. >;
  547. };
  548. pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
  549. fsl,pins = <
  550. MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
  551. MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
  552. MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
  553. MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
  554. MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
  555. MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
  556. >;
  557. };
  558. pinctrl_usdhc2: usdhc2grp {
  559. fsl,pins = <
  560. MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
  561. MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
  562. MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
  563. MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
  564. MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
  565. MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
  566. >;
  567. };
  568. pinctrl_wdog: wdoggrp {
  569. fsl,pins = <
  570. MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
  571. >;
  572. };
  573. };