imx6sx-sdb.dtsi 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (C) 2014 Freescale Semiconductor, Inc.
  4. /dts-v1/;
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/input.h>
  7. #include "imx6sx.dtsi"
  8. / {
  9. model = "Freescale i.MX6 SoloX SDB Board";
  10. compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
  11. chosen {
  12. stdout-path = &uart1;
  13. };
  14. memory@80000000 {
  15. device_type = "memory";
  16. reg = <0x80000000 0x40000000>;
  17. };
  18. backlight_display: backlight-display {
  19. compatible = "pwm-backlight";
  20. pwms = <&pwm3 0 5000000>;
  21. brightness-levels = <0 4 8 16 32 64 128 255>;
  22. default-brightness-level = <6>;
  23. };
  24. gpio-keys {
  25. compatible = "gpio-keys";
  26. pinctrl-names = "default";
  27. pinctrl-0 = <&pinctrl_gpio_keys>;
  28. volume-up {
  29. label = "Volume Up";
  30. gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
  31. linux,code = <KEY_VOLUMEUP>;
  32. wakeup-source;
  33. };
  34. volume-down {
  35. label = "Volume Down";
  36. gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
  37. linux,code = <KEY_VOLUMEDOWN>;
  38. wakeup-source;
  39. };
  40. };
  41. vcc_sd3: regulator-vcc-sd3 {
  42. compatible = "regulator-fixed";
  43. pinctrl-names = "default";
  44. pinctrl-0 = <&pinctrl_vcc_sd3>;
  45. regulator-name = "VCC_SD3";
  46. regulator-min-microvolt = <3000000>;
  47. regulator-max-microvolt = <3000000>;
  48. gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
  49. enable-active-high;
  50. };
  51. reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  52. compatible = "regulator-fixed";
  53. pinctrl-names = "default";
  54. pinctrl-0 = <&pinctrl_usb_otg1>;
  55. regulator-name = "usb_otg1_vbus";
  56. regulator-min-microvolt = <5000000>;
  57. regulator-max-microvolt = <5000000>;
  58. gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  59. enable-active-high;
  60. };
  61. reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
  62. compatible = "regulator-fixed";
  63. pinctrl-names = "default";
  64. pinctrl-0 = <&pinctrl_usb_otg2>;
  65. regulator-name = "usb_otg2_vbus";
  66. regulator-min-microvolt = <5000000>;
  67. regulator-max-microvolt = <5000000>;
  68. gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  69. enable-active-high;
  70. };
  71. reg_psu_5v: regulator-psu-5v {
  72. compatible = "regulator-fixed";
  73. regulator-name = "PSU-5V0";
  74. regulator-min-microvolt = <5000000>;
  75. regulator-max-microvolt = <5000000>;
  76. };
  77. reg_lcd_3v3: regulator-lcd-3v3 {
  78. compatible = "regulator-fixed";
  79. regulator-name = "lcd-3v3";
  80. gpio = <&gpio3 27 0>;
  81. enable-active-high;
  82. };
  83. reg_peri_3v3: regulator-peri-3v3 {
  84. compatible = "regulator-fixed";
  85. pinctrl-names = "default";
  86. pinctrl-0 = <&pinctrl_peri_3v3>;
  87. regulator-name = "peri_3v3";
  88. regulator-min-microvolt = <3300000>;
  89. regulator-max-microvolt = <3300000>;
  90. gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
  91. enable-active-high;
  92. regulator-always-on;
  93. };
  94. reg_enet_3v3: regulator-enet-3v3 {
  95. compatible = "regulator-fixed";
  96. pinctrl-names = "default";
  97. pinctrl-0 = <&pinctrl_enet_3v3>;
  98. regulator-name = "enet_3v3";
  99. regulator-min-microvolt = <3300000>;
  100. regulator-max-microvolt = <3300000>;
  101. gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
  102. regulator-boot-on;
  103. regulator-always-on;
  104. };
  105. reg_pcie_gpio: regulator-pcie-gpio {
  106. compatible = "regulator-fixed";
  107. pinctrl-names = "default";
  108. pinctrl-0 = <&pinctrl_pcie_reg>;
  109. regulator-name = "MPCIE_3V3";
  110. regulator-min-microvolt = <3300000>;
  111. regulator-max-microvolt = <3300000>;
  112. gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>;
  113. enable-active-high;
  114. };
  115. reg_lcd_5v: regulator-lcd-5v {
  116. compatible = "regulator-fixed";
  117. regulator-name = "lcd-5v0";
  118. regulator-min-microvolt = <5000000>;
  119. regulator-max-microvolt = <5000000>;
  120. };
  121. reg_can_en: regulator-can-en {
  122. compatible = "regulator-fixed";
  123. regulator-name = "can-en";
  124. regulator-min-microvolt = <3300000>;
  125. regulator-max-microvolt = <3300000>;
  126. };
  127. reg_can_stby: regulator-can-stby {
  128. compatible = "regulator-fixed";
  129. regulator-name = "can-stby";
  130. regulator-min-microvolt = <3300000>;
  131. regulator-max-microvolt = <3300000>;
  132. };
  133. sound {
  134. compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
  135. pinctrl-names = "default";
  136. pinctrl-0 = <&pinctrl_hp>;
  137. model = "wm8962-audio";
  138. ssi-controller = <&ssi2>;
  139. audio-codec = <&codec>;
  140. audio-routing =
  141. "Headphone Jack", "HPOUTL",
  142. "Headphone Jack", "HPOUTR",
  143. "Ext Spk", "SPKOUTL",
  144. "Ext Spk", "SPKOUTR",
  145. "AMIC", "MICBIAS",
  146. "IN3R", "AMIC";
  147. mux-int-port = <2>;
  148. mux-ext-port = <6>;
  149. hp-det-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>;
  150. };
  151. panel {
  152. compatible = "sii,43wvf1g";
  153. backlight = <&backlight_display>;
  154. dvdd-supply = <&reg_lcd_3v3>;
  155. avdd-supply = <&reg_lcd_5v>;
  156. port {
  157. panel_in: endpoint {
  158. remote-endpoint = <&display_out>;
  159. };
  160. };
  161. };
  162. sound-spdif {
  163. compatible = "fsl,imx-audio-spdif",
  164. "fsl,imx6sx-sdb-spdif";
  165. model = "imx-spdif";
  166. spdif-controller = <&spdif>;
  167. spdif-out;
  168. };
  169. };
  170. &audmux {
  171. pinctrl-names = "default";
  172. pinctrl-0 = <&pinctrl_audmux>;
  173. status = "okay";
  174. };
  175. &fec1 {
  176. pinctrl-names = "default";
  177. pinctrl-0 = <&pinctrl_enet1>;
  178. phy-supply = <&reg_enet_3v3>;
  179. phy-mode = "rgmii-id";
  180. phy-handle = <&ethphy1>;
  181. phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
  182. fsl,magic-packet;
  183. status = "okay";
  184. mdio {
  185. #address-cells = <1>;
  186. #size-cells = <0>;
  187. ethphy1: ethernet-phy@1 {
  188. reg = <1>;
  189. };
  190. ethphy2: ethernet-phy@2 {
  191. reg = <2>;
  192. };
  193. };
  194. };
  195. &fec2 {
  196. pinctrl-names = "default";
  197. pinctrl-0 = <&pinctrl_enet2>;
  198. phy-mode = "rgmii-id";
  199. phy-handle = <&ethphy2>;
  200. fsl,magic-packet;
  201. status = "okay";
  202. };
  203. &flexcan1 {
  204. pinctrl-names = "default";
  205. pinctrl-0 = <&pinctrl_flexcan1>;
  206. xceiver-supply = <&reg_can_stby>;
  207. status = "okay";
  208. };
  209. &flexcan2 {
  210. pinctrl-names = "default";
  211. pinctrl-0 = <&pinctrl_flexcan2>;
  212. xceiver-supply = <&reg_can_stby>;
  213. status = "okay";
  214. };
  215. &i2c3 {
  216. clock-frequency = <100000>;
  217. pinctrl-names = "default";
  218. pinctrl-0 = <&pinctrl_i2c3>;
  219. status = "okay";
  220. };
  221. &i2c4 {
  222. clock-frequency = <100000>;
  223. pinctrl-names = "default";
  224. pinctrl-0 = <&pinctrl_i2c4>;
  225. status = "okay";
  226. codec: wm8962@1a {
  227. compatible = "wlf,wm8962";
  228. reg = <0x1a>;
  229. clocks = <&clks IMX6SX_CLK_AUDIO>;
  230. DCVDD-supply = <&vgen4_reg>;
  231. DBVDD-supply = <&vgen4_reg>;
  232. AVDD-supply = <&vgen4_reg>;
  233. CPVDD-supply = <&vgen4_reg>;
  234. MICVDD-supply = <&vgen3_reg>;
  235. PLLVDD-supply = <&vgen4_reg>;
  236. SPKVDD1-supply = <&reg_psu_5v>;
  237. SPKVDD2-supply = <&reg_psu_5v>;
  238. };
  239. };
  240. &pcie {
  241. pinctrl-names = "default";
  242. pinctrl-0 = <&pinctrl_pcie>;
  243. reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>;
  244. vpcie-supply = <&reg_pcie_gpio>;
  245. status = "okay";
  246. };
  247. &lcdif1 {
  248. pinctrl-names = "default";
  249. pinctrl-0 = <&pinctrl_lcd>;
  250. status = "okay";
  251. port {
  252. display_out: endpoint {
  253. remote-endpoint = <&panel_in>;
  254. };
  255. };
  256. };
  257. &pwm3 {
  258. #pwm-cells = <2>;
  259. pinctrl-names = "default";
  260. pinctrl-0 = <&pinctrl_pwm3>;
  261. status = "okay";
  262. };
  263. &snvs_poweroff {
  264. status = "okay";
  265. };
  266. &sai1 {
  267. pinctrl-names = "default";
  268. pinctrl-0 = <&pinctrl_sai1>;
  269. status = "disabled";
  270. };
  271. &spdif {
  272. pinctrl-names = "default";
  273. pinctrl-0 = <&pinctrl_spdif>;
  274. assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>;
  275. assigned-clock-rates = <24576000>;
  276. status = "okay";
  277. };
  278. &ssi2 {
  279. status = "okay";
  280. };
  281. &uart1 {
  282. pinctrl-names = "default";
  283. pinctrl-0 = <&pinctrl_uart1>;
  284. status = "okay";
  285. };
  286. &uart5 { /* for bluetooth */
  287. pinctrl-names = "default";
  288. pinctrl-0 = <&pinctrl_uart5>;
  289. uart-has-rtscts;
  290. status = "okay";
  291. };
  292. &usbotg1 {
  293. vbus-supply = <&reg_usb_otg1_vbus>;
  294. pinctrl-names = "default";
  295. pinctrl-0 = <&pinctrl_usb_otg1_id>;
  296. status = "okay";
  297. };
  298. &usbotg2 {
  299. vbus-supply = <&reg_usb_otg2_vbus>;
  300. dr_mode = "host";
  301. status = "okay";
  302. };
  303. &usbphy1 {
  304. fsl,tx-d-cal = <106>;
  305. };
  306. &usbphy2 {
  307. fsl,tx-d-cal = <106>;
  308. };
  309. &usdhc2 {
  310. pinctrl-names = "default";
  311. pinctrl-0 = <&pinctrl_usdhc2>;
  312. non-removable;
  313. no-1-8-v;
  314. keep-power-in-suspend;
  315. wakeup-source;
  316. status = "okay";
  317. };
  318. &usdhc3 {
  319. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  320. pinctrl-0 = <&pinctrl_usdhc3>;
  321. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  322. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  323. bus-width = <8>;
  324. cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
  325. wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
  326. keep-power-in-suspend;
  327. wakeup-source;
  328. vmmc-supply = <&vcc_sd3>;
  329. status = "okay";
  330. };
  331. &usdhc4 {
  332. pinctrl-names = "default";
  333. pinctrl-0 = <&pinctrl_usdhc4>;
  334. cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>;
  335. wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
  336. status = "okay";
  337. };
  338. &wdog1 {
  339. pinctrl-names = "default";
  340. pinctrl-0 = <&pinctrl_wdog>;
  341. fsl,ext-reset-output;
  342. };
  343. &iomuxc {
  344. imx6x-sdb {
  345. pinctrl_audmux: audmuxgrp {
  346. fsl,pins = <
  347. MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
  348. MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0
  349. MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0
  350. MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
  351. MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
  352. >;
  353. };
  354. pinctrl_enet1: enet1grp {
  355. fsl,pins = <
  356. MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
  357. MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
  358. MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
  359. MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
  360. MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
  361. MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
  362. MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
  363. MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
  364. MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
  365. MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
  366. MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
  367. MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
  368. MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
  369. MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
  370. MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
  371. /* phy reset */
  372. MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x10b0
  373. >;
  374. };
  375. pinctrl_enet_3v3: enet3v3grp {
  376. fsl,pins = <
  377. MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000
  378. >;
  379. };
  380. pinctrl_enet2: enet2grp {
  381. fsl,pins = <
  382. MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
  383. MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
  384. MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
  385. MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
  386. MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
  387. MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
  388. MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
  389. MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
  390. MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
  391. MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
  392. MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
  393. MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
  394. >;
  395. };
  396. pinctrl_flexcan1: flexcan1grp {
  397. fsl,pins = <
  398. MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020
  399. MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020
  400. >;
  401. };
  402. pinctrl_flexcan2: flexcan2grp {
  403. fsl,pins = <
  404. MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
  405. MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020
  406. >;
  407. };
  408. pinctrl_gpio_keys: gpio_keysgrp {
  409. fsl,pins = <
  410. MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
  411. MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
  412. >;
  413. };
  414. pinctrl_hp: hpgrp {
  415. fsl,pins = <
  416. MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059
  417. >;
  418. };
  419. pinctrl_i2c1: i2c1grp {
  420. fsl,pins = <
  421. MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
  422. MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
  423. >;
  424. };
  425. pinctrl_i2c3: i2c3grp {
  426. fsl,pins = <
  427. MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
  428. MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
  429. >;
  430. };
  431. pinctrl_i2c4: i2c4grp {
  432. fsl,pins = <
  433. MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
  434. MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
  435. >;
  436. };
  437. pinctrl_lcd: lcdgrp {
  438. fsl,pins = <
  439. MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
  440. MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
  441. MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
  442. MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
  443. MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
  444. MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
  445. MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
  446. MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
  447. MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
  448. MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
  449. MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
  450. MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
  451. MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
  452. MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
  453. MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
  454. MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
  455. MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
  456. MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
  457. MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
  458. MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
  459. MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
  460. MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
  461. MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
  462. MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
  463. MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
  464. MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
  465. MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
  466. MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
  467. MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
  468. >;
  469. };
  470. pinctrl_mqs: mqsgrp {
  471. fsl,pins = <
  472. MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0
  473. MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0
  474. >;
  475. };
  476. pinctrl_pcie: pciegrp {
  477. fsl,pins = <
  478. MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
  479. >;
  480. };
  481. pinctrl_pcie_reg: pciereggrp {
  482. fsl,pins = <
  483. MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0
  484. >;
  485. };
  486. pinctrl_peri_3v3: peri3v3grp {
  487. fsl,pins = <
  488. MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
  489. >;
  490. };
  491. pinctrl_pwm3: pwm3grp-1 {
  492. fsl,pins = <
  493. MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
  494. >;
  495. };
  496. pinctrl_qspi2: qspi2grp {
  497. fsl,pins = <
  498. MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
  499. MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
  500. MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
  501. MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
  502. MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
  503. MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
  504. MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
  505. MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
  506. MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
  507. MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
  508. MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
  509. MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
  510. >;
  511. };
  512. pinctrl_vcc_sd3: vccsd3grp {
  513. fsl,pins = <
  514. MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
  515. >;
  516. };
  517. pinctrl_sai1: sai1grp {
  518. fsl,pins = <
  519. MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0
  520. MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0
  521. MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0
  522. MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0
  523. MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
  524. >;
  525. };
  526. pinctrl_spdif: spdifgrp {
  527. fsl,pins = <
  528. MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0
  529. >;
  530. };
  531. pinctrl_uart1: uart1grp {
  532. fsl,pins = <
  533. MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
  534. MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
  535. >;
  536. };
  537. pinctrl_uart5: uart5grp {
  538. fsl,pins = <
  539. MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1
  540. MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1
  541. MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x1b0b1
  542. MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x1b0b1
  543. >;
  544. };
  545. pinctrl_usb_otg1: usbotg1grp {
  546. fsl,pins = <
  547. MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
  548. >;
  549. };
  550. pinctrl_usb_otg1_id: usbotg1idgrp {
  551. fsl,pins = <
  552. MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
  553. >;
  554. };
  555. pinctrl_usb_otg2: usbot2ggrp {
  556. fsl,pins = <
  557. MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0
  558. >;
  559. };
  560. pinctrl_usdhc2: usdhc2grp {
  561. fsl,pins = <
  562. MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
  563. MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
  564. MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
  565. MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
  566. MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
  567. MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
  568. >;
  569. };
  570. pinctrl_usdhc3: usdhc3grp {
  571. fsl,pins = <
  572. MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
  573. MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
  574. MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
  575. MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
  576. MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
  577. MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
  578. MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
  579. MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
  580. MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
  581. MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
  582. MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
  583. MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
  584. >;
  585. };
  586. pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
  587. fsl,pins = <
  588. MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
  589. MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
  590. MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
  591. MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
  592. MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
  593. MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
  594. MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
  595. MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
  596. MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
  597. MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
  598. >;
  599. };
  600. pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
  601. fsl,pins = <
  602. MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
  603. MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
  604. MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
  605. MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
  606. MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
  607. MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
  608. MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
  609. MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
  610. MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
  611. MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
  612. >;
  613. };
  614. pinctrl_usdhc4: usdhc4grp {
  615. fsl,pins = <
  616. MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
  617. MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
  618. MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
  619. MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
  620. MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
  621. MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
  622. MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
  623. MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
  624. >;
  625. };
  626. pinctrl_wdog: wdoggrp {
  627. fsl,pins = <
  628. MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
  629. >;
  630. };
  631. };
  632. };