imx6sl-tolino-shine3.dts 7.9 KB

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  1. // SPDX-License-Identifier: (GPL-2.0)
  2. /*
  3. * Device tree for the Tolino Shine 3 ebook reader
  4. *
  5. * Name on mainboard is: 37NB-E60K00+4A4
  6. * Serials start with: E60K02 (a number also seen in
  7. * vendor kernel sources)
  8. *
  9. * This mainboard seems to be equipped with different SoCs.
  10. * In the Toline Shine 3 ebook reader it is a i.MX6SL
  11. *
  12. * Copyright 2019 Andreas Kemnade
  13. * based on works
  14. * Copyright 2016 Freescale Semiconductor, Inc.
  15. */
  16. /dts-v1/;
  17. #include <dt-bindings/input/input.h>
  18. #include <dt-bindings/gpio/gpio.h>
  19. #include "imx6sl.dtsi"
  20. #include "e60k02.dtsi"
  21. / {
  22. model = "Tolino Shine 3";
  23. compatible = "kobo,tolino-shine3", "fsl,imx6sl";
  24. };
  25. &gpio_keys {
  26. pinctrl-names = "default";
  27. pinctrl-0 = <&pinctrl_gpio_keys>;
  28. };
  29. &i2c1 {
  30. pinctrl-names = "default","sleep";
  31. pinctrl-0 = <&pinctrl_i2c1>;
  32. pinctrl-1 = <&pinctrl_i2c1_sleep>;
  33. };
  34. &i2c2 {
  35. pinctrl-names = "default","sleep";
  36. pinctrl-0 = <&pinctrl_i2c2>;
  37. pinctrl-1 = <&pinctrl_i2c2_sleep>;
  38. };
  39. &i2c3 {
  40. pinctrl-names = "default";
  41. pinctrl-0 = <&pinctrl_i2c3>;
  42. };
  43. &iomuxc {
  44. pinctrl-names = "default";
  45. pinctrl-0 = <&pinctrl_hog>;
  46. pinctrl_gpio_keys: gpio-keysgrp {
  47. fsl,pins = <
  48. MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 /* PWR_SW */
  49. MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059 /* HALL_EN */
  50. >;
  51. };
  52. pinctrl_hog: hoggrp {
  53. fsl,pins = <
  54. MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x79
  55. MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79
  56. MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x79
  57. MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x79
  58. MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79
  59. MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79
  60. MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79
  61. MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79
  62. MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79
  63. MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79
  64. MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79
  65. MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79
  66. MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79
  67. MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79
  68. MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79
  69. MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79
  70. MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79
  71. MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79
  72. MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79
  73. MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79
  74. MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79
  75. MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79
  76. MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79
  77. MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79
  78. MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79
  79. MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79
  80. MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79
  81. MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79
  82. MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79
  83. MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79
  84. MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79
  85. MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79
  86. MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x79
  87. >;
  88. };
  89. pinctrl_i2c1: i2c1grp {
  90. fsl,pins = <
  91. MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1
  92. MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1
  93. >;
  94. };
  95. pinctrl_i2c1_sleep: i2c1grp-sleep {
  96. fsl,pins = <
  97. MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1
  98. MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1
  99. >;
  100. };
  101. pinctrl_i2c2: i2c2grp {
  102. fsl,pins = <
  103. MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1
  104. MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1
  105. >;
  106. };
  107. pinctrl_i2c2_sleep: i2c2grp-sleep {
  108. fsl,pins = <
  109. MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1
  110. MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1
  111. >;
  112. };
  113. pinctrl_i2c3: i2c3grp {
  114. fsl,pins = <
  115. MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1
  116. MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1
  117. >;
  118. };
  119. pinctrl_led: ledgrp {
  120. fsl,pins = <
  121. MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x17059
  122. >;
  123. };
  124. pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp {
  125. fsl,pins = <
  126. MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 /* HWEN */
  127. >;
  128. };
  129. pinctrl_ricoh_gpio: ricoh_gpiogrp {
  130. fsl,pins = <
  131. MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */
  132. MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */
  133. MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */
  134. >;
  135. };
  136. pinctrl_uart1: uart1grp {
  137. fsl,pins = <
  138. MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
  139. MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
  140. >;
  141. };
  142. pinctrl_uart4: uart4grp {
  143. fsl,pins = <
  144. MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1
  145. MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1
  146. >;
  147. };
  148. pinctrl_usbotg1: usbotg1grp {
  149. fsl,pins = <
  150. MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
  151. >;
  152. };
  153. pinctrl_usdhc2: usdhc2grp {
  154. fsl,pins = <
  155. MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
  156. MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059
  157. MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  158. MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  159. MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  160. MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  161. >;
  162. };
  163. pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
  164. fsl,pins = <
  165. MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
  166. MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9
  167. MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
  168. MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
  169. MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
  170. MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
  171. >;
  172. };
  173. pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
  174. fsl,pins = <
  175. MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
  176. MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9
  177. MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
  178. MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
  179. MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
  180. MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
  181. >;
  182. };
  183. pinctrl_usdhc2_sleep: usdhc2grp-sleep {
  184. fsl,pins = <
  185. MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9
  186. MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9
  187. MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9
  188. MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9
  189. MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9
  190. MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9
  191. >;
  192. };
  193. pinctrl_usdhc3: usdhc3grp {
  194. fsl,pins = <
  195. MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059
  196. MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059
  197. MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059
  198. MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059
  199. MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059
  200. MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059
  201. >;
  202. };
  203. pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
  204. fsl,pins = <
  205. MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
  206. MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9
  207. MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  208. MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  209. MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  210. MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  211. >;
  212. };
  213. pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
  214. fsl,pins = <
  215. MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
  216. MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9
  217. MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  218. MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  219. MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  220. MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  221. >;
  222. };
  223. pinctrl_usdhc3_sleep: usdhc3grp-sleep {
  224. fsl,pins = <
  225. MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1
  226. MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1
  227. MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1
  228. MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1
  229. MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1
  230. MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1
  231. >;
  232. };
  233. pinctrl_wifi_power: wifi-powergrp {
  234. fsl,pins = <
  235. MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */
  236. >;
  237. };
  238. pinctrl_wifi_reset: wifi-resetgrp {
  239. fsl,pins = <
  240. MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */
  241. >;
  242. };
  243. };
  244. &leds {
  245. pinctrl-names = "default";
  246. pinctrl-0 = <&pinctrl_led>;
  247. };
  248. &lm3630a {
  249. pinctrl-names = "default";
  250. pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>;
  251. };
  252. &reg_wifi {
  253. pinctrl-names = "default";
  254. pinctrl-0 = <&pinctrl_wifi_power>;
  255. };
  256. &reg_vdd1p1 {
  257. vin-supply = <&dcdc2_reg>;
  258. };
  259. &reg_vdd2p5 {
  260. vin-supply = <&dcdc2_reg>;
  261. };
  262. &ricoh619 {
  263. pinctrl-names = "default";
  264. pinctrl-0 = <&pinctrl_ricoh_gpio>;
  265. };
  266. &uart1 {
  267. pinctrl-names = "default";
  268. pinctrl-0 = <&pinctrl_uart1>;
  269. };
  270. &uart4 {
  271. pinctrl-names = "default";
  272. pinctrl-0 = <&pinctrl_uart4>;
  273. };
  274. &usdhc2 {
  275. pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
  276. pinctrl-0 = <&pinctrl_usdhc2>;
  277. pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
  278. pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
  279. pinctrl-3 = <&pinctrl_usdhc2_sleep>;
  280. };
  281. &usdhc3 {
  282. pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
  283. pinctrl-0 = <&pinctrl_usdhc3>;
  284. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  285. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  286. pinctrl-3 = <&pinctrl_usdhc3_sleep>;
  287. };
  288. &wifi_pwrseq {
  289. pinctrl-names = "default";
  290. pinctrl-0 = <&pinctrl_wifi_reset>;
  291. };