imx6qdl-wandboard.dtsi 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Fabio Estevam <[email protected]>
  6. */
  7. #include <dt-bindings/gpio/gpio.h>
  8. / {
  9. chosen {
  10. stdout-path = &uart1;
  11. };
  12. sound {
  13. compatible = "fsl,imx6-wandboard-sgtl5000",
  14. "fsl,imx-audio-sgtl5000";
  15. model = "imx6-wandboard-sgtl5000";
  16. ssi-controller = <&ssi1>;
  17. audio-codec = <&codec>;
  18. audio-routing =
  19. "MIC_IN", "Mic Jack",
  20. "Mic Jack", "Mic Bias",
  21. "Headphone Jack", "HP_OUT";
  22. mux-int-port = <1>;
  23. mux-ext-port = <3>;
  24. };
  25. sound-spdif {
  26. compatible = "fsl,imx-audio-spdif";
  27. model = "imx-spdif";
  28. spdif-controller = <&spdif>;
  29. spdif-out;
  30. };
  31. reg_1p5v: regulator-1p5v {
  32. compatible = "regulator-fixed";
  33. regulator-name = "1P5V";
  34. regulator-min-microvolt = <1500000>;
  35. regulator-max-microvolt = <1500000>;
  36. regulator-always-on;
  37. };
  38. reg_1p8v: regulator-1p8v {
  39. compatible = "regulator-fixed";
  40. regulator-name = "1P8V";
  41. regulator-min-microvolt = <1800000>;
  42. regulator-max-microvolt = <1800000>;
  43. regulator-always-on;
  44. };
  45. reg_2p8v: regulator-2p8v {
  46. compatible = "regulator-fixed";
  47. regulator-name = "2P8V";
  48. regulator-min-microvolt = <2800000>;
  49. regulator-max-microvolt = <2800000>;
  50. regulator-always-on;
  51. };
  52. reg_2p5v: regulator-2p5v {
  53. compatible = "regulator-fixed";
  54. regulator-name = "2P5V";
  55. regulator-min-microvolt = <2500000>;
  56. regulator-max-microvolt = <2500000>;
  57. regulator-always-on;
  58. };
  59. reg_3p3v: regulator-3p3v {
  60. compatible = "regulator-fixed";
  61. regulator-name = "3P3V";
  62. regulator-min-microvolt = <3300000>;
  63. regulator-max-microvolt = <3300000>;
  64. regulator-always-on;
  65. };
  66. reg_usb_otg_vbus: regulator-usbotgvbus {
  67. compatible = "regulator-fixed";
  68. regulator-name = "usb_otg_vbus";
  69. regulator-min-microvolt = <5000000>;
  70. regulator-max-microvolt = <5000000>;
  71. pinctrl-names = "default";
  72. pinctrl-0 = <&pinctrl_usbotgvbus>;
  73. gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
  74. };
  75. };
  76. &audmux {
  77. pinctrl-names = "default";
  78. pinctrl-0 = <&pinctrl_audmux>;
  79. status = "okay";
  80. };
  81. &hdmi {
  82. ddc-i2c-bus = <&i2c1>;
  83. status = "okay";
  84. };
  85. &i2c1 {
  86. clock-frequency = <100000>;
  87. pinctrl-names = "default", "gpio";
  88. pinctrl-0 = <&pinctrl_i2c1>;
  89. pinctrl-1 = <&pinctrl_i2c1_gpio>;
  90. scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  91. sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  92. status = "okay";
  93. };
  94. &i2c2 {
  95. clock-frequency = <100000>;
  96. pinctrl-names = "default", "gpio";
  97. pinctrl-0 = <&pinctrl_i2c2>;
  98. pinctrl-1 = <&pinctrl_i2c2_gpio>;
  99. scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  100. sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  101. status = "okay";
  102. codec: sgtl5000@a {
  103. pinctrl-names = "default";
  104. pinctrl-0 = <&pinctrl_mclk>;
  105. compatible = "fsl,sgtl5000";
  106. reg = <0x0a>;
  107. clocks = <&clks IMX6QDL_CLK_CKO>;
  108. VDDA-supply = <&reg_2p5v>;
  109. VDDIO-supply = <&reg_3p3v>;
  110. lrclk-strength = <3>;
  111. };
  112. camera@3c {
  113. compatible = "ovti,ov5645";
  114. pinctrl-names = "default";
  115. pinctrl-0 = <&pinctrl_ov5645>;
  116. reg = <0x3c>;
  117. clocks = <&clks IMX6QDL_CLK_CKO2>;
  118. clock-names = "xclk";
  119. clock-frequency = <24000000>;
  120. vdddo-supply = <&reg_1p8v>;
  121. vdda-supply = <&reg_2p8v>;
  122. vddd-supply = <&reg_1p5v>;
  123. enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
  124. reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
  125. port {
  126. ov5645_to_mipi_csi2: endpoint {
  127. remote-endpoint = <&mipi_csi2_in>;
  128. clock-lanes = <0>;
  129. data-lanes = <1 2>;
  130. };
  131. };
  132. };
  133. };
  134. &iomuxc {
  135. pinctrl-names = "default";
  136. imx6qdl-wandboard {
  137. pinctrl_audmux: audmuxgrp {
  138. fsl,pins = <
  139. MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
  140. MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
  141. MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
  142. MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
  143. >;
  144. };
  145. pinctrl_enet: enetgrp {
  146. fsl,pins = <
  147. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  148. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  149. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  150. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  151. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  152. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  153. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  154. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  155. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  156. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  157. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  158. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  159. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  160. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  161. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  162. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  163. >;
  164. };
  165. pinctrl_i2c1: i2c1grp {
  166. fsl,pins = <
  167. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  168. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  169. >;
  170. };
  171. pinctrl_i2c1_gpio: i2c1gpiogrp {
  172. fsl,pins = <
  173. MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b0
  174. MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b0
  175. >;
  176. };
  177. pinctrl_i2c2: i2c2grp {
  178. fsl,pins = <
  179. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  180. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  181. >;
  182. };
  183. pinctrl_i2c2_gpio: i2c2gpiogrp {
  184. fsl,pins = <
  185. MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b0
  186. MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b0
  187. >;
  188. };
  189. pinctrl_mclk: mclkgrp {
  190. fsl,pins = <
  191. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
  192. >;
  193. };
  194. pinctrl_ov5645: ov5645grp {
  195. fsl,pins = <
  196. MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0
  197. MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
  198. MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
  199. >;
  200. };
  201. pinctrl_spdif: spdifgrp {
  202. fsl,pins = <
  203. MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
  204. >;
  205. };
  206. pinctrl_uart1: uart1grp {
  207. fsl,pins = <
  208. MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
  209. MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  210. >;
  211. };
  212. pinctrl_uart3: uart3grp {
  213. fsl,pins = <
  214. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  215. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  216. MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
  217. MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
  218. >;
  219. };
  220. pinctrl_usbotg: usbotggrp {
  221. fsl,pins = <
  222. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  223. >;
  224. };
  225. pinctrl_usbotgvbus: usbotgvbusgrp {
  226. fsl,pins = <
  227. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0
  228. >;
  229. };
  230. pinctrl_usdhc1: usdhc1grp {
  231. fsl,pins = <
  232. MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
  233. MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
  234. MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
  235. MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
  236. MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
  237. MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
  238. >;
  239. };
  240. pinctrl_usdhc2: usdhc2grp {
  241. fsl,pins = <
  242. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  243. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  244. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  245. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  246. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  247. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  248. >;
  249. };
  250. pinctrl_usdhc3: usdhc3grp {
  251. fsl,pins = <
  252. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  253. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  254. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  255. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  256. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  257. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  258. >;
  259. };
  260. };
  261. };
  262. &fec {
  263. pinctrl-names = "default";
  264. pinctrl-0 = <&pinctrl_enet>;
  265. phy-mode = "rgmii-id";
  266. phy-handle = <&ethphy>;
  267. phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
  268. status = "okay";
  269. mdio {
  270. #address-cells = <1>;
  271. #size-cells = <0>;
  272. ethphy: ethernet-phy@1 {
  273. reg = <1>;
  274. qca,clk-out-frequency = <125000000>;
  275. };
  276. };
  277. };
  278. &mipi_csi {
  279. status = "okay";
  280. port@0 {
  281. reg = <0>;
  282. mipi_csi2_in: endpoint {
  283. remote-endpoint = <&ov5645_to_mipi_csi2>;
  284. clock-lanes = <0>;
  285. data-lanes = <1 2>;
  286. };
  287. };
  288. };
  289. &spdif {
  290. pinctrl-names = "default";
  291. pinctrl-0 = <&pinctrl_spdif>;
  292. status = "okay";
  293. };
  294. &ssi1 {
  295. status = "okay";
  296. };
  297. &uart1 {
  298. pinctrl-names = "default";
  299. pinctrl-0 = <&pinctrl_uart1>;
  300. status = "okay";
  301. };
  302. &uart3 {
  303. pinctrl-names = "default";
  304. pinctrl-0 = <&pinctrl_uart3>;
  305. uart-has-rtscts;
  306. status = "okay";
  307. };
  308. &usbh1 {
  309. status = "okay";
  310. };
  311. &usbotg {
  312. vbus-supply = <&reg_usb_otg_vbus>;
  313. pinctrl-names = "default";
  314. pinctrl-0 = <&pinctrl_usbotg>;
  315. disable-over-current;
  316. dr_mode = "otg";
  317. status = "okay";
  318. };
  319. &usdhc1 {
  320. pinctrl-names = "default";
  321. pinctrl-0 = <&pinctrl_usdhc1>;
  322. cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
  323. status = "okay";
  324. };
  325. &usdhc3 {
  326. pinctrl-names = "default";
  327. pinctrl-0 = <&pinctrl_usdhc3>;
  328. cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
  329. status = "okay";
  330. };