imx6qdl-vicut1.dtsi 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /*
  3. * Copyright (c) 2014 Protonic Holland
  4. * Copyright (c) 2020 Oleksij Rempel <[email protected]>, Pengutronix
  5. */
  6. #include <dt-bindings/display/sdtv-standards.h>
  7. #include <dt-bindings/gpio/gpio.h>
  8. #include <dt-bindings/input/input.h>
  9. #include <dt-bindings/leds/common.h>
  10. #include <dt-bindings/media/tvp5150.h>
  11. #include <dt-bindings/sound/fsl-imx-audmux.h>
  12. / {
  13. chosen {
  14. stdout-path = &uart4;
  15. };
  16. backlight_lcd: backlight {
  17. compatible = "pwm-backlight";
  18. pinctrl-names = "default";
  19. pinctrl-0 = <&pinctrl_backlight>;
  20. pwms = <&pwm1 0 5000000 0>;
  21. brightness-levels = <0 16 64 255>;
  22. num-interpolated-steps = <16>;
  23. default-brightness-level = <48>;
  24. power-supply = <&reg_3v3>;
  25. enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
  26. };
  27. backlight_led: backlight-led {
  28. compatible = "pwm-backlight";
  29. pwms = <&pwm3 0 5000000 0>;
  30. brightness-levels = <0 16 64 255>;
  31. num-interpolated-steps = <16>;
  32. default-brightness-level = <48>;
  33. power-supply = <&reg_3v3>;
  34. };
  35. /* only for backwards compatibility with old HW */
  36. backlight_isb: backlight-isb {
  37. compatible = "pwm-backlight";
  38. pwms = <&pwm2 0 5000000 0>;
  39. brightness-levels = <0 8 48 255>;
  40. num-interpolated-steps = <5>;
  41. default-brightness-level = <0>;
  42. power-supply = <&reg_3v3>;
  43. };
  44. connector {
  45. compatible = "composite-video-connector";
  46. label = "Composite0";
  47. sdtv-standards = <SDTV_STD_PAL_B>;
  48. port {
  49. comp0_out: endpoint {
  50. remote-endpoint = <&tvp5150_comp0_in>;
  51. };
  52. };
  53. };
  54. counter-0 {
  55. compatible = "interrupt-counter";
  56. pinctrl-names = "default";
  57. pinctrl-0 = <&pinctrl_counter0>;
  58. gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
  59. };
  60. counter-1 {
  61. compatible = "interrupt-counter";
  62. pinctrl-names = "default";
  63. pinctrl-0 = <&pinctrl_counter1>;
  64. gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
  65. };
  66. counter-2 {
  67. compatible = "interrupt-counter";
  68. pinctrl-names = "default";
  69. pinctrl-0 = <&pinctrl_counter2>;
  70. gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
  71. };
  72. leds {
  73. compatible = "gpio-leds";
  74. pinctrl-names = "default";
  75. pinctrl-0 = <&pinctrl_leds>;
  76. led-0 {
  77. label = "debug0";
  78. function = LED_FUNCTION_HEARTBEAT;
  79. gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
  80. linux,default-trigger = "heartbeat";
  81. };
  82. led-1 {
  83. label = "debug1";
  84. function = LED_FUNCTION_DISK;
  85. gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  86. linux,default-trigger = "disk-activity";
  87. };
  88. led-2 {
  89. label = "power_led";
  90. function = LED_FUNCTION_POWER;
  91. gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
  92. default-state = "on";
  93. };
  94. led-3 {
  95. label = "isb_led";
  96. function = LED_FUNCTION_POWER;
  97. gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
  98. default-state = "on";
  99. };
  100. };
  101. reg_1v8: regulator-1v8 {
  102. compatible = "regulator-fixed";
  103. regulator-name = "1v8";
  104. regulator-min-microvolt = <1800000>;
  105. regulator-max-microvolt = <1800000>;
  106. };
  107. reg_3v3: regulator-3v3 {
  108. compatible = "regulator-fixed";
  109. regulator-name = "3v3";
  110. regulator-min-microvolt = <3300000>;
  111. regulator-max-microvolt = <3300000>;
  112. };
  113. reg_otg_vbus: regulator-otg-vbus {
  114. compatible = "regulator-fixed";
  115. regulator-name = "otg-vbus";
  116. regulator-min-microvolt = <5000000>;
  117. regulator-max-microvolt = <5000000>;
  118. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  119. enable-active-high;
  120. };
  121. sound {
  122. compatible = "simple-audio-card";
  123. simple-audio-card,name = "prti6q-sgtl5000";
  124. simple-audio-card,format = "i2s";
  125. simple-audio-card,widgets =
  126. "Microphone", "Microphone Jack",
  127. "Line", "Line In Jack",
  128. "Headphone", "Headphone Jack",
  129. "Speaker", "External Speaker";
  130. simple-audio-card,routing =
  131. "MIC_IN", "Microphone Jack",
  132. "LINE_IN", "Line In Jack",
  133. "Headphone Jack", "HP_OUT",
  134. "External Speaker", "LINE_OUT";
  135. simple-audio-card,cpu {
  136. sound-dai = <&ssi1>;
  137. system-clock-frequency = <0>; /* Do NOT call fsl_ssi_set_dai_sysclk! */
  138. };
  139. simple-audio-card,codec {
  140. sound-dai = <&codec>;
  141. bitclock-master;
  142. frame-master;
  143. };
  144. };
  145. thermal-zones {
  146. chassis-thermal {
  147. polling-delay = <20000>;
  148. polling-delay-passive = <0>;
  149. thermal-sensors = <&tsens0>;
  150. };
  151. };
  152. };
  153. &audmux {
  154. pinctrl-names = "default";
  155. pinctrl-0 = <&pinctrl_audmux>;
  156. status = "okay";
  157. mux-ssi1 {
  158. fsl,audmux-port = <0>;
  159. fsl,port-config = <
  160. IMX_AUDMUX_V2_PTCR_SYN 0
  161. IMX_AUDMUX_V2_PTCR_TFSEL(2) 0
  162. IMX_AUDMUX_V2_PTCR_TCSEL(2) 0
  163. IMX_AUDMUX_V2_PTCR_TFSDIR 0
  164. IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2)
  165. >;
  166. };
  167. mux-pins3 {
  168. fsl,audmux-port = <2>;
  169. fsl,port-config = <
  170. IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0)
  171. 0 IMX_AUDMUX_V2_PDCR_TXRXEN
  172. >;
  173. };
  174. };
  175. &can1 {
  176. pinctrl-names = "default";
  177. pinctrl-0 = <&pinctrl_can1>;
  178. termination-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
  179. termination-ohms = <150>;
  180. status = "okay";
  181. };
  182. &can2 {
  183. pinctrl-names = "default";
  184. pinctrl-0 = <&pinctrl_can2>;
  185. status = "okay";
  186. };
  187. &clks {
  188. assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>;
  189. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
  190. };
  191. &ecspi1 {
  192. cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
  193. pinctrl-names = "default";
  194. pinctrl-0 = <&pinctrl_ecspi1>;
  195. status = "okay";
  196. flash@0 {
  197. compatible = "jedec,spi-nor";
  198. reg = <0>;
  199. spi-max-frequency = <20000000>;
  200. };
  201. };
  202. &gpio2 {
  203. gpio-line-names =
  204. "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "",
  205. "", "LED_PWM", "", "", "",
  206. "", "", "",
  207. "", "", "", "", "", "ISB_IN2", "ISB_nIN1", "ON_SWITCH",
  208. "POWER_LED", "", "", "", "", "", "", "";
  209. };
  210. &gpio3 {
  211. gpio-line-names =
  212. "", "", "", "", "", "", "", "",
  213. "", "", "", "", "", "", "", "",
  214. "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1",
  215. "CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ",
  216. "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0",
  217. "YACO_RESET";
  218. };
  219. &gpio7 {
  220. gpio-line-names =
  221. "EMMC_DAT5", "EMMC_DAT4", "EMMC_CMD", "EMMC_CLK", "EMMC_DAT0",
  222. "EMMC_DAT1", "EMMC_DAT2", "EMMC_DAT3",
  223. "EMMC_RST", "", "", "", "CAM_DETECT", "", "", "",
  224. "", "EMMC_DAT7", "EMMC_DAT6", "", "", "", "", "",
  225. "", "", "", "", "", "", "", "";
  226. };
  227. &i2c1 {
  228. clock-frequency = <100000>;
  229. pinctrl-names = "default";
  230. pinctrl-0 = <&pinctrl_i2c1>;
  231. status = "okay";
  232. codec: audio-codec@a {
  233. compatible = "fsl,sgtl5000";
  234. reg = <0xa>;
  235. #sound-dai-cells = <0>;
  236. clocks = <&clks 201>;
  237. VDDA-supply = <&reg_3v3>;
  238. VDDIO-supply = <&reg_3v3>;
  239. VDDD-supply = <&reg_1v8>;
  240. };
  241. video-decoder@5c {
  242. compatible = "ti,tvp5150";
  243. reg = <0x5c>;
  244. #address-cells = <1>;
  245. #size-cells = <0>;
  246. port@0 {
  247. reg = <0>;
  248. tvp5150_comp0_in: endpoint {
  249. remote-endpoint = <&comp0_out>;
  250. };
  251. };
  252. /* Output port 2 is video output pad */
  253. port@2 {
  254. reg = <2>;
  255. tvp5151_to_ipu1_csi0_mux: endpoint {
  256. remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
  257. };
  258. };
  259. };
  260. };
  261. &i2c3 {
  262. clock-frequency = <100000>;
  263. pinctrl-names = "default";
  264. pinctrl-0 = <&pinctrl_i2c3>;
  265. status = "okay";
  266. adc@49 {
  267. compatible = "ti,ads1015";
  268. reg = <0x49>;
  269. #address-cells = <1>;
  270. #size-cells = <0>;
  271. channel@4 {
  272. reg = <4>;
  273. ti,gain = <3>;
  274. ti,datarate = <3>;
  275. };
  276. channel@5 {
  277. reg = <5>;
  278. ti,gain = <3>;
  279. ti,datarate = <3>;
  280. };
  281. channel@6 {
  282. reg = <6>;
  283. ti,gain = <3>;
  284. ti,datarate = <3>;
  285. };
  286. channel@7 {
  287. reg = <7>;
  288. ti,gain = <3>;
  289. ti,datarate = <3>;
  290. };
  291. };
  292. rtc@51 {
  293. compatible = "nxp,pcf8563";
  294. reg = <0x51>;
  295. };
  296. tsens0: temperature-sensor@70 {
  297. compatible = "ti,tmp103";
  298. reg = <0x70>;
  299. #thermal-sensor-cells = <0>;
  300. };
  301. };
  302. &ipu1_csi0 {
  303. pinctrl-names = "default";
  304. pinctrl-0 = <&pinctrl_ipu1_csi0>;
  305. status = "okay";
  306. };
  307. &ipu1_csi0_mux_from_parallel_sensor {
  308. remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>;
  309. };
  310. &ldb {
  311. status = "okay";
  312. lvds-channel@0 {
  313. status = "okay";
  314. port@4 {
  315. reg = <4>;
  316. lvds0_out: endpoint {
  317. remote-endpoint = <&panel_in>;
  318. };
  319. };
  320. };
  321. };
  322. &pwm1 {
  323. pinctrl-names = "default";
  324. pinctrl-0 = <&pinctrl_pwm1>;
  325. status = "okay";
  326. };
  327. &pwm2 {
  328. pinctrl-names = "default";
  329. pinctrl-0 = <&pinctrl_pwm2>;
  330. status = "okay";
  331. };
  332. &pwm3 {
  333. pinctrl-names = "default";
  334. pinctrl-0 = <&pinctrl_pwm3>;
  335. status = "okay";
  336. };
  337. &ssi1 {
  338. #sound-dai-cells = <0>;
  339. fsl,mode = "ac97-slave";
  340. status = "okay";
  341. };
  342. &uart1 {
  343. pinctrl-names = "default";
  344. pinctrl-0 = <&pinctrl_uart1>;
  345. status = "okay";
  346. };
  347. &uart3 {
  348. pinctrl-names = "default";
  349. pinctrl-0 = <&pinctrl_uart3>;
  350. status = "okay";
  351. };
  352. &uart4 {
  353. pinctrl-names = "default";
  354. pinctrl-0 = <&pinctrl_uart4>;
  355. status = "okay";
  356. };
  357. &uart5 {
  358. pinctrl-names = "default";
  359. pinctrl-0 = <&pinctrl_uart5>;
  360. status = "okay";
  361. };
  362. &usbh1 {
  363. pinctrl-names = "default";
  364. phy_type = "utmi";
  365. dr_mode = "host";
  366. status = "okay";
  367. };
  368. &usbotg {
  369. vbus-supply = <&reg_otg_vbus>;
  370. pinctrl-names = "default";
  371. pinctrl-0 = <&pinctrl_usbotg>;
  372. phy_type = "utmi";
  373. dr_mode = "host";
  374. disable-over-current;
  375. status = "okay";
  376. };
  377. &usdhc1 {
  378. pinctrl-names = "default";
  379. pinctrl-0 = <&pinctrl_usdhc1>;
  380. cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
  381. no-1-8-v;
  382. disable-wp;
  383. cap-sd-highspeed;
  384. no-mmc;
  385. no-sdio;
  386. status = "okay";
  387. };
  388. &usdhc3 {
  389. pinctrl-names = "default";
  390. pinctrl-0 = <&pinctrl_usdhc3>;
  391. bus-width = <8>;
  392. no-1-8-v;
  393. non-removable;
  394. no-sd;
  395. no-sdio;
  396. status = "okay";
  397. };
  398. &iomuxc {
  399. pinctrl-names = "default";
  400. pinctrl-0 = <&pinctrl_hog>;
  401. pinctrl_audmux: audmuxgrp {
  402. fsl,pins = <
  403. /* SGTL5000 sys_mclk */
  404. MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0
  405. MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
  406. MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
  407. MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
  408. MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
  409. >;
  410. };
  411. pinctrl_backlight: backlightgrp {
  412. fsl,pins = <
  413. MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0
  414. >;
  415. };
  416. pinctrl_can1: can1grp {
  417. fsl,pins = <
  418. MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000
  419. MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008
  420. /* CAN1_SR */
  421. MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008
  422. /* CAN1_TERM */
  423. MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088
  424. >;
  425. };
  426. pinctrl_can2: can2grp {
  427. fsl,pins = <
  428. MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000
  429. MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008
  430. /* CAN2_SR */
  431. MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008
  432. >;
  433. };
  434. pinctrl_counter0: counter0grp {
  435. fsl,pins = <
  436. MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000
  437. >;
  438. };
  439. pinctrl_counter1: counter1grp {
  440. fsl,pins = <
  441. MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000
  442. >;
  443. };
  444. pinctrl_counter2: counter2grp {
  445. fsl,pins = <
  446. MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000
  447. >;
  448. };
  449. pinctrl_ecspi1: ecspi1grp {
  450. fsl,pins = <
  451. MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
  452. MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
  453. MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
  454. /* CS */
  455. MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
  456. >;
  457. };
  458. pinctrl_hog: hoggrp {
  459. fsl,pins = <
  460. /* ITU656_nRESET */
  461. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
  462. /* CAM1_MIRROR */
  463. MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0
  464. /* CAM2_MIRROR */
  465. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0
  466. /* CAM_nDETECT */
  467. MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
  468. /* ISB_IN1 */
  469. MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0
  470. /* ISB_nIN2 */
  471. MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0
  472. /* WARN_LIGHT */
  473. MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0
  474. /* ON2_FB */
  475. MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0
  476. /* YACO_nIRQ */
  477. MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0
  478. /* YACO_BOOT0 */
  479. MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0
  480. /* YACO_nRESET */
  481. MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
  482. /* FORCE_ON1 */
  483. MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
  484. /* AUDIO_nRESET */
  485. MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0
  486. /* ITU656_nPDN */
  487. MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0
  488. /* New in HW revision 1 */
  489. /* ON1_FB */
  490. MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0
  491. /* DIP1_FB */
  492. MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
  493. >;
  494. };
  495. pinctrl_i2c1: i2c1grp {
  496. fsl,pins = <
  497. MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1
  498. MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1
  499. >;
  500. };
  501. pinctrl_i2c3: i2c3grp {
  502. fsl,pins = <
  503. MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
  504. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  505. >;
  506. };
  507. pinctrl_ipu1_csi0: ipu1csi0grp {
  508. fsl,pins = <
  509. MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
  510. MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
  511. MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
  512. MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
  513. MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
  514. MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
  515. MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
  516. MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
  517. MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
  518. >;
  519. };
  520. pinctrl_leds: ledsgrp {
  521. fsl,pins = <
  522. /* DEBUG0 */
  523. MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0
  524. /* DEBUG1 */
  525. MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0
  526. /* POWER_LED */
  527. MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0
  528. /* ISB_LED */
  529. MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0
  530. >;
  531. };
  532. pinctrl_pwm1: pwm1grp {
  533. fsl,pins = <
  534. MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0
  535. >;
  536. };
  537. pinctrl_pwm2: pwm2grp {
  538. fsl,pins = <
  539. MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b0
  540. >;
  541. };
  542. pinctrl_pwm3: pwm3grp {
  543. fsl,pins = <
  544. MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0
  545. >;
  546. };
  547. /* YaCO AUX Uart */
  548. pinctrl_uart1: uart1grp {
  549. fsl,pins = <
  550. MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
  551. MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  552. >;
  553. };
  554. /* YaCO Touchscreen UART */
  555. pinctrl_uart3: uart3grp {
  556. fsl,pins = <
  557. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  558. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  559. >;
  560. };
  561. pinctrl_uart4: uart4grp {
  562. fsl,pins = <
  563. MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
  564. MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
  565. >;
  566. };
  567. pinctrl_uart5: uart5grp {
  568. fsl,pins = <
  569. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  570. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  571. >;
  572. };
  573. pinctrl_usbotg: usbotggrp {
  574. fsl,pins = <
  575. MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
  576. /* power enable, high active */
  577. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
  578. >;
  579. };
  580. pinctrl_usdhc1: usdhc1grp {
  581. fsl,pins = <
  582. MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9
  583. MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
  584. MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
  585. MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
  586. MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
  587. MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
  588. MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0
  589. >;
  590. };
  591. pinctrl_usdhc3: usdhc3grp {
  592. fsl,pins = <
  593. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099
  594. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099
  595. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099
  596. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099
  597. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099
  598. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099
  599. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099
  600. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099
  601. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099
  602. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099
  603. MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
  604. >;
  605. };
  606. };